diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/cae_test/general')
419 files changed, 33578 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/addition.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/addition.cpp new file mode 100644 index 000000000..10eb25125 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/addition.cpp @@ -0,0 +1,165 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + addition.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-12 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "addition.h" + +void addition::entry(){ + + int tmp1; + sc_bigint<4> tmp2; + sc_biguint<4> tmp3; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 1; + tmp5 = tmp5 + 1; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + // execute increment post-operation and write outputs + out_value1.write(tmp1++); + out_value2.write(tmp2++); + out_value3.write(tmp3++); + out_value4.write(tmp4++); + out_value5.write(tmp5++); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + // execute increment pre-operation and write outputs + out_value1.write(++tmp1); + out_value2.write(++tmp2); + out_value3.write(++tmp3); + out_value4.write(++tmp4); + out_value5.write(++tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute operations with overflow + tmp1 = tmp1 + 254; + tmp2 = tmp2 + 254; + tmp3 = tmp3 + 254; + tmp4 = tmp4 + 254; + tmp5 = tmp5 + 254; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute operations with self assignment + tmp1 += 254; + tmp2 += 254; + tmp3 += 254; + tmp4 += 254; + tmp5 += 254; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute operations with signed and unsigned mix and mixed bit width + tmp1 = (tmp3 + tmp2).to_int(); + tmp2 = tmp2 + tmp4; + tmp3 = tmp3 + tmp5; + tmp4 = tmp4 + tmp5; + tmp5 = tmp4 + tmp5; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/addition.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/addition.f new file mode 100644 index 000000000..b4ba6bd0f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/addition.f @@ -0,0 +1,4 @@ +addition/stimulus.cpp +addition/display.cpp +addition/addition.cpp +addition/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/addition.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/addition.h new file mode 100644 index 000000000..899bc9983 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/addition.h @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + addition.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-12 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( addition ) +{ + SC_HAS_PROCESS( addition ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; + const sc_signal_bool_vector4& in_value2; + const sc_signal_bool_vector4& in_value3; + const sc_signal_bool_vector8& in_value4; + const sc_signal_bool_vector8& in_value5; + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal_bool_vector4& out_value2; + sc_signal_bool_vector4& out_value3; + sc_signal_bool_vector8& out_value4; + sc_signal_bool_vector8& out_value5; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + addition( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector4& IN_VALUE3, + const sc_signal_bool_vector8& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector4& OUT_VALUE3, + sc_signal_bool_vector8& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), // connection definition + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/common.h new file mode 100644 index 000000000..8a560ac63 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/display.cpp new file mode 100644 index 000000000..38e5c8b61 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/display.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-12 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up. + while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data3.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/display.h new file mode 100644 index 000000000..4c20196ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/display.h @@ -0,0 +1,77 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-12 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal_bool_vector4& in_data2; // Input port + const sc_signal_bool_vector4& in_data3; // Input port + const sc_signal_bool_vector8& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal_bool_vector4& IN_DATA2, + const sc_signal_bool_vector4& IN_DATA3, + const sc_signal_bool_vector8& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/golden/addition.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/golden/addition.log new file mode 100644 index 000000000..ee6b81b72 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/golden/addition.log @@ -0,0 +1,31 @@ +SystemC Simulation +Stimuli : 0 0 0 0 0 at 23 ns +Display : 1 0001 0001 00000001 00000001 at 27 ns +Display : 1 0001 0001 00000001 00000001 at 29 ns +Display : 3 0011 0011 00000011 00000011 at 31 ns +Display : 257 0001 0001 00000001 00000001 at 34 ns +Display : 511 1111 1111 11111111 11111111 at 37 ns +Display : 14 1110 1110 11111110 11111101 at 40 ns +Stimuli : 1 1 1 1 1 at 44 ns +Display : 2 0010 0010 00000010 00000010 at 48 ns +Display : 2 0010 0010 00000010 00000010 at 50 ns +Display : 4 0100 0100 00000100 00000100 at 52 ns +Display : 258 0010 0010 00000010 00000010 at 55 ns +Display : 512 0000 0000 00000000 00000000 at 58 ns +Display : 0 0000 0000 00000000 00000000 at 61 ns +Stimuli : 2 2 2 2 2 at 65 ns +Display : 3 0011 0011 00000011 00000011 at 69 ns +Display : 3 0011 0011 00000011 00000011 at 71 ns +Display : 5 0101 0101 00000101 00000101 at 73 ns +Display : 259 0011 0011 00000011 00000011 at 76 ns +Display : 513 0001 0001 00000001 00000001 at 79 ns +Display : 2 0010 0010 00000010 00000011 at 82 ns +Stimuli : 3 3 3 3 3 at 86 ns +Display : 4 0100 0100 00000100 00000100 at 90 ns +Display : 4 0100 0100 00000100 00000100 at 92 ns +Display : 6 0110 0110 00000110 00000110 at 94 ns +Display : 260 0100 0100 00000100 00000100 at 97 ns +Display : 514 0010 0010 00000010 00000010 at 100 ns +Display : 4 0100 0100 00000100 00000110 at 103 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/main.cpp new file mode 100644 index 000000000..3e32605f9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/main.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-12 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" +#include "display.h" +#include "addition.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector4 stimulus_line3; + sc_signal_bool_vector8 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector4 result_line3; + sc_signal_bool_vector8 result_line4; + sc_signal_bool_vector8 result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + addition addition1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/stimulus.cpp new file mode 100644 index 000000000..2d43a45c4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-12 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" + +void stimulus::entry() { + int send_value1 = 0; + sc_signed send_value2(4); + sc_unsigned send_value3(4); + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value2 = 0; + send_value3 = 0; + send_value4 = 0; + send_value5 = 0; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(20); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1++; + send_value2 = send_value2+1; + send_value3 = send_value3+1; + send_value4 = send_value4+1; + send_value5 = send_value5+1; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/stimulus.h new file mode 100644 index 000000000..b73fb9d4c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/addition/stimulus.h @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-12 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal_bool_vector4& out_stimulus2; + sc_signal_bool_vector4& out_stimulus3; + sc_signal_bool_vector8& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal_bool_vector4& OUT_STIMULUS2, + sc_signal_bool_vector4& OUT_STIMULUS3, + sc_signal_bool_vector8& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.cpp new file mode 100644 index 000000000..df19755c1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.cpp @@ -0,0 +1,99 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "bitwidth.h" + +void bitwidth::entry(){ + + sc_bigint<4> tmp1; + sc_biguint<4> tmp2; + sc_bigint<6> tmp3; + sc_biguint<6> tmp4; + sc_bigint<8> tmp5; + sc_biguint<8> tmp6; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + //execute simple operations + // expected bitwidth 4 4 4 signed + tmp1 = tmp1 + tmp2; + // expected bitwidth 4 6 6 signed + tmp3 = tmp1 + tmp3; + // expected bitwidth 4 4 6 signed + tmp6 = tmp2 + tmp1; + // expected bitwidth 8 8 6 signed + tmp4 = tmp5 + tmp6; + // expected bitwidth 6 8 4 unsigned + tmp2 = tmp4 + tmp6; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.f new file mode 100644 index 000000000..53a59162e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.f @@ -0,0 +1,4 @@ +bitwidth/stimulus.cpp +bitwidth/display.cpp +bitwidth/bitwidth.cpp +bitwidth/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.h new file mode 100644 index 000000000..9ced486ea --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/bitwidth.h @@ -0,0 +1,120 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( bitwidth ) +{ + SC_HAS_PROCESS( bitwidth ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector4& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; // Input port + const sc_signal_bool_vector6& in_value3; // Input port + const sc_signal_bool_vector6& in_value4; // Input port + const sc_signal_bool_vector8& in_value5; // Input port + const sc_signal_bool_vector8& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal_bool_vector4& out_value1; // Output port + sc_signal_bool_vector4& out_value2; // Output port + sc_signal_bool_vector6& out_value3; // Output port + sc_signal_bool_vector6& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal_bool_vector8& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + bitwidth ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector4& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector6& IN_VALUE3, + const sc_signal_bool_vector6& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal_bool_vector8& IN_VALUE6, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector4& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector6& OUT_VALUE3, + sc_signal_bool_vector6& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal_bool_vector8& OUT_VALUE6, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/common.h new file mode 100644 index 000000000..2a49981d9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<6> > sc_signal_bool_vector6; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.cpp new file mode 100644 index 000000000..76acd9e62 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << in_data6.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.h new file mode 100644 index 000000000..d35bb1abc --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/display.h @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector4& in_data1; // Input port + const sc_signal_bool_vector4& in_data2; // Input port + const sc_signal_bool_vector6& in_data3; // Input port + const sc_signal_bool_vector6& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal_bool_vector8& in_data6; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector4& IN_DATA1, + const sc_signal_bool_vector4& IN_DATA2, + const sc_signal_bool_vector6& IN_DATA3, + const sc_signal_bool_vector6& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal_bool_vector8& IN_DATA6, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_data6(IN_DATA6), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/golden/bitwidth.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/golden/bitwidth.log new file mode 100644 index 000000000..d8f3d5726 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/golden/bitwidth.log @@ -0,0 +1,51 @@ +SystemC Simulation +Stimuli : 0 0 0 0 0 0 at 23 ns +Display : 0000 0000 000000 000000 00000000 00000000 at 27 ns +Stimuli : 2 2 8 8 32 32 at 44 ns +Display : 0100 1100 001100 100110 00100000 00000110 at 48 ns +Stimuli : 4 4 16 16 64 64 at 65 ns +Display : 1000 1000 001000 111100 01000000 11111100 at 69 ns +Stimuli : 6 6 24 24 96 96 at 86 ns +Display : 1100 0100 010100 100010 01100000 00000010 at 90 ns +Stimuli : -8 8 -32 32 -128 128 at 107 ns +Display : 0000 0000 100000 001000 10000000 00001000 at 111 ns +Stimuli : -6 10 -24 40 -96 160 at 128 ns +Display : 0100 1100 101100 101110 10100000 00001110 at 132 ns +Stimuli : -4 12 -16 48 -64 192 at 149 ns +Display : 1000 1000 101000 000100 11000000 00000100 at 153 ns +Stimuli : -2 14 -8 56 -32 224 at 170 ns +Display : 1100 0100 110100 101010 11100000 00001010 at 174 ns +Stimuli : 0 0 0 0 0 0 at 191 ns +Display : 0000 0000 000000 000000 00000000 00000000 at 195 ns +Stimuli : 2 2 8 8 32 32 at 212 ns +Display : 0100 1100 001100 100110 00100000 00000110 at 216 ns +Stimuli : 4 4 16 16 64 64 at 233 ns +Display : 1000 1000 001000 111100 01000000 11111100 at 237 ns +Stimuli : 6 6 24 24 96 96 at 254 ns +Display : 1100 0100 010100 100010 01100000 00000010 at 258 ns +Stimuli : -8 8 -32 32 -128 128 at 275 ns +Display : 0000 0000 100000 001000 10000000 00001000 at 279 ns +Stimuli : -6 10 -24 40 -96 160 at 296 ns +Display : 0100 1100 101100 101110 10100000 00001110 at 300 ns +Stimuli : -4 12 -16 48 -64 192 at 317 ns +Display : 1000 1000 101000 000100 11000000 00000100 at 321 ns +Stimuli : -2 14 -8 56 -32 224 at 338 ns +Display : 1100 0100 110100 101010 11100000 00001010 at 342 ns +Stimuli : 0 0 0 0 0 0 at 359 ns +Display : 0000 0000 000000 000000 00000000 00000000 at 363 ns +Stimuli : 2 2 8 8 32 32 at 380 ns +Display : 0100 1100 001100 100110 00100000 00000110 at 384 ns +Stimuli : 4 4 16 16 64 64 at 401 ns +Display : 1000 1000 001000 111100 01000000 11111100 at 405 ns +Stimuli : 6 6 24 24 96 96 at 422 ns +Display : 1100 0100 010100 100010 01100000 00000010 at 426 ns +Stimuli : -8 8 -32 32 -128 128 at 443 ns +Display : 0000 0000 100000 001000 10000000 00001000 at 447 ns +Stimuli : -6 10 -24 40 -96 160 at 464 ns +Display : 0100 1100 101100 101110 10100000 00001110 at 468 ns +Stimuli : -4 12 -16 48 -64 192 at 485 ns +Display : 1000 1000 101000 000100 11000000 00000100 at 489 ns +Stimuli : -2 14 -8 56 -32 224 at 506 ns +Display : 1100 0100 110100 101010 11100000 00001010 at 510 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/main.cpp new file mode 100644 index 000000000..238dd032a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/main.cpp @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" +#include "display.h" +#include "bitwidth.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector4 stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector6 stimulus_line3; + sc_signal_bool_vector6 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal_bool_vector8 stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal_bool_vector4 result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector6 result_line3; + sc_signal_bool_vector6 result_line4; + sc_signal_bool_vector8 result_line5; + sc_signal_bool_vector8 result_line6; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid); + + bitwidth bitwidth1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.cpp new file mode 100644 index 000000000..15546d1b2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.cpp @@ -0,0 +1,94 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" + +void stimulus::entry() { + sc_signed send_value1(4); + sc_unsigned send_value2(4); + sc_signed send_value3(6); + sc_unsigned send_value4(6); + sc_signed send_value5(8); + sc_unsigned send_value6(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value1 = 0; + send_value2 = 0; + send_value3 = 0; + send_value4 = 0; + send_value5 = 0; + send_value6 = 0; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + out_stimulus6.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(20); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_stimulus6.write( send_value6 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " + << send_value6 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+2; + send_value2 = send_value2+2; + send_value3 = send_value3+8; + send_value4 = send_value4+8; + send_value5 = send_value5+32; + send_value6 = send_value6+32; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.h new file mode 100644 index 000000000..edbd6be48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/bitwidth/stimulus.h @@ -0,0 +1,83 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-08-02 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector4& out_stimulus1; + sc_signal_bool_vector4& out_stimulus2; + sc_signal_bool_vector6& out_stimulus3; + sc_signal_bool_vector6& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal_bool_vector8& out_stimulus6; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector4& OUT_STIMULUS1, + sc_signal_bool_vector4& OUT_STIMULUS2, + sc_signal_bool_vector6& OUT_STIMULUS3, + sc_signal_bool_vector6& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal_bool_vector8& OUT_STIMULUS6, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_stimulus6(OUT_STIMULUS6), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/datatypes.cpp new file mode 100644 index 000000000..753647536 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/datatypes.cpp @@ -0,0 +1,134 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "datatypes.h" +#define true 1 +#define false 0 + +void datatypes::entry() + +{ + + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + int tmp7[2]; + char tmp8[2]; + // int tmp9[2]; + int* tmp9; + +// define sc_bool_vector + sc_bv<4> tmp10; + tmp10[3] = 0; tmp10[2] = 1; tmp10[1] = 0; tmp10[0] = 1; + +// define 2 dimentional array + sc_bv<1> tmp11[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// + +// initialization of sc_array + + tmp7[0] = 3; + tmp7[1] = 12; + tmp8[0] = 'S'; + tmp8[1] = 'C'; + tmp9 = tmp7; + tmp11[0][0] = "1"; + tmp11[1][0] = "0"; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + out_ack.write(true); + + //execute mixed data type addition operations + tmp1r = tmp1 + tmp2 + (sc_bigint<1>)tmp1.range(0, 0) ; // #### + // tmp2r = tmp6 + tmp1 + int(tmp10[2]); // treat tmp10[2] as carry in + tmp2r = tmp6 + tmp1 + tmp10[2].to_bool(); // treat tmp10[2] as carry in + tmp3r = tmp4 + tmp6; + tmp4r = ++tmp5; + // tmp4r -= int(tmp11[0][0]); + tmp4r -= tmp11[0][0].to_bool(); + tmp5r = tmp6 + tmp4; + tmp6r = tmp8[0] + tmp9[1]; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/datatypes.h new file mode 100644 index 000000000..7ce8039e3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/datatypes.h @@ -0,0 +1,123 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/display.cpp new file mode 100644 index 000000000..ef7667e69 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/display.cpp @@ -0,0 +1,49 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "display.h" + +void display::entry() { + + while(true){ + do { wait(); } while ( in_valid == false ); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/display.h new file mode 100644 index 000000000..7804753f9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/display.h @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/golden/datatypes.log new file mode 100644 index 000000000..db69787de --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/golden/datatypes.log @@ -0,0 +1,203 @@ +SystemC Simulation +Stimuli: 0 1 12345678 -123456 20000 +Display: 00000001 01010011 -123374 20000 7698 _ +Stimuli: 1 3 12345683 -123453 20006 +Display: 00000011 01011000 -123367 20006 7705 _ +Stimuli: 2 5 12345688 -123450 20012 +Display: 00000111 01011101 -123360 20012 7712 _ +Stimuli: 3 7 12345693 -123447 20018 +Display: 00001001 01100010 -123353 20018 7719 _ +Stimuli: 4 9 12345698 -123444 20024 +Display: 00001101 01100111 -123346 20024 7726 _ +Stimuli: 5 11 12345703 -123441 20030 +Display: 00001111 01101100 -123339 20030 7733 _ +Stimuli: 6 13 12345708 -123438 20036 +Display: 00010011 01110001 -123332 20036 7740 _ +Stimuli: 7 15 12345713 -123435 20042 +Display: 00010101 01110110 -123325 20042 7747 _ +Stimuli: 8 17 12345718 -123432 20048 +Display: 00011001 01111011 -123318 20048 7754 _ +Stimuli: 9 19 12345723 -123429 20054 +Display: 00011011 10000000 -123311 20054 7761 _ +Stimuli: 10 21 12345728 -123426 20060 +Display: 00011111 10000101 -123304 20060 7768 _ +Stimuli: 11 23 12345733 -123423 20066 +Display: 00100001 10001010 -123297 20066 7775 _ +Stimuli: 12 25 12345738 -123420 20072 +Display: 00100101 10001111 -123546 20072 7526 _ +Stimuli: 13 27 12345743 -123417 20078 +Display: 00100111 10010100 -123539 20078 7533 _ +Stimuli: 14 29 12345748 -123414 20084 +Display: 00101011 10011001 -123532 20084 7540 _ +Stimuli: 15 31 12345753 -123411 20090 +Display: 00101101 10011110 -123525 20090 7547 _ +Stimuli: 16 33 12345758 -123408 20096 +Display: 00110001 10100011 -123518 20096 7554 _ +Stimuli: 17 35 12345763 -123405 20102 +Display: 00110011 10101000 -123511 20102 7561 _ +Stimuli: 18 37 12345768 -123402 20108 +Display: 00110111 10101101 -123504 20108 7568 _ +Stimuli: 19 39 12345773 -123399 20114 +Display: 00111001 10110010 -123497 20114 7575 _ +Stimuli: 20 41 12345778 -123396 20120 +Display: 00111101 10110111 -123490 20120 7582 _ +Stimuli: 21 43 12345783 -123393 20126 +Display: 00111111 10111100 -123483 20126 7589 _ +Stimuli: 22 45 12345788 -123390 20132 +Display: 01000011 11000001 -123476 20132 7596 _ +Stimuli: 23 47 12345793 -123387 20138 +Display: 01000101 11000110 -123469 20138 7603 _ +Stimuli: 24 49 12345798 -123384 20144 +Display: 01001001 11001011 -123462 20144 7610 _ +Stimuli: 25 51 12345803 -123381 20150 +Display: 01001011 11010000 -123455 20150 7617 _ +Stimuli: 26 53 12345808 -123378 20156 +Display: 01001111 11010101 -123448 20156 7624 _ +Stimuli: 27 55 12345813 -123375 20162 +Display: 01010001 11011010 -123441 20162 7631 _ +Stimuli: 28 57 12345818 -123372 20168 +Display: 01010101 11011111 -123434 20168 7638 _ +Stimuli: 29 59 12345823 -123369 20174 +Display: 01010111 11100100 -123427 20174 7645 _ +Stimuli: 30 61 12345828 -123366 20180 +Display: 01011011 11101001 -123420 20180 7652 _ +Stimuli: 31 63 12345833 -123363 20186 +Display: 01011101 11101110 -123413 20186 7659 _ +Stimuli: 32 65 12345838 -123360 20192 +Display: 01100001 11110011 -123406 20192 7666 _ +Stimuli: 33 67 12345843 -123357 20198 +Display: 01100011 11111000 -123399 20198 7673 _ +Stimuli: 34 69 12345848 -123354 20204 +Display: 01100111 11111101 -123392 20204 7680 _ +Stimuli: 35 71 12345853 -123351 20210 +Display: 01101001 00000010 -123385 20210 7687 _ +Stimuli: 36 73 12345858 -123348 20216 +Display: 01101101 00000111 -123378 20216 7694 _ +Stimuli: 37 75 12345863 -123345 20222 +Display: 01101111 00001100 -123371 20222 7701 _ +Stimuli: 38 77 12345868 -123342 20228 +Display: 01110011 00010001 -123364 20228 7708 _ +Stimuli: 39 79 12345873 -123339 20234 +Display: 01110101 00010110 -123357 20234 7715 _ +Stimuli: 40 81 12345878 -123336 20240 +Display: 01111001 00011011 -123350 20240 7722 _ +Stimuli: 41 83 12345883 -123333 20246 +Display: 01111011 00100000 -123343 20246 7729 _ +Stimuli: 42 85 12345888 -123330 20252 +Display: 01111111 00100101 -123336 20252 7736 _ +Stimuli: 43 87 12345893 -123327 20258 +Display: 10000001 00101010 -123329 20258 7743 _ +Stimuli: 44 89 12345898 -123324 20264 +Display: 10000101 00101111 -123322 20264 7750 _ +Stimuli: 45 91 12345903 -123321 20270 +Display: 10000111 00110100 -123315 20270 7757 _ +Stimuli: 46 93 12345908 -123318 20276 +Display: 10001011 00111001 -123308 20276 7764 _ +Stimuli: 47 95 12345913 -123315 20282 +Display: 10001101 00111110 -123301 20282 7771 _ +Stimuli: 48 97 12345918 -123312 20288 +Display: 10010001 01000011 -123294 20288 7778 _ +Stimuli: 49 99 12345923 -123309 20294 +Display: 10010011 01001000 -123287 20294 7785 _ +Stimuli: 50 101 12345928 -123306 20300 +Display: 10010111 01001101 -123280 20300 7792 _ +Stimuli: 51 103 12345933 -123303 20306 +Display: 10011001 01010010 -123273 20306 7799 _ +Stimuli: 52 105 12345938 -123300 20312 +Display: 10011101 01010111 -123266 20312 7806 _ +Stimuli: 53 107 12345943 -123297 20318 +Display: 10011111 01011100 -123259 20318 7813 _ +Stimuli: 54 109 12345948 -123294 20324 +Display: 10100011 01100001 -123252 20324 7820 _ +Stimuli: 55 111 12345953 -123291 20330 +Display: 10100101 01100110 -123245 20330 7827 _ +Stimuli: 56 113 12345958 -123288 20336 +Display: 10101001 01101011 -123238 20336 7834 _ +Stimuli: 57 115 12345963 -123285 20342 +Display: 10101011 01110000 -123231 20342 7841 _ +Stimuli: 58 117 12345968 -123282 20348 +Display: 10101111 01110101 -123224 20348 7848 _ +Stimuli: 59 119 12345973 -123279 20354 +Display: 10110001 01111010 -123217 20354 7855 _ +Stimuli: 60 121 12345978 -123276 20360 +Display: 10110101 01111111 -123210 20360 7862 _ +Stimuli: 61 123 12345983 -123273 20366 +Display: 10110111 10000100 -123203 20366 7869 _ +Stimuli: 62 125 12345988 -123270 20372 +Display: 10111011 10001001 -123196 20372 7876 _ +Stimuli: 63 127 12345993 -123267 20378 +Display: 10111101 10001110 -123189 20378 7883 _ +Stimuli: 64 -127 12345998 -123264 20384 +Display: 11000001 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+ + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Stan Liao, Synopsys, Inc., 1999-09-21 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/stimulus.cpp new file mode 100644 index 000000000..79a2d896a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/stimulus.cpp @@ -0,0 +1,84 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + + int counter = 0; + tmp1 = "00000000"; + tmp2 = "00000001"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = 'R'; + + + while(counter<100){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " << tmp5 << " " << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 2; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp6 = tmp6 + 4; + do { wait(); } while (in_ack==false); + out_valid.write(false); + counter++; + wait(); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/stimulus.h new file mode 100644 index 000000000..689995a6a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/datatypes/stimulus.h @@ -0,0 +1,89 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/common.h new file mode 100644 index 000000000..b0b56195b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<5> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/display.cpp new file mode 100644 index 000000000..64c5ee2b4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/display.cpp @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/display.h new file mode 100644 index 000000000..21e3c27fd --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/display.h @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/golden/increment.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/golden/increment.log new file mode 100644 index 000000000..e8205e774 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/golden/increment.log @@ -0,0 +1,51 @@ +SystemC Simulation +Stimuli : 0 0 at 23 ns +Display : 3 00011 at 27 ns +Stimuli : 4 4 at 44 ns +Display : 7 00111 at 48 ns +Stimuli : 8 8 at 65 ns +Display : 11 01011 at 69 ns +Stimuli : 12 12 at 86 ns +Display : 15 01111 at 90 ns +Stimuli : 16 -16 at 107 ns +Display : 19 10011 at 111 ns +Stimuli : 20 -12 at 128 ns +Display : 23 10111 at 132 ns +Stimuli : 24 -8 at 149 ns +Display : 27 11011 at 153 ns +Stimuli : 28 -4 at 170 ns +Display : 31 11111 at 174 ns +Stimuli : 32 0 at 191 ns +Display : 35 00011 at 195 ns +Stimuli : 36 4 at 212 ns +Display : 39 00111 at 216 ns +Stimuli : 40 8 at 233 ns +Display : 43 01011 at 237 ns +Stimuli : 44 12 at 254 ns +Display : 47 01111 at 258 ns +Stimuli : 48 -16 at 275 ns +Display : 51 10011 at 279 ns +Stimuli : 52 -12 at 296 ns +Display : 55 10111 at 300 ns +Stimuli : 56 -8 at 317 ns +Display : 59 11011 at 321 ns +Stimuli : 60 -4 at 338 ns +Display : 63 11111 at 342 ns +Stimuli : 64 0 at 359 ns +Display : 67 00011 at 363 ns +Stimuli : 68 4 at 380 ns +Display : 71 00111 at 384 ns +Stimuli : 72 8 at 401 ns +Display : 75 01011 at 405 ns +Stimuli : 76 12 at 422 ns +Display : 79 01111 at 426 ns +Stimuli : 80 -16 at 443 ns +Display : 83 10011 at 447 ns +Stimuli : 84 -12 at 464 ns +Display : 87 10111 at 468 ns +Stimuli : 88 -8 at 485 ns +Display : 91 11011 at 489 ns +Stimuli : 92 -4 at 506 ns +Display : 95 11111 at 510 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/increment.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/increment.cpp new file mode 100644 index 000000000..3b32d2317 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/increment.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + increment.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "increment.h" + +void increment::entry(){ + + #define ONE 1 + const int eins = 1; + int tmp1; + sc_bigint<5> tmp2; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + + //execute simple operations + tmp1 = tmp1 + 1; + tmp1 = tmp1 + ONE; + tmp1 = tmp1 + eins; + tmp2 = tmp2 + 1; + tmp2 = tmp2 + ONE; + tmp2 = tmp2 + eins; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/increment.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/increment.f new file mode 100644 index 000000000..3e7b5f3b7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/increment.f @@ -0,0 +1,4 @@ +increment/stimulus.cpp +increment/display.cpp +increment/increment.cpp +increment/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/increment.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/increment.h new file mode 100644 index 000000000..30093ede8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/increment.h @@ -0,0 +1,96 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + increment.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( increment ) +{ + SC_HAS_PROCESS( increment ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + increment ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/main.cpp new file mode 100644 index 000000000..6189f9dc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" +#include "display.h" +#include "increment.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal_bool_vector result_line2; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + input_valid); + + increment increment1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + input_valid, + result_line1, + result_line2, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/stimulus.cpp new file mode 100644 index 000000000..9f22a9c34 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/stimulus.cpp @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" + +void stimulus::entry() +{ + int send_value1 = 0; + sc_signed send_value2(5); + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value2 = 0; + out_stimulus1.write(0); + out_stimulus2.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(20); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+4; + send_value2 = send_value2+4; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/stimulus.h new file mode 100644 index 000000000..0bda545fa --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/increment/stimulus.h @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal_bool_vector& out_stimulus2; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal_bool_vector& OUT_STIMULUS2, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/common.h new file mode 100644 index 000000000..60baad076 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/common.h @@ -0,0 +1,49 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<5> > sc_signal_bool_vector5; +typedef sc_signal<sc_bv<6> > sc_signal_bool_vector6; +typedef sc_signal<sc_bv<7> > sc_signal_bool_vector7; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/display.cpp new file mode 100644 index 000000000..b13920d6c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " + << in_data1.read() << " " + << in_data3.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/display.h new file mode 100644 index 000000000..524ee27b0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/display.h @@ -0,0 +1,77 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector4& in_data1; // Input port + const sc_signal_bool_vector5& in_data2; // Input port + const sc_signal_bool_vector6& in_data3; // Input port + const sc_signal_bool_vector7& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector4& IN_DATA1, + const sc_signal_bool_vector5& IN_DATA2, + const sc_signal_bool_vector6& IN_DATA3, + const sc_signal_bool_vector7& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/golden/sharing.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/golden/sharing.log new file mode 100644 index 000000000..dda9320f3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/golden/sharing.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 0 0 0 0 0 at 23 ns +Display : 1010 001010 001010 0001010 00001010 at 27 ns +Display : 1011 001011 001011 0010100 00001011 at 30 ns +Stimuli : 1 1 1 1 1 at 44 ns +Display : 1011 001011 001011 0001011 00001011 at 48 ns +Display : 1100 001100 001100 0010101 00001100 at 51 ns +Stimuli : 2 2 2 2 2 at 65 ns +Display : 1100 001100 001100 0001100 00001100 at 69 ns +Display : 1101 001101 001101 0010110 00001101 at 72 ns +Stimuli : 3 3 3 3 3 at 86 ns +Display : 1101 001101 001101 0001101 00001101 at 90 ns +Display : 1110 001110 001110 0010111 00001110 at 93 ns +Stimuli : 4 4 4 4 4 at 107 ns +Display : 1110 001110 001110 0001110 00001110 at 111 ns +Display : 1111 001111 001111 0011000 00001111 at 114 ns +Stimuli : 5 5 5 5 5 at 128 ns +Display : 1111 001111 001111 0001111 00001111 at 132 ns +Display : 0000 010000 010000 0011001 00010000 at 135 ns +Stimuli : 6 6 6 6 6 at 149 ns +Display : 0000 010000 010000 0010000 00010000 at 153 ns +Display : 0001 010001 010001 0011010 00010001 at 156 ns +Stimuli : 7 7 7 7 7 at 170 ns +Display : 0001 010001 010001 0010001 00010001 at 174 ns +Display : 0010 010010 010010 0011011 00010010 at 177 ns +Stimuli : -8 8 8 8 8 at 191 ns +Display : 0010 010010 010010 0010010 00010010 at 195 ns +Display : 0011 010011 010011 0011100 00010011 at 198 ns +Stimuli : -7 9 9 9 9 at 212 ns +Display : 0011 010011 010011 0010011 00010011 at 216 ns +Display : 0100 010100 010100 0011101 00010100 at 219 ns +Stimuli : -6 10 10 10 10 at 233 ns +Display : 0100 010100 010100 0010100 00010100 at 237 ns +Display : 0101 010101 010101 0011110 00010101 at 240 ns +Stimuli : -5 11 11 11 11 at 254 ns +Display : 0101 010101 010101 0010101 00010101 at 258 ns +Display : 0110 010110 010110 0011111 00010110 at 261 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/main.cpp new file mode 100644 index 000000000..056a41e79 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/main.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" +#include "display.h" +#include "sharing.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector4 stimulus_line1; + sc_signal_bool_vector5 stimulus_line2; + sc_signal_bool_vector6 stimulus_line3; + sc_signal_bool_vector7 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal_bool_vector4 result_line1; + sc_signal_bool_vector5 result_line2; + sc_signal_bool_vector6 result_line3; + sc_signal_bool_vector7 result_line4; + sc_signal_bool_vector8 result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + sharing sharing1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/sharing.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/sharing.cpp new file mode 100644 index 000000000..aa1dca4c5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/sharing.cpp @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "sharing.h" + +void sharing::entry(){ + + sc_bigint<4> tmp1; + sc_biguint<5> tmp2; + sc_bigint<6> tmp3; + sc_biguint<7> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp1 = tmp1 + 10; + tmp2 = tmp2 + 10; + tmp3 = tmp3 + 10; + tmp4 = tmp4 + 10; + tmp5 = tmp5 + 10; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute simple operations + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 10; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 10; + tmp5 = tmp5 + 1; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/sharing.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/sharing.f new file mode 100644 index 000000000..0c0f3ff29 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/sharing.f @@ -0,0 +1,4 @@ +sharing/stimulus.cpp +sharing/display.cpp +sharing/sharing.cpp +sharing/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/sharing.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/sharing.h new file mode 100644 index 000000000..d185d964c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/sharing.h @@ -0,0 +1,108 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( sharing ) +{ + SC_HAS_PROCESS( sharing ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector4& in_value1; // Input port + const sc_signal_bool_vector5& in_value2; // Input port + const sc_signal_bool_vector6& in_value3; // Input port + const sc_signal_bool_vector7& in_value4; // Input port + const sc_signal_bool_vector8& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal_bool_vector4& out_value1; // Output port + sc_signal_bool_vector5& out_value2; // Output port + sc_signal_bool_vector6& out_value3; // Output port + sc_signal_bool_vector7& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + sharing ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector4& IN_VALUE1, + const sc_signal_bool_vector5& IN_VALUE2, + const sc_signal_bool_vector6& IN_VALUE3, + const sc_signal_bool_vector7& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector4& OUT_VALUE1, + sc_signal_bool_vector5& OUT_VALUE2, + sc_signal_bool_vector6& OUT_VALUE3, + sc_signal_bool_vector7& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/stimulus.cpp new file mode 100644 index 000000000..7b71dd7a7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/stimulus.cpp @@ -0,0 +1,88 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" + +void stimulus::entry() { + sc_bigint<4> send_value1; + sc_biguint<5> send_value2; + sc_bigint<6> send_value3; + sc_biguint<7> send_value4; + sc_biguint<8> send_value5; + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value1 = 0; + send_value2 = 0; + send_value3 = 0; + send_value4 = 0; + send_value5 = 0; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(20); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+1; + send_value2 = send_value2+1; + send_value3 = send_value3+1; + send_value4 = send_value4+1; + send_value5 = send_value5+1; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/stimulus.h new file mode 100644 index 000000000..28a75e233 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/addition/sharing/stimulus.h @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-09 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector4& out_stimulus1; + sc_signal_bool_vector5& out_stimulus2; + sc_signal_bool_vector6& out_stimulus3; + sc_signal_bool_vector7& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector4& OUT_STIMULUS1, + sc_signal_bool_vector5& OUT_STIMULUS2, + sc_signal_bool_vector6& OUT_STIMULUS3, + sc_signal_bool_vector7& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/common.h new file mode 100644 index 000000000..335b51334 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<2> > sc_signal_bool_vector2; +typedef sc_signal<sc_bv<3> > sc_signal_bool_vector3; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/datatypes.cpp new file mode 100644 index 000000000..1418eba9b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/datatypes.cpp @@ -0,0 +1,105 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-12-10 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry(){ + + sc_biguint<2> tmp1; + sc_bigint<2> tmp2; + sc_biguint<3> tmp3; + sc_bigint<3> tmp4; + sc_biguint<2> tmp1r; + sc_bigint<2> tmp2r; + sc_biguint<3> tmp3r; + sc_bigint<3> tmp4r; + + // reset_loop + out_valid.write(false); + out_ack.write(false); + wait(); + + // + // main loop + // + + while(1) { + //input handshake + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + + // input handshake + out_ack.write(true); + + //execute datatypes operations + // unsigned(2) <- signed(3)/unsigned(2) + tmp1r = tmp4 / tmp1; + // signed(2) <- unsigned(2)/signed(3) + tmp2r = tmp1 / tmp4; + // unsigned(3) <- unsigned(3)/unsigned(2) + tmp3r = tmp3 / tmp1; + // signed(3) <- signed(3)/signed(2) + tmp4r = tmp4 / tmp2; + + // write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + + //output handshake + out_valid.write(true); + wait(); + + //input handshake + out_ack.write(false); + + //output handshake + out_valid.write(false); + wait(); + } +} + +// EOF + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/datatypes.h new file mode 100644 index 000000000..0d58458fd --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/datatypes.h @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector2& in_value1; // Input port + const sc_signal_bool_vector2& in_value2; // Input port + const sc_signal_bool_vector3& in_value3; // Input port + const sc_signal_bool_vector3& in_value4; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal_bool_vector2& out_value1; // Output port + sc_signal_bool_vector2& out_value2; // Output port + sc_signal_bool_vector3& out_value3; // Output port + sc_signal_bool_vector3& out_value4; // Output port + sc_signal<bool>& out_ack; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + datatypes ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector2& IN_VALUE1, + const sc_signal_bool_vector2& IN_VALUE2, + const sc_signal_bool_vector3& IN_VALUE3, + const sc_signal_bool_vector3& IN_VALUE4, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector2& OUT_VALUE1, + sc_signal_bool_vector2& OUT_VALUE2, + sc_signal_bool_vector3& OUT_VALUE3, + sc_signal_bool_vector3& OUT_VALUE4, + sc_signal<bool>& OUT_ACK, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_ack (OUT_ACK), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + +void entry (); + +}; + +// EOF + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/display.cpp new file mode 100644 index 000000000..649ac74a3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/display.cpp @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-12-11 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + wait(); + + while(counter<100){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << endl; + do { wait(); } while ( in_valid == true); + counter++; + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/display.h new file mode 100644 index 000000000..c4efff539 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/display.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector2& in_value1; // Input port + const sc_signal_bool_vector2& in_value2; // Input port + const sc_signal_bool_vector3& in_value3; // Input port + const sc_signal_bool_vector3& in_value4; // Input port + const sc_signal<bool>& in_valid; // Input port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector2& IN_VALUE1, + const sc_signal_bool_vector2& IN_VALUE2, + const sc_signal_bool_vector3& IN_VALUE3, + const sc_signal_bool_vector3& IN_VALUE4, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/golden/datatypes.log new file mode 100644 index 000000000..487107cf4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/golden/datatypes.log @@ -0,0 +1,204 @@ +SystemC Simulation +Stimuli: 1 -2 2 3 +Display: 11 00 010 111 +Stimuli: 2 -1 3 -4 +Display: 10 00 001 100 +Stimuli: 3 1 4 -3 +Display: 11 11 001 101 +Stimuli: 1 -2 5 -2 +Display: 10 00 101 001 +Stimuli: 2 -1 6 -1 +Display: 00 10 011 001 +Stimuli: 3 1 7 1 +Display: 00 11 010 001 +Stimuli: 1 -2 1 2 +Display: 10 00 001 111 +Stimuli: 2 -1 2 3 +Display: 01 00 001 101 +Stimuli: 3 1 3 -4 +Display: 11 00 001 100 +Stimuli: 1 -2 4 -3 +Display: 01 00 100 001 +Stimuli: 2 -1 5 -2 +Display: 11 11 010 010 +Stimuli: 3 1 6 -1 +Display: 00 01 010 111 +Stimuli: 1 -2 7 1 +Display: 01 01 111 000 +Stimuli: 2 -1 1 2 +Display: 01 01 000 110 +Stimuli: 3 1 2 3 +Display: 01 01 000 011 +Stimuli: 1 -2 3 -4 +Display: 00 00 011 010 +Stimuli: 2 -1 4 -3 +Display: 11 00 010 011 +Stimuli: 3 1 5 -2 +Display: 00 11 001 110 +Stimuli: 1 -2 6 -1 +Display: 11 11 110 000 +Stimuli: 2 -1 7 1 +Display: 00 10 011 111 +Stimuli: 3 1 1 2 +Display: 00 01 000 010 +Stimuli: 1 -2 2 3 +Display: 11 00 010 111 +Stimuli: 2 -1 3 -4 +Display: 10 00 001 100 +Stimuli: 3 1 4 -3 +Display: 11 11 001 101 +Stimuli: 1 -2 5 -2 +Display: 10 00 101 001 +Stimuli: 2 -1 6 -1 +Display: 00 10 011 001 +Stimuli: 3 1 7 1 +Display: 00 11 010 001 +Stimuli: 1 -2 1 2 +Display: 10 00 001 111 +Stimuli: 2 -1 2 3 +Display: 01 00 001 101 +Stimuli: 3 1 3 -4 +Display: 11 00 001 100 +Stimuli: 1 -2 4 -3 +Display: 01 00 100 001 +Stimuli: 2 -1 5 -2 +Display: 11 11 010 010 +Stimuli: 3 1 6 -1 +Display: 00 01 010 111 +Stimuli: 1 -2 7 1 +Display: 01 01 111 000 +Stimuli: 2 -1 1 2 +Display: 01 01 000 110 +Stimuli: 3 1 2 3 +Display: 01 01 000 011 +Stimuli: 1 -2 3 -4 +Display: 00 00 011 010 +Stimuli: 2 -1 4 -3 +Display: 11 00 010 011 +Stimuli: 3 1 5 -2 +Display: 00 11 001 110 +Stimuli: 1 -2 6 -1 +Display: 11 11 110 000 +Stimuli: 2 -1 7 1 +Display: 00 10 011 111 +Stimuli: 3 1 1 2 +Display: 00 01 000 010 +Stimuli: 1 -2 2 3 +Display: 11 00 010 111 +Stimuli: 2 -1 3 -4 +Display: 10 00 001 100 +Stimuli: 3 1 4 -3 +Display: 11 11 001 101 +Stimuli: 1 -2 5 -2 +Display: 10 00 101 001 +Stimuli: 2 -1 6 -1 +Display: 00 10 011 001 +Stimuli: 3 1 7 1 +Display: 00 11 010 001 +Stimuli: 1 -2 1 2 +Display: 10 00 001 111 +Stimuli: 2 -1 2 3 +Display: 01 00 001 101 +Stimuli: 3 1 3 -4 +Display: 11 00 001 100 +Stimuli: 1 -2 4 -3 +Display: 01 00 100 001 +Stimuli: 2 -1 5 -2 +Display: 11 11 010 010 +Stimuli: 3 1 6 -1 +Display: 00 01 010 111 +Stimuli: 1 -2 7 1 +Display: 01 01 111 000 +Stimuli: 2 -1 1 2 +Display: 01 01 000 110 +Stimuli: 3 1 2 3 +Display: 01 01 000 011 +Stimuli: 1 -2 3 -4 +Display: 00 00 011 010 +Stimuli: 2 -1 4 -3 +Display: 11 00 010 011 +Stimuli: 3 1 5 -2 +Display: 00 11 001 110 +Stimuli: 1 -2 6 -1 +Display: 11 11 110 000 +Stimuli: 2 -1 7 1 +Display: 00 10 011 111 +Stimuli: 3 1 1 2 +Display: 00 01 000 010 +Stimuli: 1 -2 2 3 +Display: 11 00 010 111 +Stimuli: 2 -1 3 -4 +Display: 10 00 001 100 +Stimuli: 3 1 4 -3 +Display: 11 11 001 101 +Stimuli: 1 -2 5 -2 +Display: 10 00 101 001 +Stimuli: 2 -1 6 -1 +Display: 00 10 011 001 +Stimuli: 3 1 7 1 +Display: 00 11 010 001 +Stimuli: 1 -2 1 2 +Display: 10 00 001 111 +Stimuli: 2 -1 2 3 +Display: 01 00 001 101 +Stimuli: 3 1 3 -4 +Display: 11 00 001 100 +Stimuli: 1 -2 4 -3 +Display: 01 00 100 001 +Stimuli: 2 -1 5 -2 +Display: 11 11 010 010 +Stimuli: 3 1 6 -1 +Display: 00 01 010 111 +Stimuli: 1 -2 7 1 +Display: 01 01 111 000 +Stimuli: 2 -1 1 2 +Display: 01 01 000 110 +Stimuli: 3 1 2 3 +Display: 01 01 000 011 +Stimuli: 1 -2 3 -4 +Display: 00 00 011 010 +Stimuli: 2 -1 4 -3 +Display: 11 00 010 011 +Stimuli: 3 1 5 -2 +Display: 00 11 001 110 +Stimuli: 1 -2 6 -1 +Display: 11 11 110 000 +Stimuli: 2 -1 7 1 +Display: 00 10 011 111 +Stimuli: 3 1 1 2 +Display: 00 01 000 010 +Stimuli: 1 -2 2 3 +Display: 11 00 010 111 +Stimuli: 2 -1 3 -4 +Display: 10 00 001 100 +Stimuli: 3 1 4 -3 +Display: 11 11 001 101 +Stimuli: 1 -2 5 -2 +Display: 10 00 101 001 +Stimuli: 2 -1 6 -1 +Display: 00 10 011 001 +Stimuli: 3 1 7 1 +Display: 00 11 010 001 +Stimuli: 1 -2 1 2 +Display: 10 00 001 111 +Stimuli: 2 -1 2 3 +Display: 01 00 001 101 +Stimuli: 3 1 3 -4 +Display: 11 00 001 100 +Stimuli: 1 -2 4 -3 +Display: 01 00 100 001 +Stimuli: 2 -1 5 -2 +Display: 11 11 010 010 +Stimuli: 3 1 6 -1 +Display: 00 01 010 111 +Stimuli: 1 -2 7 1 +Display: 01 01 111 000 +Stimuli: 2 -1 1 2 +Display: 01 01 000 110 +Stimuli: 3 1 2 3 +Display: 01 01 000 011 +Stimuli: 1 -2 3 -4 +Display: 00 00 011 010 +Stimuli: 2 -1 4 -3 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/main.cpp new file mode 100644 index 000000000..a56c0c05e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/main.cpp @@ -0,0 +1,94 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector2 stimulus_line1; + sc_signal_bool_vector2 stimulus_line2; + sc_signal_bool_vector3 stimulus_line3; + sc_signal_bool_vector3 stimulus_line4; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector2 result_line1; + sc_signal_bool_vector2 result_line2; + sc_signal_bool_vector3 result_line3; + sc_signal_bool_vector3 result_line4; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + ack, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/stimulus.cpp new file mode 100644 index 000000000..5f0d4fc1d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/stimulus.cpp @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-10-01 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_unsigned tmp1(2); + sc_signed tmp2(2); + sc_unsigned tmp3(3); + sc_signed tmp4(3); + sc_unsigned zero_2(2); + sc_unsigned zero_3(3); + + zero_3 = "000"; + zero_2 = "00"; + tmp1 = "01"; + tmp2 = "10"; + tmp3 = "010"; + tmp4 = "011"; + + + while(true){ + // handshake + out_valid.write(true); + // write stimuli + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + cout << "Stimuli: "<< tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << endl; + // update stimuli + tmp1 = tmp1 + 1; + if (tmp1 == zero_2) tmp1 = "01"; + tmp2 = tmp2 + 1; + if (tmp2 == zero_2) tmp2 = "01"; + tmp3 = tmp3 + 1; + if (tmp3 == zero_3) tmp3 = "001"; + tmp4 = tmp4 + 1; + if (tmp4 == zero_3) tmp4 = "001"; + // handshake + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/stimulus.h new file mode 100644 index 000000000..5e7335244 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/stimulus.h @@ -0,0 +1,84 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset ; + sc_signal_bool_vector2& out_value1; // Output port + sc_signal_bool_vector2& out_value2; // Output port + sc_signal_bool_vector3& out_value3; // Output port + sc_signal_bool_vector3& out_value4; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector2& OUT_VALUE1, + sc_signal_bool_vector2& OUT_VALUE2, + sc_signal_bool_vector3& OUT_VALUE3, + sc_signal_bool_vector3& OUT_VALUE4, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/common.h new file mode 100644 index 000000000..8a560ac63 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/display.cpp new file mode 100644 index 000000000..2a99472b8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/display.h new file mode 100644 index 000000000..5902ca652 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal_bool_vector4& in_data2; // Input port + const sc_signal_bool_vector4& in_data3; // Input port + const sc_signal_bool_vector8& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal_bool_vector4& IN_DATA2, + const sc_signal_bool_vector4& IN_DATA3, + const sc_signal_bool_vector8& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/divide.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/divide.cpp new file mode 100644 index 000000000..bc363dc9a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/divide.cpp @@ -0,0 +1,129 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + divide.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "divide.h" + +void divide::entry(){ + + int tmp1; + sc_bigint<4> tmp2; + sc_biguint<4> tmp3; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute operations + tmp1 = tmp1/2; + tmp2 = tmp2/2; + tmp3 = tmp3/2; + tmp4 = tmp4/2; + tmp5 = tmp5/2; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute slf assigning operations + tmp1 /= 3; + tmp2 /= 3; + tmp3 /= 3; + tmp4 /= 3; + tmp5 /= 3; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute self assigning operations + if (tmp3!=0) + tmp1 = (tmp2/tmp3).to_int(); + if (tmp4!=0) + tmp2 = tmp2/tmp4; + if (tmp5!=0) + tmp3 = tmp3/tmp5; + if (tmp5!=0) + tmp4 = tmp4/tmp5; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/divide.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/divide.f new file mode 100644 index 000000000..2e58a7f37 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/divide.f @@ -0,0 +1,4 @@ +divide/stimulus.cpp +divide/display.cpp +divide/divide.cpp +divide/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/divide.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/divide.h new file mode 100644 index 000000000..20be049c1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/divide.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + divide.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( divide ) +{ + SC_HAS_PROCESS( divide ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; // Input port + const sc_signal_bool_vector4& in_value3; // Input port + const sc_signal_bool_vector8& in_value4; // Input port + const sc_signal_bool_vector8& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal_bool_vector4& out_value2; // Output port + sc_signal_bool_vector4& out_value3; // Output port + sc_signal_bool_vector8& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + divide( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector4& IN_VALUE3, + const sc_signal_bool_vector8& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector4& OUT_VALUE3, + sc_signal_bool_vector8& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/golden/divide.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/golden/divide.log new file mode 100644 index 000000000..e48b2110a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/golden/divide.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli : 254 -2 14 -2 254 at 18 ns +Display : 127 1111 0111 11111111 01111111 at 22 ns +Display : 42 1111 0010 00000000 00101010 at 25 ns +Display : 0 1111 0000 00000000 00101010 at 28 ns +Stimuli : 253 -3 13 -3 253 at 34 ns +Display : 126 1111 0110 11111111 01111110 at 38 ns +Display : 42 1111 0010 00000000 00101010 at 41 ns +Display : 0 1111 0000 00000000 00101010 at 44 ns +Stimuli : 252 -4 12 -4 252 at 50 ns +Display : 126 1110 0110 11111110 01111110 at 54 ns +Display : 42 1110 0010 00000000 00101010 at 57 ns +Display : 0 1110 0000 00000000 00101010 at 60 ns +Stimuli : 251 -5 11 -5 251 at 66 ns +Display : 125 1110 0101 11111110 01111101 at 70 ns +Display : 41 1110 0001 00000000 00101001 at 73 ns +Display : 0 1110 0000 00000000 00101001 at 76 ns +Stimuli : 250 -6 10 -6 250 at 82 ns +Display : 125 1101 0101 11111101 01111101 at 86 ns +Display : 41 1101 0001 11111111 00101001 at 89 ns +Display : -1 1101 0000 00000000 00101001 at 92 ns +Stimuli : 249 -7 9 -7 249 at 98 ns +Display : 124 1101 0100 11111101 01111100 at 102 ns +Display : 41 1101 0001 11111111 00101001 at 105 ns +Display : -1 1101 0000 00000000 00101001 at 108 ns +Stimuli : 248 -8 8 -8 248 at 114 ns +Display : 124 1100 0100 11111100 01111100 at 118 ns +Display : 41 1100 0001 11111111 00101001 at 121 ns +Display : -1 1100 0000 00000000 00101001 at 124 ns +Stimuli : 247 7 7 -9 247 at 130 ns +Display : 123 0011 0011 11111100 01111011 at 134 ns +Display : 41 0011 0001 11111111 00101001 at 137 ns +Display : 1 0011 0000 00000000 00101001 at 140 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/main.cpp new file mode 100644 index 000000000..5285ae4aa --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "divide.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector4 stimulus_line3; + sc_signal_bool_vector8 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector4 result_line3; + sc_signal_bool_vector8 result_line4; + sc_signal_bool_vector8 result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + divide divide1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/stimulus.cpp new file mode 100644 index 000000000..f4f3ffac7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/stimulus.cpp @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + int send_value1 = 254; + sc_signed send_value2(4); + sc_unsigned send_value3(4); + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + reset.write(true); + out_valid.write(false); + send_value2 = 14; + send_value3 = 14; + send_value4 = 254; + send_value5 = 254; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + while(true){ + wait(15); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1--; + send_value2 = send_value2-1; + send_value3 = send_value3-1; + send_value4 = send_value4-1; + send_value5 = send_value5-1; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/stimulus.h new file mode 100644 index 000000000..4fe06d3f2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/divide/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal_bool_vector4& out_stimulus2; + sc_signal_bool_vector4& out_stimulus3; + sc_signal_bool_vector8& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal_bool_vector4& OUT_STIMULUS2, + sc_signal_bool_vector4& OUT_STIMULUS3, + sc_signal_bool_vector8& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/common.h new file mode 100644 index 000000000..8a560ac63 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/display.cpp new file mode 100644 index 000000000..2a99472b8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/display.h new file mode 100644 index 000000000..93a9e567b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal_bool_vector4& in_data2; // Input port + const sc_signal_bool_vector4& in_data3; // Input port + const sc_signal_bool_vector8& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal_bool_vector4& IN_DATA2, + const sc_signal_bool_vector4& IN_DATA3, + const sc_signal_bool_vector8& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/golden/modulo.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/golden/modulo.log new file mode 100644 index 000000000..2fffc9ded --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/golden/modulo.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli : 254 -2 14 -2 254 at 18 ns +Display : 4 1110 0100 11111110 00000100 at 22 ns +Display : 1 1110 0001 11111110 00000001 at 25 ns +Display : 0 0000 0000 00000000 00000001 at 28 ns +Stimuli : 253 -3 13 -3 253 at 34 ns +Display : 3 1101 0011 11111101 00000011 at 38 ns +Display : 0 0000 0000 00000000 00000000 at 41 ns +Display : 0 0000 0000 00000000 00000000 at 44 ns +Stimuli : 252 -4 12 -4 252 at 50 ns +Display : 2 1100 0010 11111100 00000010 at 54 ns +Display : 2 1111 0010 11111111 00000010 at 57 ns +Display : -1 0000 0000 11111111 00000010 at 60 ns +Stimuli : 251 -5 11 -5 251 at 66 ns +Display : 1 0000 0001 00000000 00000001 at 70 ns +Display : 1 0000 0001 00000000 00000001 at 73 ns +Display : 0 0000 0000 00000000 00000001 at 76 ns +Stimuli : 250 -6 10 -6 250 at 82 ns +Display : 0 1111 0000 11111111 00000000 at 86 ns +Display : 0 1111 0000 11111111 00000000 at 89 ns +Display : 0 0000 0000 11111111 00000000 at 92 ns +Stimuli : 249 -7 9 -7 249 at 98 ns +Display : 4 1110 0100 11111110 00000100 at 102 ns +Display : 1 1110 0001 11111110 00000001 at 105 ns +Display : 0 0000 0000 00000000 00000001 at 108 ns +Stimuli : 248 -8 8 -8 248 at 114 ns +Display : 3 1101 0011 11111101 00000011 at 118 ns +Display : 0 0000 0000 00000000 00000000 at 121 ns +Display : 0 0000 0000 00000000 00000000 at 124 ns +Stimuli : 247 7 7 -9 247 at 130 ns +Display : 2 0010 0010 11111100 00000010 at 134 ns +Display : 2 0010 0010 11111111 00000010 at 137 ns +Display : 0 0000 0000 11111111 00000010 at 140 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/main.cpp new file mode 100644 index 000000000..db408bc47 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "modulo.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector4 stimulus_line3; + sc_signal_bool_vector8 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector4 result_line3; + sc_signal_bool_vector8 result_line4; + sc_signal_bool_vector8 result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + modulo modulo1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/modulo.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/modulo.cpp new file mode 100644 index 000000000..eba16c8f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/modulo.cpp @@ -0,0 +1,131 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + modulo.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "modulo.h" + +void modulo::entry(){ + + int tmp1; + sc_bigint<4> tmp2; + sc_biguint<4> tmp3; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute operations + tmp1 = tmp1%5; + tmp2 = tmp2%5; + tmp3 = tmp3%5; + tmp4 = tmp4%5; + tmp5 = tmp5%5; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute self assignment operations + tmp1 %= 3; + tmp2 %= 3; + tmp3 %= 3; + tmp4 %= 3; + tmp5 %= 3; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute different type operations + if (tmp3!=0) + tmp1 = (tmp2%tmp3).to_int(); + if (tmp4!=0) + tmp2 = tmp2%tmp4; + if (tmp5!=0) + tmp3 = tmp3%tmp5; + if (tmp5!=0) + tmp4 = tmp4%tmp5; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/modulo.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/modulo.f new file mode 100644 index 000000000..444eb5b42 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/modulo.f @@ -0,0 +1,4 @@ +modulo/stimulus.cpp +modulo/display.cpp +modulo/modulo.cpp +modulo/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/modulo.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/modulo.h new file mode 100644 index 000000000..e77849c8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/modulo.h @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + modulo.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( modulo ) +{ + SC_HAS_PROCESS( modulo ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; // Input port + const sc_signal_bool_vector4& in_value3; // Input port + const sc_signal_bool_vector8& in_value4; // Input port + const sc_signal_bool_vector8& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal_bool_vector4& out_value2; // Output port + sc_signal_bool_vector4& out_value3; // Output port + sc_signal_bool_vector8& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + modulo( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector4& IN_VALUE3, + const sc_signal_bool_vector8& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector4& OUT_VALUE3, + sc_signal_bool_vector8& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/stimulus.cpp new file mode 100644 index 000000000..f224e9210 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/stimulus.cpp @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + int send_value1 = 254; + sc_signed send_value2(4); + sc_unsigned send_value3(4); + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + reset.write(true); + out_valid.write(false); + send_value2 = 14; + send_value3 = 14; + send_value4 = 254; + send_value5 = 254; + out_stimulus1.write(0); + out_stimulus3.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + while(true){ + wait(15); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1--; + send_value2 = send_value2-1; + send_value3 = send_value3-1; + send_value4 = send_value4-1; + send_value5 = send_value5-1; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/stimulus.h new file mode 100644 index 000000000..7d02a2958 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/modulo/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal_bool_vector4& out_stimulus2; + sc_signal_bool_vector4& out_stimulus3; + sc_signal_bool_vector8& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal_bool_vector4& OUT_STIMULUS2, + sc_signal_bool_vector4& OUT_STIMULUS3, + sc_signal_bool_vector8& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/common.h new file mode 100644 index 000000000..8a560ac63 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/display.cpp new file mode 100644 index 000000000..2a99472b8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/display.h new file mode 100644 index 000000000..5902ca652 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal_bool_vector4& in_data2; // Input port + const sc_signal_bool_vector4& in_data3; // Input port + const sc_signal_bool_vector8& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal_bool_vector4& IN_DATA2, + const sc_signal_bool_vector4& IN_DATA3, + const sc_signal_bool_vector8& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/golden/mult.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/golden/mult.log new file mode 100644 index 000000000..7f225d536 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/golden/mult.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli : 0 0 0 0 0 at 18 ns +Display : 0 0000 0000 00000000 00000000 at 22 ns +Display : 0 0000 0000 00000000 00000000 at 25 ns +Display : 0 0000 0000 00000000 00000000 at 28 ns +Stimuli : 1 1 1 1 1 at 34 ns +Display : 2 0010 0010 00000010 00000010 at 38 ns +Display : 4 0100 0100 00000100 00000100 at 41 ns +Display : 16 0000 0000 00010000 01000000 at 44 ns +Stimuli : 2 2 2 2 2 at 50 ns +Display : 4 0100 0100 00000100 00000100 at 54 ns +Display : 8 1000 1000 00001000 00001000 at 57 ns +Display : -64 0000 0000 01000000 00000000 at 60 ns +Stimuli : 3 3 3 3 3 at 66 ns +Display : 6 0110 0110 00000110 00000110 at 70 ns +Display : 12 1100 1100 00001100 00001100 at 73 ns +Display : -48 0000 0000 10010000 11000000 at 76 ns +Stimuli : 4 4 4 4 4 at 82 ns +Display : 8 1000 1000 00001000 00001000 at 86 ns +Display : 16 0000 0000 00010000 00010000 at 89 ns +Display : 0 0000 0000 00000000 00000000 at 92 ns +Stimuli : 5 5 5 5 5 at 98 ns +Display : 10 1010 1010 00001010 00001010 at 102 ns +Display : 20 0100 0100 00010100 00010100 at 105 ns +Display : 16 0000 0000 10010000 01000000 at 108 ns +Stimuli : 6 6 6 6 6 at 114 ns +Display : 12 1100 1100 00001100 00001100 at 118 ns +Display : 24 1000 1000 00011000 00011000 at 121 ns +Display : -64 0000 0000 01000000 00000000 at 124 ns +Stimuli : 7 7 7 7 7 at 130 ns +Display : 14 1110 1110 00001110 00001110 at 134 ns +Display : 28 1100 1100 00011100 00011100 at 137 ns +Display : -48 0000 0000 00010000 11000000 at 140 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/main.cpp new file mode 100644 index 000000000..9ef3b5199 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "mult.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector4 stimulus_line3; + sc_signal_bool_vector8 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector4 result_line3; + sc_signal_bool_vector8 result_line4; + sc_signal_bool_vector8 result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + mult mult1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/mult.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/mult.cpp new file mode 100644 index 000000000..3faec6274 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/mult.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + mult.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "mult.h" + +void mult::entry(){ + + int tmp1; + sc_bigint<4> tmp2; + sc_biguint<4> tmp3; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp1 = tmp1 * 2; + tmp2 = tmp2 * 2; + tmp3 = tmp3 * 2; + tmp4 = tmp4 * 2; + tmp5 = tmp5 * 2; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute self assigning operations + tmp1 *= 2; + tmp2 *= 2; + tmp3 *= 2; + tmp4 *= 2; + tmp5 *= 2; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute complex operations with different bit width + tmp1 = (tmp2*tmp3).to_int(); + tmp2 = tmp2*tmp4; + tmp3 = tmp3*tmp5; + tmp4 = tmp4*tmp5; + tmp5 = tmp4*tmp5; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/mult.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/mult.f new file mode 100644 index 000000000..795188df6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/mult.f @@ -0,0 +1,4 @@ +mult/stimulus.cpp +mult/display.cpp +mult/mult.cpp +mult/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/mult.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/mult.h new file mode 100644 index 000000000..d7a5d76b6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/mult.h @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + mult.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( mult ) +{ + SC_HAS_PROCESS( mult ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; // Input port + const sc_signal_bool_vector4& in_value3; // Input port + const sc_signal_bool_vector8& in_value4; // Input port + const sc_signal_bool_vector8& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal_bool_vector4& out_value2; // Output port + sc_signal_bool_vector4& out_value3; // Output port + sc_signal_bool_vector8& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + mult( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector4& IN_VALUE3, + const sc_signal_bool_vector8& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector4& OUT_VALUE3, + sc_signal_bool_vector8& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/stimulus.cpp new file mode 100644 index 000000000..456016581 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/stimulus.cpp @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + int send_value1 = 0; + sc_signed send_value2(4); + sc_unsigned send_value3(4); + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + reset.write(true); + out_valid.write(false); + send_value2 = 0; + send_value3 = 0; + send_value4 = 0; + send_value5 = 0; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + while(true){ + wait(15); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1++; + send_value2 = send_value2+1; + send_value3 = send_value3+1; + send_value4 = send_value4+1; + send_value5 = send_value5+1; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/stimulus.h new file mode 100644 index 000000000..457d783ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/mult/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-05-13 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal_bool_vector4& out_stimulus2; + sc_signal_bool_vector4& out_stimulus3; + sc_signal_bool_vector8& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal_bool_vector4& OUT_STIMULUS2, + sc_signal_bool_vector4& OUT_STIMULUS3, + sc_signal_bool_vector8& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.cpp new file mode 100644 index 000000000..3dc7a1980 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-12-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "bitwidth.h" + +void bitwidth::entry(){ + + sc_biguint<2> tmp1; + sc_biguint<2> tmp1a; + sc_bigint<4> tmp2; + sc_bigint<4> tmp2a; + sc_biguint<6> tmp3; + sc_biguint<6> tmp3a; + sc_bigint<8> tmp4; + sc_bigint<8> tmp4a; + + // reset_loop + out_valid.write(false); + out_ack.write(false); + wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + + //execute simple operations + // expected bitwidth 2 2 2 + tmp1a = tmp1 - tmp1; + // expected bitwidth 2 4 4 + tmp2a = tmp2 - tmp1; + // expected bitwidth 6 2 6 + tmp3a = tmp3 - tmp1; + // expected bitwidth 4 8 8 + tmp4a = tmp4 - tmp2; + + out_ack.write(true); + wait(); + out_ack.write(false); + + // write outputs + out_value1.write(tmp1a); + out_value2.write(tmp2a); + out_value3.write(tmp3a); + out_value4.write(tmp4a); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.f new file mode 100644 index 000000000..53a59162e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.f @@ -0,0 +1,4 @@ +bitwidth/stimulus.cpp +bitwidth/display.cpp +bitwidth/bitwidth.cpp +bitwidth/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.h new file mode 100644 index 000000000..e31268284 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/bitwidth.h @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( bitwidth ) +{ + SC_HAS_PROCESS( bitwidth ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector2& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; // Input port + const sc_signal_bool_vector6& in_value3; // Input port + const sc_signal_bool_vector8& in_value4; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal_bool_vector2& out_value1; // Output port + sc_signal_bool_vector4& out_value2; // Output port + sc_signal_bool_vector6& out_value3; // Output port + sc_signal_bool_vector8& out_value4; // Output port + sc_signal<bool>& out_ack; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + bitwidth ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector2& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector6& IN_VALUE3, + const sc_signal_bool_vector8& IN_VALUE4, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector2& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector6& OUT_VALUE3, + sc_signal_bool_vector8& OUT_VALUE4, + sc_signal<bool>& OUT_ACK, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_ack (OUT_ACK), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + +void entry (); + +}; + +// EOF + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/common.h new file mode 100644 index 000000000..d3b94a8f8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/common.h @@ -0,0 +1,48 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<2> > sc_signal_bool_vector2; +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<6> > sc_signal_bool_vector6; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.cpp new file mode 100644 index 000000000..e6d9371f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-12-10 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter<100){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << endl; + do { wait(); } while ( in_valid == true); + counter++; + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.h new file mode 100644 index 000000000..00498390d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/display.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector2& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; // Input port + const sc_signal_bool_vector6& in_value3; // Input port + const sc_signal_bool_vector8& in_value4; // Input port + const sc_signal<bool>& in_valid; // Input port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector2& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector6& IN_VALUE3, + const sc_signal_bool_vector8& IN_VALUE4, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/golden/bitwidth.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/golden/bitwidth.log new file mode 100644 index 000000000..26dab71e7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/golden/bitwidth.log @@ -0,0 +1,204 @@ +SystemC Simulation +Stimuli: 0 1 2 3 +Stimuli: 1 2 3 4 +Display: 00 0001 000010 00000010 +Stimuli: -2 3 4 5 +Display: 00 0001 000010 00000010 +Stimuli: -1 4 5 6 +Display: 00 0001 000010 00000010 +Stimuli: 0 5 6 7 +Display: 00 0001 000010 00000010 +Stimuli: 1 6 7 8 +Display: 00 0101 000110 00000010 +Stimuli: -2 7 8 9 +Display: 00 0101 000110 00000010 +Stimuli: -1 -8 9 10 +Display: 00 0101 000110 00000010 +Stimuli: 0 -7 10 11 +Display: 00 0101 000110 00010010 +Stimuli: 1 -6 11 12 +Display: 00 1001 001010 00010010 +Stimuli: -2 -5 12 13 +Display: 00 1001 001010 00010010 +Stimuli: -1 -4 13 14 +Display: 00 1001 001010 00010010 +Stimuli: 0 -3 14 15 +Display: 00 1001 001010 00010010 +Stimuli: 1 -2 15 16 +Display: 00 1101 001110 00010010 +Stimuli: -2 -1 16 17 +Display: 00 1101 001110 00010010 +Stimuli: -1 0 17 18 +Display: 00 1101 001110 00010010 +Stimuli: 0 1 18 19 +Display: 00 1101 001110 00010010 +Stimuli: 1 2 19 20 +Display: 00 0001 010010 00010010 +Stimuli: -2 3 20 21 +Display: 00 0001 010010 00010010 +Stimuli: -1 4 21 22 +Display: 00 0001 010010 00010010 +Stimuli: 0 5 22 23 +Display: 00 0001 010010 00010010 +Stimuli: 1 6 23 24 +Display: 00 0101 010110 00010010 +Stimuli: -2 7 24 25 +Display: 00 0101 010110 00010010 +Stimuli: -1 -8 25 26 +Display: 00 0101 010110 00010010 +Stimuli: 0 -7 26 27 +Display: 00 0101 010110 00100010 +Stimuli: 1 -6 27 28 +Display: 00 1001 011010 00100010 +Stimuli: -2 -5 28 29 +Display: 00 1001 011010 00100010 +Stimuli: -1 -4 29 30 +Display: 00 1001 011010 00100010 +Stimuli: 0 -3 30 31 +Display: 00 1001 011010 00100010 +Stimuli: 1 -2 31 32 +Display: 00 1101 011110 00100010 +Stimuli: -2 -1 -32 33 +Display: 00 1101 011110 00100010 +Stimuli: -1 0 -31 34 +Display: 00 1101 011110 00100010 +Stimuli: 0 1 -30 35 +Display: 00 1101 011110 00100010 +Stimuli: 1 2 -29 36 +Display: 00 0001 100010 00100010 +Stimuli: -2 3 -28 37 +Display: 00 0001 100010 00100010 +Stimuli: -1 4 -27 38 +Display: 00 0001 100010 00100010 +Stimuli: 0 5 -26 39 +Display: 00 0001 100010 00100010 +Stimuli: 1 6 -25 40 +Display: 00 0101 100110 00100010 +Stimuli: -2 7 -24 41 +Display: 00 0101 100110 00100010 +Stimuli: -1 -8 -23 42 +Display: 00 0101 100110 00100010 +Stimuli: 0 -7 -22 43 +Display: 00 0101 100110 00110010 +Stimuli: 1 -6 -21 44 +Display: 00 1001 101010 00110010 +Stimuli: -2 -5 -20 45 +Display: 00 1001 101010 00110010 +Stimuli: -1 -4 -19 46 +Display: 00 1001 101010 00110010 +Stimuli: 0 -3 -18 47 +Display: 00 1001 101010 00110010 +Stimuli: 1 -2 -17 48 +Display: 00 1101 101110 00110010 +Stimuli: -2 -1 -16 49 +Display: 00 1101 101110 00110010 +Stimuli: -1 0 -15 50 +Display: 00 1101 101110 00110010 +Stimuli: 0 1 -14 51 +Display: 00 1101 101110 00110010 +Stimuli: 1 2 -13 52 +Display: 00 0001 110010 00110010 +Stimuli: -2 3 -12 53 +Display: 00 0001 110010 00110010 +Stimuli: -1 4 -11 54 +Display: 00 0001 110010 00110010 +Stimuli: 0 5 -10 55 +Display: 00 0001 110010 00110010 +Stimuli: 1 6 -9 56 +Display: 00 0101 110110 00110010 +Stimuli: -2 7 -8 57 +Display: 00 0101 110110 00110010 +Stimuli: -1 -8 -7 58 +Display: 00 0101 110110 00110010 +Stimuli: 0 -7 -6 59 +Display: 00 0101 110110 01000010 +Stimuli: 1 -6 -5 60 +Display: 00 1001 111010 01000010 +Stimuli: -2 -5 -4 61 +Display: 00 1001 111010 01000010 +Stimuli: -1 -4 -3 62 +Display: 00 1001 111010 01000010 +Stimuli: 0 -3 -2 63 +Display: 00 1001 111010 01000010 +Stimuli: 1 -2 -1 64 +Display: 00 1101 111110 01000010 +Stimuli: -2 -1 0 65 +Display: 00 1101 111110 01000010 +Stimuli: -1 0 1 66 +Display: 00 1101 111110 01000010 +Stimuli: 0 1 2 67 +Display: 00 1101 111110 01000010 +Stimuli: 1 2 3 68 +Display: 00 0001 000010 01000010 +Stimuli: -2 3 4 69 +Display: 00 0001 000010 01000010 +Stimuli: -1 4 5 70 +Display: 00 0001 000010 01000010 +Stimuli: 0 5 6 71 +Display: 00 0001 000010 01000010 +Stimuli: 1 6 7 72 +Display: 00 0101 000110 01000010 +Stimuli: -2 7 8 73 +Display: 00 0101 000110 01000010 +Stimuli: -1 -8 9 74 +Display: 00 0101 000110 01000010 +Stimuli: 0 -7 10 75 +Display: 00 0101 000110 01010010 +Stimuli: 1 -6 11 76 +Display: 00 1001 001010 01010010 +Stimuli: -2 -5 12 77 +Display: 00 1001 001010 01010010 +Stimuli: -1 -4 13 78 +Display: 00 1001 001010 01010010 +Stimuli: 0 -3 14 79 +Display: 00 1001 001010 01010010 +Stimuli: 1 -2 15 80 +Display: 00 1101 001110 01010010 +Stimuli: -2 -1 16 81 +Display: 00 1101 001110 01010010 +Stimuli: -1 0 17 82 +Display: 00 1101 001110 01010010 +Stimuli: 0 1 18 83 +Display: 00 1101 001110 01010010 +Stimuli: 1 2 19 84 +Display: 00 0001 010010 01010010 +Stimuli: -2 3 20 85 +Display: 00 0001 010010 01010010 +Stimuli: -1 4 21 86 +Display: 00 0001 010010 01010010 +Stimuli: 0 5 22 87 +Display: 00 0001 010010 01010010 +Stimuli: 1 6 23 88 +Display: 00 0101 010110 01010010 +Stimuli: -2 7 24 89 +Display: 00 0101 010110 01010010 +Stimuli: -1 -8 25 90 +Display: 00 0101 010110 01010010 +Stimuli: 0 -7 26 91 +Display: 00 0101 010110 01100010 +Stimuli: 1 -6 27 92 +Display: 00 1001 011010 01100010 +Stimuli: -2 -5 28 93 +Display: 00 1001 011010 01100010 +Stimuli: -1 -4 29 94 +Display: 00 1001 011010 01100010 +Stimuli: 0 -3 30 95 +Display: 00 1001 011010 01100010 +Stimuli: 1 -2 31 96 +Display: 00 1101 011110 01100010 +Stimuli: -2 -1 -32 97 +Display: 00 1101 011110 01100010 +Stimuli: -1 0 -31 98 +Display: 00 1101 011110 01100010 +Stimuli: 0 1 -30 99 +Display: 00 1101 011110 01100010 +Stimuli: 1 2 -29 100 +Display: 00 0001 100010 01100010 +Stimuli: -2 3 -28 101 +Display: 00 0001 100010 01100010 +Stimuli: -1 4 -27 102 +Display: 00 0001 100010 01100010 +Stimuli: 0 5 -26 103 +Display: 00 0001 100010 01100010 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/main.cpp new file mode 100644 index 000000000..61341a228 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "bitwidth.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector2 stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector6 stimulus_line3; + sc_signal_bool_vector8 stimulus_line4; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector2 result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector6 result_line3; + sc_signal_bool_vector8 result_line4; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + input_valid, + ack); + + bitwidth bitwidth1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + ack, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.cpp new file mode 100644 index 000000000..4ce6064b4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.cpp @@ -0,0 +1,73 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(2); + sc_signed tmp2(4); + sc_signed tmp3(6); + sc_signed tmp4(8); + + tmp1 = "0b00"; + tmp2 = "0b0001"; + tmp3 = "0b000010"; + tmp4 = "0b00000011"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + cout << "Stimuli: "<< tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.h new file mode 100644 index 000000000..0fa07858c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/stimulus.h @@ -0,0 +1,84 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset ; + sc_signal_bool_vector2& out_value1; // Output port + sc_signal_bool_vector4& out_value2; // Output port + sc_signal_bool_vector6& out_value3; // Output port + sc_signal_bool_vector8& out_value4; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector2& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector6& OUT_VALUE3, + sc_signal_bool_vector8& OUT_VALUE4, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/datatypes.cpp new file mode 100644 index 000000000..d3e2cd1e1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/datatypes.cpp @@ -0,0 +1,119 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + int tmp7[2]; + char tmp8[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// + +// initialization of sc_array + + tmp7[0] = 3; + tmp7[1] = 12; + tmp8[0] = 'R'; + tmp8[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + out_ack.write(true); + + //execute mixed data type subtraction operations + tmp1r = tmp1 - tmp2; + tmp2r = tmp6 - tmp1; + tmp3r = tmp4 - tmp6; + tmp4r = --tmp5; + tmp4r -= 1; + tmp5r = tmp6 - tmp4; + tmp6r = tmp8[0] - tmp7[1]; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/datatypes.h new file mode 100644 index 000000000..b7e6f7a00 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/datatypes.h @@ -0,0 +1,126 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/display.cpp new file mode 100644 index 000000000..a8037ef4f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/display.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<100){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/display.h new file mode 100644 index 000000000..2e1149286 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/display.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/golden/datatypes.log new file mode 100644 index 000000000..afdff5743 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/golden/datatypes.log @@ -0,0 +1,204 @@ +SystemC Simulation +Stimuli: 0 1 12345678 -123456 20000 +Display: 11111111 01010010 -123538 19998 -7534 F +Stimuli: 1 3 12345683 -123453 20006 +Display: 11111110 01010101 -123539 20004 -7533 F +Stimuli: 2 5 12345688 -123450 20012 +Display: 11111101 01011000 -123540 20010 -7532 F +Stimuli: 3 7 12345693 -123447 20018 +Display: 11111100 01011011 -123541 20016 -7531 F +Stimuli: 4 9 12345698 -123444 20024 +Display: 11111011 01011110 -123542 20022 -7530 F +Stimuli: 5 11 12345703 -123441 20030 +Display: 11111010 01100001 -123543 20028 -7529 F +Stimuli: 6 13 12345708 -123438 20036 +Display: 11111001 01100100 -123544 20034 -7528 F +Stimuli: 7 15 12345713 -123435 20042 +Display: 11111000 01100111 -123545 20040 -7527 F +Stimuli: 8 17 12345718 -123432 20048 +Display: 11110111 01101010 -123546 20046 -7526 F +Stimuli: 9 19 12345723 -123429 20054 +Display: 11110110 01101101 -123547 20052 -7525 F +Stimuli: 10 21 12345728 -123426 20060 +Display: 11110101 01110000 -123548 20058 -7524 F +Stimuli: 11 23 12345733 -123423 20066 +Display: 11110100 01110011 -123549 20064 -7523 F +Stimuli: 12 25 12345738 -123420 20072 +Display: 11110011 01110110 -123294 20070 -7778 F +Stimuli: 13 27 12345743 -123417 20078 +Display: 11110010 01111001 -123295 20076 -7777 F +Stimuli: 14 29 12345748 -123414 20084 +Display: 11110001 01111100 -123296 20082 -7776 F +Stimuli: 15 31 12345753 -123411 20090 +Display: 11110000 01111111 -123297 20088 -7775 F +Stimuli: 16 33 12345758 -123408 20096 +Display: 11101111 10000010 -123298 20094 -7774 F +Stimuli: 17 35 12345763 -123405 20102 +Display: 11101110 10000101 -123299 20100 -7773 F +Stimuli: 18 37 12345768 -123402 20108 +Display: 11101101 10001000 -123300 20106 -7772 F +Stimuli: 19 39 12345773 -123399 20114 +Display: 11101100 10001011 -123301 20112 -7771 F +Stimuli: 20 41 12345778 -123396 20120 +Display: 11101011 10001110 -123302 20118 -7770 F +Stimuli: 21 43 12345783 -123393 20126 +Display: 11101010 10010001 -123303 20124 -7769 F +Stimuli: 22 45 12345788 -123390 20132 +Display: 11101001 10010100 -123304 20130 -7768 F +Stimuli: 23 47 12345793 -123387 20138 +Display: 11101000 10010111 -123305 20136 -7767 F +Stimuli: 24 49 12345798 -123384 20144 +Display: 11100111 10011010 -123306 20142 -7766 F +Stimuli: 25 51 12345803 -123381 20150 +Display: 11100110 10011101 -123307 20148 -7765 F +Stimuli: 26 53 12345808 -123378 20156 +Display: 11100101 10100000 -123308 20154 -7764 F +Stimuli: 27 55 12345813 -123375 20162 +Display: 11100100 10100011 -123309 20160 -7763 F +Stimuli: 28 57 12345818 -123372 20168 +Display: 11100011 10100110 -123310 20166 -7762 F +Stimuli: 29 59 12345823 -123369 20174 +Display: 11100010 10101001 -123311 20172 -7761 F +Stimuli: 30 61 12345828 -123366 20180 +Display: 11100001 10101100 -123312 20178 -7760 F +Stimuli: 31 63 12345833 -123363 20186 +Display: 11100000 10101111 -123313 20184 -7759 F +Stimuli: 32 65 12345838 -123360 20192 +Display: 11011111 10110010 -123314 20190 -7758 F +Stimuli: 33 67 12345843 -123357 20198 +Display: 11011110 10110101 -123315 20196 -7757 F +Stimuli: 34 69 12345848 -123354 20204 +Display: 11011101 10111000 -123316 20202 -7756 F +Stimuli: 35 71 12345853 -123351 20210 +Display: 11011100 10111011 -123317 20208 -7755 F +Stimuli: 36 73 12345858 -123348 20216 +Display: 11011011 10111110 -123318 20214 -7754 F +Stimuli: 37 75 12345863 -123345 20222 +Display: 11011010 11000001 -123319 20220 -7753 F +Stimuli: 38 77 12345868 -123342 20228 +Display: 11011001 11000100 -123320 20226 -7752 F +Stimuli: 39 79 12345873 -123339 20234 +Display: 11011000 11000111 -123321 20232 -7751 F +Stimuli: 40 81 12345878 -123336 20240 +Display: 11010111 11001010 -123322 20238 -7750 F +Stimuli: 41 83 12345883 -123333 20246 +Display: 11010110 11001101 -123323 20244 -7749 F +Stimuli: 42 85 12345888 -123330 20252 +Display: 11010101 11010000 -123324 20250 -7748 F +Stimuli: 43 87 12345893 -123327 20258 +Display: 11010100 11010011 -123325 20256 -7747 F +Stimuli: 44 89 12345898 -123324 20264 +Display: 11010011 11010110 -123326 20262 -7746 F +Stimuli: 45 91 12345903 -123321 20270 +Display: 11010010 11011001 -123327 20268 -7745 F +Stimuli: 46 93 12345908 -123318 20276 +Display: 11010001 11011100 -123328 20274 -7744 F +Stimuli: 47 95 12345913 -123315 20282 +Display: 11010000 11011111 -123329 20280 -7743 F +Stimuli: 48 97 12345918 -123312 20288 +Display: 11001111 11100010 -123330 20286 -7742 F +Stimuli: 49 99 12345923 -123309 20294 +Display: 11001110 11100101 -123331 20292 -7741 F +Stimuli: 50 101 12345928 -123306 20300 +Display: 11001101 11101000 -123332 20298 -7740 F +Stimuli: 51 103 12345933 -123303 20306 +Display: 11001100 11101011 -123333 20304 -7739 F +Stimuli: 52 105 12345938 -123300 20312 +Display: 11001011 11101110 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b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/main.cpp new file mode 100644 index 000000000..baafeba5d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/main.cpp @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/stimulus.cpp new file mode 100644 index 000000000..ebcfe7bf0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/stimulus.cpp @@ -0,0 +1,82 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + + tmp1 = "00000000"; + tmp2 = "00000001"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = 'R'; + + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " << tmp5 << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 2; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp6 = tmp6 + 4; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/stimulus.h new file mode 100644 index 000000000..cf0a3e621 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/stimulus.h @@ -0,0 +1,90 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/decrement.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/decrement.cpp new file mode 100644 index 000000000..86f654680 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/decrement.cpp @@ -0,0 +1,92 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + decrement.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "decrement.h" + +void decrement::entry(){ + + #define ONE 1 + const int eins = 1; + int tmp1; + sc_bigint<4> tmp2; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + + // + // main loop + // + + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + + //execute simple operations + tmp1 = tmp1 - 1; + tmp1 = tmp1 - ONE; + tmp1 = tmp1 - eins; + tmp1--; + tmp2 = tmp2 - 1; + tmp2 = tmp2 - ONE; + tmp2 = tmp2 - eins; + tmp2--; + + out_ack.write(true); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/decrement.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/decrement.f new file mode 100644 index 000000000..894de102e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/decrement.f @@ -0,0 +1,4 @@ +decrement/stimulus.cpp +decrement/display.cpp +decrement/decrement.cpp +decrement/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/decrement.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/decrement.h new file mode 100644 index 000000000..cf19214a9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/decrement.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + decrement.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( decrement ) +{ + SC_HAS_PROCESS( decrement ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal<int>& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + decrement ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<bool>& OUT_ACK, + sc_signal<int>& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/display.cpp new file mode 100644 index 000000000..c1192ec7b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + + while(counter++<100){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/display.h new file mode 100644 index 000000000..80f2aa3cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/display.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<bool>& in_valid; // Input port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal<int>& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/golden/decrement.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/golden/decrement.log new file mode 100644 index 000000000..10fc11b2e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/golden/decrement.log @@ -0,0 +1,204 @@ +SystemC Simulation +Stimuli: 0 1 +Display: -4 1101 +Stimuli: 1 2 +Display: -3 1110 +Stimuli: 2 3 +Display: -2 1111 +Stimuli: 3 4 +Display: -1 0000 +Stimuli: 4 5 +Display: 0 0001 +Stimuli: 5 6 +Display: 1 0010 +Stimuli: 6 7 +Display: 2 0011 +Stimuli: 7 -8 +Display: 3 0100 +Stimuli: 8 -7 +Display: 4 0101 +Stimuli: 9 -6 +Display: 5 0110 +Stimuli: 10 -5 +Display: 6 0111 +Stimuli: 11 -4 +Display: 7 1000 +Stimuli: 12 -3 +Display: 8 1001 +Stimuli: 13 -2 +Display: 9 1010 +Stimuli: 14 -1 +Display: 10 1011 +Stimuli: 15 0 +Display: 11 1100 +Stimuli: 16 1 +Display: 12 1101 +Stimuli: 17 2 +Display: 13 1110 +Stimuli: 18 3 +Display: 14 1111 +Stimuli: 19 4 +Display: 15 0000 +Stimuli: 20 5 +Display: 16 0001 +Stimuli: 21 6 +Display: 17 0010 +Stimuli: 22 7 +Display: 18 0011 +Stimuli: 23 -8 +Display: 19 0100 +Stimuli: 24 -7 +Display: 20 0101 +Stimuli: 25 -6 +Display: 21 0110 +Stimuli: 26 -5 +Display: 22 0111 +Stimuli: 27 -4 +Display: 23 1000 +Stimuli: 28 -3 +Display: 24 1001 +Stimuli: 29 -2 +Display: 25 1010 +Stimuli: 30 -1 +Display: 26 1011 +Stimuli: 31 0 +Display: 27 1100 +Stimuli: 32 1 +Display: 28 1101 +Stimuli: 33 2 +Display: 29 1110 +Stimuli: 34 3 +Display: 30 1111 +Stimuli: 35 4 +Display: 31 0000 +Stimuli: 36 5 +Display: 32 0001 +Stimuli: 37 6 +Display: 33 0010 +Stimuli: 38 7 +Display: 34 0011 +Stimuli: 39 -8 +Display: 35 0100 +Stimuli: 40 -7 +Display: 36 0101 +Stimuli: 41 -6 +Display: 37 0110 +Stimuli: 42 -5 +Display: 38 0111 +Stimuli: 43 -4 +Display: 39 1000 +Stimuli: 44 -3 +Display: 40 1001 +Stimuli: 45 -2 +Display: 41 1010 +Stimuli: 46 -1 +Display: 42 1011 +Stimuli: 47 0 +Display: 43 1100 +Stimuli: 48 1 +Display: 44 1101 +Stimuli: 49 2 +Display: 45 1110 +Stimuli: 50 3 +Display: 46 1111 +Stimuli: 51 4 +Display: 47 0000 +Stimuli: 52 5 +Display: 48 0001 +Stimuli: 53 6 +Display: 49 0010 +Stimuli: 54 7 +Display: 50 0011 +Stimuli: 55 -8 +Display: 51 0100 +Stimuli: 56 -7 +Display: 52 0101 +Stimuli: 57 -6 +Display: 53 0110 +Stimuli: 58 -5 +Display: 54 0111 +Stimuli: 59 -4 +Display: 55 1000 +Stimuli: 60 -3 +Display: 56 1001 +Stimuli: 61 -2 +Display: 57 1010 +Stimuli: 62 -1 +Display: 58 1011 +Stimuli: 63 0 +Display: 59 1100 +Stimuli: 64 1 +Display: 60 1101 +Stimuli: 65 2 +Display: 61 1110 +Stimuli: 66 3 +Display: 62 1111 +Stimuli: 67 4 +Display: 63 0000 +Stimuli: 68 5 +Display: 64 0001 +Stimuli: 69 6 +Display: 65 0010 +Stimuli: 70 7 +Display: 66 0011 +Stimuli: 71 -8 +Display: 67 0100 +Stimuli: 72 -7 +Display: 68 0101 +Stimuli: 73 -6 +Display: 69 0110 +Stimuli: 74 -5 +Display: 70 0111 +Stimuli: 75 -4 +Display: 71 1000 +Stimuli: 76 -3 +Display: 72 1001 +Stimuli: 77 -2 +Display: 73 1010 +Stimuli: 78 -1 +Display: 74 1011 +Stimuli: 79 0 +Display: 75 1100 +Stimuli: 80 1 +Display: 76 1101 +Stimuli: 81 2 +Display: 77 1110 +Stimuli: 82 3 +Display: 78 1111 +Stimuli: 83 4 +Display: 79 0000 +Stimuli: 84 5 +Display: 80 0001 +Stimuli: 85 6 +Display: 81 0010 +Stimuli: 86 7 +Display: 82 0011 +Stimuli: 87 -8 +Display: 83 0100 +Stimuli: 88 -7 +Display: 84 0101 +Stimuli: 89 -6 +Display: 85 0110 +Stimuli: 90 -5 +Display: 86 0111 +Stimuli: 91 -4 +Display: 87 1000 +Stimuli: 92 -3 +Display: 88 1001 +Stimuli: 93 -2 +Display: 89 1010 +Stimuli: 94 -1 +Display: 90 1011 +Stimuli: 95 0 +Display: 91 1100 +Stimuli: 96 1 +Display: 92 1101 +Stimuli: 97 2 +Display: 93 1110 +Stimuli: 98 3 +Display: 94 1111 +Stimuli: 99 4 +Display: 95 0000 +Stimuli: 100 5 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/main.cpp new file mode 100644 index 000000000..89e3a7295 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/main.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "decrement.h" + +int sc_main(int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal_bool_vector result_line2; + + // initialization to fix regressions - ali + output_valid = false; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + input_valid, + ack); + + decrement decrement1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + input_valid, + ack, + result_line1, + result_line2, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + output_valid); + + sc_start(); + + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/stimulus.cpp new file mode 100644 index 000000000..924a46e69 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/stimulus.cpp @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + int tmp1; + sc_signed tmp2(4); + + tmp1 = 0; + tmp2 = "0001"; + + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + cout << "Stimuli: " << tmp1 << " " << tmp2 << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/stimulus.h new file mode 100644 index 000000000..92e32db22 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/decrement/stimulus.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset ; + sc_signal<int>& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal<int>& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/common.h new file mode 100644 index 000000000..60baad076 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/common.h @@ -0,0 +1,49 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<5> > sc_signal_bool_vector5; +typedef sc_signal<sc_bv<6> > sc_signal_bool_vector6; +typedef sc_signal<sc_bv<7> > sc_signal_bool_vector7; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/display.cpp new file mode 100644 index 000000000..47832f313 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<100){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << " " << in_value5.read() << endl; + do { wait(); } while ( in_valid == true); + } + wait(); + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/display.h new file mode 100644 index 000000000..377dd8cbd --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/display.h @@ -0,0 +1,84 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector4& in_value1; // Output port + const sc_signal_bool_vector5& in_value2; // Output port + const sc_signal_bool_vector6& in_value3; // Output port + const sc_signal_bool_vector7& in_value4; // Output port + const sc_signal_bool_vector8& in_value5; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector4& IN_VALUE1, + const sc_signal_bool_vector5& IN_VALUE2, + const sc_signal_bool_vector6& IN_VALUE3, + const sc_signal_bool_vector7& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/golden/sharing.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/golden/sharing.log new file mode 100644 index 000000000..1789b5327 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/golden/sharing.log @@ -0,0 +1,204 @@ +SystemC Simulation +Stimuli: 0 1 2 3 4 +Display: 1100 11101 111110 0000001 00000010 +Stimuli: 1 2 3 4 5 +Display: 1101 11110 111111 0000010 00000011 +Stimuli: 2 3 4 5 6 +Display: 1110 11111 000000 0000011 00000100 +Stimuli: 3 4 5 6 7 +Display: 1111 00000 000001 0000100 00000101 +Stimuli: 4 5 6 7 8 +Display: 0000 00001 000010 0000101 00000110 +Stimuli: 5 6 7 8 9 +Display: 0001 00010 000011 0000110 00000111 +Stimuli: 6 7 8 9 10 +Display: 0010 00011 000100 0000111 00001000 +Stimuli: 7 8 9 10 11 +Display: 0011 00100 000101 0001000 00001001 +Stimuli: -8 9 10 11 12 +Display: 0100 00101 000110 0001001 00001010 +Stimuli: -7 10 11 12 13 +Display: 0101 00110 000111 0001010 00001011 +Stimuli: -6 11 12 13 14 +Display: 0110 00111 001000 0001011 00001100 +Stimuli: -5 12 13 14 15 +Display: 0111 01000 001001 0001100 00001101 +Stimuli: -4 13 14 15 16 +Display: 1000 01001 001010 0001101 00001110 +Stimuli: -3 14 15 16 17 +Display: 1001 01010 001011 0001110 00001111 +Stimuli: -2 15 16 17 18 +Display: 1010 01011 001100 0001111 00010000 +Stimuli: -1 -16 17 18 19 +Display: 1011 01100 001101 0010000 00010001 +Stimuli: 0 -15 18 19 20 +Display: 1100 01101 001110 0010001 00010010 +Stimuli: 1 -14 19 20 21 +Display: 1101 01110 001111 0010010 00010011 +Stimuli: 2 -13 20 21 22 +Display: 1110 01111 010000 0010011 00010100 +Stimuli: 3 -12 21 22 23 +Display: 1111 10000 010001 0010100 00010101 +Stimuli: 4 -11 22 23 24 +Display: 0000 10001 010010 0010101 00010110 +Stimuli: 5 -10 23 24 25 +Display: 0001 10010 010011 0010110 00010111 +Stimuli: 6 -9 24 25 26 +Display: 0010 10011 010100 0010111 00011000 +Stimuli: 7 -8 25 26 27 +Display: 0011 10100 010101 0011000 00011001 +Stimuli: -8 -7 26 27 28 +Display: 0100 10101 010110 0011001 00011010 +Stimuli: -7 -6 27 28 29 +Display: 0101 10110 010111 0011010 00011011 +Stimuli: -6 -5 28 29 30 +Display: 0110 10111 011000 0011011 00011100 +Stimuli: -5 -4 29 30 31 +Display: 0111 11000 011001 0011100 00011101 +Stimuli: -4 -3 30 31 32 +Display: 1000 11001 011010 0011101 00011110 +Stimuli: -3 -2 31 32 33 +Display: 1001 11010 011011 0011110 00011111 +Stimuli: -2 -1 -32 33 34 +Display: 1010 11011 011100 0011111 00100000 +Stimuli: -1 0 -31 34 35 +Display: 1011 11100 011101 0100000 00100001 +Stimuli: 0 1 -30 35 36 +Display: 1100 11101 011110 0100001 00100010 +Stimuli: 1 2 -29 36 37 +Display: 1101 11110 011111 0100010 00100011 +Stimuli: 2 3 -28 37 38 +Display: 1110 11111 100000 0100011 00100100 +Stimuli: 3 4 -27 38 39 +Display: 1111 00000 100001 0100100 00100101 +Stimuli: 4 5 -26 39 40 +Display: 0000 00001 100010 0100101 00100110 +Stimuli: 5 6 -25 40 41 +Display: 0001 00010 100011 0100110 00100111 +Stimuli: 6 7 -24 41 42 +Display: 0010 00011 100100 0100111 00101000 +Stimuli: 7 8 -23 42 43 +Display: 0011 00100 100101 0101000 00101001 +Stimuli: -8 9 -22 43 44 +Display: 0100 00101 100110 0101001 00101010 +Stimuli: -7 10 -21 44 45 +Display: 0101 00110 100111 0101010 00101011 +Stimuli: -6 11 -20 45 46 +Display: 0110 00111 101000 0101011 00101100 +Stimuli: -5 12 -19 46 47 +Display: 0111 01000 101001 0101100 00101101 +Stimuli: -4 13 -18 47 48 +Display: 1000 01001 101010 0101101 00101110 +Stimuli: -3 14 -17 48 49 +Display: 1001 01010 101011 0101110 00101111 +Stimuli: -2 15 -16 49 50 +Display: 1010 01011 101100 0101111 00110000 +Stimuli: -1 -16 -15 50 51 +Display: 1011 01100 101101 0110000 00110001 +Stimuli: 0 -15 -14 51 52 +Display: 1100 01101 101110 0110001 00110010 +Stimuli: 1 -14 -13 52 53 +Display: 1101 01110 101111 0110010 00110011 +Stimuli: 2 -13 -12 53 54 +Display: 1110 01111 110000 0110011 00110100 +Stimuli: 3 -12 -11 54 55 +Display: 1111 10000 110001 0110100 00110101 +Stimuli: 4 -11 -10 55 56 +Display: 0000 10001 110010 0110101 00110110 +Stimuli: 5 -10 -9 56 57 +Display: 0001 10010 110011 0110110 00110111 +Stimuli: 6 -9 -8 57 58 +Display: 0010 10011 110100 0110111 00111000 +Stimuli: 7 -8 -7 58 59 +Display: 0011 10100 110101 0111000 00111001 +Stimuli: -8 -7 -6 59 60 +Display: 0100 10101 110110 0111001 00111010 +Stimuli: -7 -6 -5 60 61 +Display: 0101 10110 110111 0111010 00111011 +Stimuli: -6 -5 -4 61 62 +Display: 0110 10111 111000 0111011 00111100 +Stimuli: -5 -4 -3 62 63 +Display: 0111 11000 111001 0111100 00111101 +Stimuli: -4 -3 -2 63 64 +Display: 1000 11001 111010 0111101 00111110 +Stimuli: -3 -2 -1 -64 65 +Display: 1001 11010 111011 0111110 00111111 +Stimuli: -2 -1 0 -63 66 +Display: 1010 11011 111100 0111111 01000000 +Stimuli: -1 0 1 -62 67 +Display: 1011 11100 111101 1000000 01000001 +Stimuli: 0 1 2 -61 68 +Display: 1100 11101 111110 1000001 01000010 +Stimuli: 1 2 3 -60 69 +Display: 1101 11110 111111 1000010 01000011 +Stimuli: 2 3 4 -59 70 +Display: 1110 11111 000000 1000011 01000100 +Stimuli: 3 4 5 -58 71 +Display: 1111 00000 000001 1000100 01000101 +Stimuli: 4 5 6 -57 72 +Display: 0000 00001 000010 1000101 01000110 +Stimuli: 5 6 7 -56 73 +Display: 0001 00010 000011 1000110 01000111 +Stimuli: 6 7 8 -55 74 +Display: 0010 00011 000100 1000111 01001000 +Stimuli: 7 8 9 -54 75 +Display: 0011 00100 000101 1001000 01001001 +Stimuli: -8 9 10 -53 76 +Display: 0100 00101 000110 1001001 01001010 +Stimuli: -7 10 11 -52 77 +Display: 0101 00110 000111 1001010 01001011 +Stimuli: -6 11 12 -51 78 +Display: 0110 00111 001000 1001011 01001100 +Stimuli: -5 12 13 -50 79 +Display: 0111 01000 001001 1001100 01001101 +Stimuli: -4 13 14 -49 80 +Display: 1000 01001 001010 1001101 01001110 +Stimuli: -3 14 15 -48 81 +Display: 1001 01010 001011 1001110 01001111 +Stimuli: -2 15 16 -47 82 +Display: 1010 01011 001100 1001111 01010000 +Stimuli: -1 -16 17 -46 83 +Display: 1011 01100 001101 1010000 01010001 +Stimuli: 0 -15 18 -45 84 +Display: 1100 01101 001110 1010001 01010010 +Stimuli: 1 -14 19 -44 85 +Display: 1101 01110 001111 1010010 01010011 +Stimuli: 2 -13 20 -43 86 +Display: 1110 01111 010000 1010011 01010100 +Stimuli: 3 -12 21 -42 87 +Display: 1111 10000 010001 1010100 01010101 +Stimuli: 4 -11 22 -41 88 +Display: 0000 10001 010010 1010101 01010110 +Stimuli: 5 -10 23 -40 89 +Display: 0001 10010 010011 1010110 01010111 +Stimuli: 6 -9 24 -39 90 +Display: 0010 10011 010100 1010111 01011000 +Stimuli: 7 -8 25 -38 91 +Display: 0011 10100 010101 1011000 01011001 +Stimuli: -8 -7 26 -37 92 +Display: 0100 10101 010110 1011001 01011010 +Stimuli: -7 -6 27 -36 93 +Display: 0101 10110 010111 1011010 01011011 +Stimuli: -6 -5 28 -35 94 +Display: 0110 10111 011000 1011011 01011100 +Stimuli: -5 -4 29 -34 95 +Display: 0111 11000 011001 1011100 01011101 +Stimuli: -4 -3 30 -33 96 +Display: 1000 11001 011010 1011101 01011110 +Stimuli: -3 -2 31 -32 97 +Display: 1001 11010 011011 1011110 01011111 +Stimuli: -2 -1 -32 -31 98 +Display: 1010 11011 011100 1011111 01100000 +Stimuli: -1 0 -31 -30 99 +Display: 1011 11100 011101 1100000 01100001 +Stimuli: 0 1 -30 -29 100 +Display: 1100 11101 011110 1100001 01100010 +Stimuli: 1 2 -29 -28 101 +Display: 1101 11110 011111 1100010 01100011 +Stimuli: 2 3 -28 -27 102 +Display: 1110 11111 100000 1100011 01100100 +Stimuli: 3 4 -27 -26 103 +Display: 1111 00000 100001 1100100 01100101 +Stimuli: 4 5 -26 -25 104 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/main.cpp new file mode 100644 index 000000000..82b0ce24a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/main.cpp @@ -0,0 +1,108 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "sharing.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector4 stimulus_line1; + sc_signal_bool_vector5 stimulus_line2; + sc_signal_bool_vector6 stimulus_line3; + sc_signal_bool_vector7 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector4 result_line1; + sc_signal_bool_vector5 result_line2; + sc_signal_bool_vector6 result_line3; + sc_signal_bool_vector7 result_line4; + sc_signal_bool_vector8 result_line5; + + // SYL 990908 - Initialize some signals -- logs diffed + // when I hacked the simulation kernel. + reset = 0; + input_valid = 0; + ack = 0; + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + ack); + + sharing sharing1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/sharing.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/sharing.cpp new file mode 100644 index 000000000..8215ce41d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/sharing.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "sharing.h" + +void sharing::entry(){ + + sc_bigint<4> tmp1; + sc_biguint<5> tmp2; + sc_bigint<6> tmp3; + sc_biguint<7> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + out_ack.write(true); + + //execute simple operations + tmp1 = tmp1 - 4; + tmp2 = tmp2 - 4; + tmp3 = tmp3 - 4; + tmp4 = tmp4 - 2; + tmp5 = tmp5 - 2; + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + wait(); + } +} + +// EOF + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/sharing.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/sharing.f new file mode 100644 index 000000000..0c0f3ff29 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/sharing.f @@ -0,0 +1,4 @@ +sharing/stimulus.cpp +sharing/display.cpp +sharing/sharing.cpp +sharing/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/sharing.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/sharing.h new file mode 100644 index 000000000..ca7191f3d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/sharing.h @@ -0,0 +1,113 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( sharing ) +{ + SC_HAS_PROCESS( sharing ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector4& in_value1; // Input port + const sc_signal_bool_vector5& in_value2; // Input port + const sc_signal_bool_vector6& in_value3; // Input port + const sc_signal_bool_vector7& in_value4; // Input port + const sc_signal_bool_vector8& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector4& out_value1; // Output port + sc_signal_bool_vector5& out_value2; // Output port + sc_signal_bool_vector6& out_value3; // Output port + sc_signal_bool_vector7& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + sharing ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector4& IN_VALUE1, + const sc_signal_bool_vector5& IN_VALUE2, + const sc_signal_bool_vector6& IN_VALUE3, + const sc_signal_bool_vector7& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector4& OUT_VALUE1, + sc_signal_bool_vector5& OUT_VALUE2, + sc_signal_bool_vector6& OUT_VALUE3, + sc_signal_bool_vector7& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/stimulus.cpp new file mode 100644 index 000000000..4c05ea844 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/stimulus.cpp @@ -0,0 +1,77 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(4); + sc_signed tmp2(5); + sc_signed tmp3(6); + sc_signed tmp4(7); + sc_signed tmp5(8); + + tmp1 = "0b0000"; + tmp2 = "0b00001"; + tmp3 = "0b000010"; + tmp4 = "0b0000011"; + tmp5 = "0b00000100"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " << tmp5 << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 1; + tmp5 = tmp5 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/stimulus.h new file mode 100644 index 000000000..9a8f62092 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/sharing/stimulus.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector4& out_value1; // Output port + sc_signal_bool_vector5& out_value2; // Output port + sc_signal_bool_vector6& out_value3; // Output port + sc_signal_bool_vector7& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector4& OUT_VALUE1, + sc_signal_bool_vector5& OUT_VALUE2, + sc_signal_bool_vector6& OUT_VALUE3, + sc_signal_bool_vector7& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/common.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/common.h new file mode 100644 index 000000000..8a560ac63 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/display.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/display.h new file mode 100644 index 000000000..a11ccd275 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal_bool_vector4& in_data2; // Input port + const sc_signal_bool_vector4& in_data3; // Input port + const sc_signal_bool_vector8& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal_bool_vector4& IN_DATA2, + const sc_signal_bool_vector4& IN_DATA3, + const sc_signal_bool_vector8& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/golden/subtract.log b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/golden/subtract.log new file mode 100644 index 000000000..9486fc2bd --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/golden/subtract.log @@ -0,0 +1,31 @@ +SystemC Simulation +Stimuli : 255 -1 15 -1 255 at 23 ns +Display : 254 1110 1110 11111110 11111110 at 27 ns +Display : 254 1110 1110 11111110 11111110 at 29 ns +Display : 252 1100 1100 11111100 11111100 at 31 ns +Display : -2 1110 1110 11111110 11111110 at 34 ns +Display : -256 0000 0000 00000000 00000000 at 37 ns +Display : 0 0000 0000 00000000 00000000 at 40 ns +Stimuli : 254 -2 14 -2 254 at 44 ns +Display : 253 1101 1101 11111101 11111101 at 48 ns +Display : 253 1101 1101 11111101 11111101 at 50 ns +Display : 251 1011 1011 11111011 11111011 at 52 ns +Display : -3 1101 1101 11111101 11111101 at 55 ns +Display : -257 1111 1111 11111111 11111111 at 58 ns +Display : 16 0000 0000 00000000 00000001 at 61 ns +Stimuli : 253 -3 13 -3 253 at 65 ns +Display : 252 1100 1100 11111100 11111100 at 69 ns +Display : 252 1100 1100 11111100 11111100 at 71 ns +Display : 250 1010 1010 11111010 11111010 at 73 ns +Display : -4 1100 1100 11111100 11111100 at 76 ns +Display : -258 1110 1110 11111110 11111110 at 79 ns +Display : 16 0000 0000 00000000 00000010 at 82 ns +Stimuli : 252 -4 12 -4 252 at 86 ns +Display : 251 1011 1011 11111011 11111011 at 90 ns +Display : 251 1011 1011 11111011 11111011 at 92 ns +Display : 249 1001 1001 11111001 11111001 at 94 ns +Display : -5 1011 1011 11111011 11111011 at 97 ns +Display : -259 1101 1101 11111101 11111101 at 100 ns +Display : 16 0000 0000 00000000 00000011 at 103 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/main.cpp new file mode 100644 index 000000000..86a1b91b1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "subtract.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector4 stimulus_line3; + sc_signal_bool_vector8 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector4 result_line3; + sc_signal_bool_vector8 result_line4; + sc_signal_bool_vector8 result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + subtraction subtraction1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/stimulus.cpp new file mode 100644 index 000000000..8856451d4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/stimulus.cpp @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + int send_value1 = 255; + sc_signed send_value2(4); + sc_unsigned send_value3(4); + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + reset.write(true); + out_valid.write(false); + send_value2 = 15; + send_value3 = 15; + send_value4 = 255; + send_value5 = 255; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + while(true){ + wait(20); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1--; + send_value2 -= 1; + send_value3 -= 1; + send_value4 -= 1; + send_value5 -= 1; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/stimulus.h new file mode 100644 index 000000000..1d675ef5c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal_bool_vector4& out_stimulus2; + sc_signal_bool_vector4& out_stimulus3; + sc_signal_bool_vector8& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal_bool_vector4& OUT_STIMULUS2, + sc_signal_bool_vector4& OUT_STIMULUS3, + sc_signal_bool_vector8& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/subtract.cpp b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/subtract.cpp new file mode 100644 index 000000000..a3fc5ee4b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/subtract.cpp @@ -0,0 +1,166 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + subtract.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "subtract.h" + +void subtraction::entry(){ + + int tmp1; + sc_bigint<4> tmp2; + sc_biguint<4> tmp3; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute operations + tmp1 = tmp1 - 1; + tmp2 = tmp2 - 1; + tmp3 = tmp3 - 1; + tmp4 = tmp4 - 1; + tmp5 = tmp5 - 1; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + // write outputs + out_value1.write(tmp1--); + out_value2.write(tmp2--); + out_value3.write(tmp3--); + out_value4.write(tmp4--); + out_value5.write(tmp5--); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + // write outputs + out_value1.write(--tmp1); + out_value2.write(--tmp2); + out_value3.write(--tmp3); + out_value4.write(--tmp4); + out_value5.write(--tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute operations + tmp1 = tmp1 - 254; + tmp2 = tmp2 - 14; + tmp3 = tmp3 - 14; + tmp4 = tmp4 - 254; + tmp5 = tmp5 - 254; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute operations + tmp1 -= 254; + tmp2 -= 14; + tmp3 -= 14; + tmp4 -= 254; + tmp5 -= 254; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + //execute operations with signed and unsigned mix and mixed bit width + tmp1 = (tmp3 - tmp2).to_int(); + tmp2 = tmp2 - tmp4; + tmp3 = tmp3 - tmp5; + tmp4 = tmp4 - tmp5; + tmp5 = tmp4 - tmp5; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/subtract.f b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/subtract.f new file mode 100644 index 000000000..fe9d1d54d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/subtract.f @@ -0,0 +1,4 @@ +subtract/stimulus.cpp +subtract/display.cpp +subtract/subtract.cpp +subtract/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/subtract.h b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/subtract.h new file mode 100644 index 000000000..bac065909 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/subtract/subtract.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + subtract.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( subtraction ) +{ + SC_HAS_PROCESS( subtraction ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; + const sc_signal_bool_vector4& in_value3; + const sc_signal_bool_vector8& in_value4; + const sc_signal_bool_vector8& in_value5; + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal_bool_vector4& out_value2; + sc_signal_bool_vector4& out_value3; + sc_signal_bool_vector8& out_value4; + sc_signal_bool_vector8& out_value5; + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + subtraction( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector4& IN_VALUE3, + const sc_signal_bool_vector8& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector4& OUT_VALUE3, + sc_signal_bool_vector8& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.cpp new file mode 100644 index 000000000..5a8b81974 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + and_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "and_1.h" + +void and_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = tmp1 & 0x0f & 0x12; + tmp2 = tmp2 & 0x0f & 0x13 ; + tmp3 = tmp3 & tmp3_tmp; + tmp4 = tmp4 & 0x0f & 0x14 ; + tmp5 = tmp5 & 0x0f & 0x15 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 &= 0x03; + tmp2 &= 0x03; + tmp3 &= tmp3_tmp; + tmp4 &= 0x03; + tmp5 &= 0x03; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.f new file mode 100644 index 000000000..606aecf73 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.f @@ -0,0 +1,4 @@ +and_1/stimulus.cpp +and_1/display.cpp +and_1/and_1.cpp +and_1/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.h new file mode 100644 index 000000000..2e88eb916 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/and_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + and_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( and_1 ) +{ + SC_HAS_PROCESS( and_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + and_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.h new file mode 100644 index 000000000..59a19b5f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/golden/and_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/golden/and_1.log new file mode 100644 index 000000000..dfc053eb3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/golden/and_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : 0 1 00000001 00000000 00000001 at 17 ns +Display : 0 1 00000001 00000000 00000001 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : 0 0 00001100 00000100 00000100 at 28 ns +Display : 0 0 00000000 00000000 00000000 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : 2 3 00000111 00000100 00000101 at 39 ns +Display : 2 3 00000011 00000000 00000001 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : 2 2 00000010 00000000 00000000 at 50 ns +Display : 2 2 00000010 00000000 00000000 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : 0 1 00001101 00000100 00000101 at 61 ns +Display : 0 1 00000001 00000000 00000001 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : 0 0 00001000 00000000 00000000 at 72 ns +Display : 0 0 00000000 00000000 00000000 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : 2 3 00000011 00000000 00000001 at 83 ns +Display : 2 3 00000011 00000000 00000001 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : 2 2 00001110 00000100 00000100 at 94 ns +Display : 2 2 00000010 00000000 00000000 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : 0 1 00001001 00000000 00000001 at 105 ns +Display : 0 1 00000001 00000000 00000001 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : 0 0 00000100 00000100 00000100 at 116 ns +Display : 0 0 00000000 00000000 00000000 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : 2 3 00001111 00000100 00000101 at 127 ns +Display : 2 3 00000011 00000000 00000001 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : 2 2 00001010 00000000 00000000 at 138 ns +Display : 2 2 00000010 00000000 00000000 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/main.cpp new file mode 100644 index 000000000..79b1c4704 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "and_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + and_1 and1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.cpp new file mode 100644 index 000000000..8664cf6ec --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_bigint<8> send_value4; + sc_biguint<8> send_value5; + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/and_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/common.h new file mode 100644 index 000000000..8976a26a2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; +typedef sc_signal<sc_lv<4> > sc_signal_logic_vector4; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.cpp new file mode 100644 index 000000000..0cbeaaf72 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.cpp @@ -0,0 +1,142 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + bool tmp7; + bool tmp7r; + sc_bv<4> tmp8; + sc_bv<4> tmp8r; + sc_lv<4> tmp9; + sc_lv<4> tmp9r; + +// define 1 dimensional array + int tmpa[2]; + char tmpb[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmpa[0] = 12; + tmpa[1] = 127; + tmpb[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmpb[0] = in_value7.read(); + tmp7 = in_value8.read(); + tmp8 = in_value9.read(); + tmp9 = in_value10.read(); + + out_ack.write(true); + + //execute mixed data type and operations + + // signed(8) <- signed(8) & unsigned(8) + tmp1r = tmp1 & tmp2; + // unsigned(8) <- char & long + tmp2r = tmp6 & tmp3; + // long <- int & char + tmp3r = tmp4 & tmp6; + // int <- int & short + tmp4r = tmp4 & tmp5; + // short <- short & const + tmp5r = tmp5 & 5; + // char <- char_array[0] & int_array[1] + tmp6r = tmpb[0] & tmpa[1]; + // bool <- bool & bool; + tmp7r = tmp7 & tmp7; + // sc_bool_vector(4) <- sc_bool_vector(4) & sc_logic_vector(4) + tmp8r = tmp8 & tmp9; + // sc_logic_vector(4) <- sc_bool_vector(4) & "0111" + tmp9r = tmp9 & sc_bv<4>( "0111" ); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_value7.write(tmp7r); + out_value8.write(tmp8r); + out_value9.write(tmp9r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.h new file mode 100644 index 000000000..547119370 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/datatypes.h @@ -0,0 +1,146 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector8& in_value1; // Input port + const sc_signal_bool_vector8& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_value8 ; + const sc_signal_bool_vector4& in_value9; // Input port + const sc_signal_logic_vector4& in_value10; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_value7; // Output port + sc_signal_bool_vector4& out_value8; // Output port + sc_signal_logic_vector4& out_value9; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALUE8, + const sc_signal_bool_vector4& IN_VALUE9, + const sc_signal_logic_vector4& IN_VALUE10, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALUE7, + sc_signal_bool_vector4& OUT_VALUE8, + sc_signal_logic_vector4& OUT_VALUE9, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_value10 (IN_VALUE10), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.cpp new file mode 100644 index 000000000..0c6fdf20e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<40){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << " " << in_value7.read() << " " << in_value8.read() << " " << in_value9.read() <<endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.h new file mode 100644 index 000000000..3bc92072f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/display.h @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector8& in_value1; // Output port + const sc_signal_bool_vector8& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_value7; // Output port + const sc_signal_bool_vector4& in_value8; // Output port + const sc_signal_logic_vector4& in_value9; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALUE7, + const sc_signal_bool_vector4& IN_VALUE8, + const sc_signal_logic_vector4& IN_VALUE9, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/golden/datatypes.log new file mode 100644 index 000000000..0af19af8b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/golden/datatypes.log @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 00000000 00000100 0 3072 0 A 1 0000 0010 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 00000011 00000000 0 3074 4 B 0 0010 0011 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 00000000 00000000 4 3076 4 C 1 0000 0100 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 00000001 00000100 0 3072 0 D 0 0100 0101 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 00000100 00100000 4 3080 0 E 1 0100 0110 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 00000111 00100100 4 3086 4 F 0 0110 0111 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 00000000 00100100 0 3136 4 G 1 0000 0000 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 00000001 00100000 4 3136 0 H 0 1000 0001 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 00000000 00100100 0 3152 0 I 1 1000 0010 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 00000011 00100000 0 3154 4 J 0 1010 0011 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 00001000 00000000 4 3164 4 K 1 1000 0100 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 00001001 00000100 32 3168 0 L 0 1100 0101 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 +Display: 00001100 00000000 36 3168 0 M 1 1100 0110 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 00001111 00000100 36 3174 4 N 0 1110 0111 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 00010000 00000100 32 3168 4 O 1 0000 0000 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 00010001 00000000 36 3176 0 P 0 0000 0001 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 00010000 00000100 32 3200 0 Q 1 0000 0010 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 00010011 00100000 32 3202 4 R 0 0010 0011 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 00010000 00100000 36 3204 4 S 1 0000 0100 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 00010001 00100100 32 3216 0 T 0 0100 0101 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 00010100 00100000 36 3224 0 U 1 0100 0110 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 00010111 00100100 36 3230 4 V 0 0110 0111 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 00000000 00100100 0 3584 4 W 1 0000 0000 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 00000001 00000000 4 3584 0 X 0 1000 0001 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 00000000 00000100 0 3584 0 Y 1 1000 0010 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 00000011 00000000 0 3586 4 Z 0 1010 0011 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 00001000 00000000 4 3596 4 [ 1 1000 0100 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 00001001 00000100 0 3584 0 \ 0 1100 0101 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 00001100 00000000 4 3584 0 ] 1 1100 0110 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 00001111 00000100 4 3590 4 ^ 0 1110 0111 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 00000000 00100100 0 3600 4 _ 1 0000 0000 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 00000001 00100000 4 3608 0 ` 0 0000 0001 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 00000000 00100100 32 3616 0 a 1 0000 0010 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 00000011 00100000 32 3618 4 b 0 0010 0011 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 00000000 00100000 36 3620 4 c 1 0000 0100 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 00000001 00100100 32 3616 0 d 0 0100 0101 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 00000100 00000000 36 3624 0 e 1 0100 0110 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 00000111 00000100 36 3630 4 f 0 0110 0111 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 00100000 00000100 32 3584 4 g 1 0000 0000 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 00100001 00000000 36 3584 0 h 0 1000 0001 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/main.cpp new file mode 100644 index 000000000..ae4db66ee --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/main.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector8 stimulus_line1; + sc_signal_bool_vector8 stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> stimulus_line8; + sc_signal_bool_vector4 stimulus_line9; + sc_signal_logic_vector4 stimulus_line10; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector8 result_line1; + sc_signal_bool_vector8 result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + sc_signal<bool> result_line7; + sc_signal_bool_vector4 result_line8; + sc_signal_logic_vector4 result_line9; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.cpp new file mode 100644 index 000000000..384030f0d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + bool tmp8; + sc_unsigned tmp9(4); + sc_unsigned tmp10(4); + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + tmp8 = "0"; + tmp9 = "0b0001"; + tmp10 = "0b0010"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + out_value8.write(tmp8); + out_value9.write(tmp9); + out_value10.write(tmp10); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << " " << tmp8 << " " << tmp9 << " " << tmp10 <<endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + tmp8 = !tmp8; + tmp9 = tmp9 + 1; + tmp10 = tmp10 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.h new file mode 100644 index 000000000..5fa7f4b64 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/stimulus.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_value8 ; + sc_signal_bool_vector4& out_value9; // Output port + sc_signal_logic_vector4& out_value10; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALUE8, + sc_signal_bool_vector4& OUT_VALUE9, + sc_signal_logic_vector4& OUT_VALUE10, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_value10 (OUT_VALUE10), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/common.h new file mode 100644 index 000000000..8976a26a2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; +typedef sc_signal<sc_lv<4> > sc_signal_logic_vector4; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.cpp new file mode 100644 index 000000000..ec1d89946 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.cpp @@ -0,0 +1,143 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + bool tmp7; + bool tmp7r; + sc_bv<4> tmp8; + sc_bv<4> tmp8r; + sc_lv<4> tmp9; + sc_lv<4> tmp9r; + +// define 1 dimensional array + int tmpa[2]; + char tmpb[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmpa[0] = 12; + tmpa[1] = 127; + tmpb[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmpb[0] = in_value7.read(); + tmp7 = in_value8.read(); + tmp8 = in_value9.read(); + tmp9 = in_value10.read(); + + out_ack.write(true); + + //execute mixed data type not operations + + // signed(8) <- ~ unsigned(8) + tmp1r = ~ tmp2; + // unsigned(8) <- ~ long + tmp2r = ~ tmp3; + // long <- ~ char + tmp3r = ~ tmp6; + // int <- ~ short + tmp4r = ~ tmp5; + // short <- ~ int + tmp5r = ~ tmp4; + // char <- ~ char_array[0] + // tmp6r = ~ tmp8[0]; + tmp6r = ~ tmp8[0].to_bool(); + // bool <- ! bool; + tmp7r = !tmp7; + // sc_bool_vector(4) <- ~ sc_logic_vector(4) + tmp8r = ~ tmp9; + // sc_logic_vector(4) <- ~ sc_bool_vector(4) + tmp9r = ~ tmp9; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_value7.write(tmp7r); + out_value8.write(tmp8r); + out_value9.write(tmp9r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.h new file mode 100644 index 000000000..9aba0ab1f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/datatypes.h @@ -0,0 +1,146 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector8& in_value1; // Input port + const sc_signal_bool_vector8& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_value8 ; + const sc_signal_bool_vector4& in_value9 ; // Input port + const sc_signal_logic_vector4& in_value10; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_value7; // Output port + sc_signal_bool_vector4& out_value8; // Output port + sc_signal_logic_vector4& out_value9; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALUE8, + const sc_signal_bool_vector4& IN_VALUE9, + const sc_signal_logic_vector4& IN_VALUE10, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALUE7, + sc_signal_bool_vector4& OUT_VALUE8, + sc_signal_logic_vector4& OUT_VALUE9, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_value10 (IN_VALUE10), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.cpp new file mode 100644 index 000000000..75d3350de --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<40){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << (int)in_value6.read() << " " << in_value7.read() << " " << in_value8.read() << " " << in_value9.read() <<endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.h new file mode 100644 index 000000000..dc73106ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/display.h @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector8& in_value1; // Output port + const sc_signal_bool_vector8& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_value7; // Output port + const sc_signal_bool_vector4& in_value8; // Output port + const sc_signal_logic_vector4& in_value9; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALUE7, + const sc_signal_bool_vector4& IN_VALUE8, + const sc_signal_logic_vector4& IN_VALUE9, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log new file mode 100644 index 000000000..4b372afbf --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 11111101 10110001 -37 -20001 -7617 -2 0 1101 1101 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 11111100 10101100 -37 -20007 -7620 -1 1 1100 1100 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 11111011 10100111 -37 -20013 -7623 -2 0 1011 1011 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 11111010 10100010 -37 -20019 -7626 -1 1 1010 1010 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 11111001 10011101 -37 -20025 -7629 -2 0 1001 1001 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 11111000 10011000 -37 -20031 -7632 -1 1 1000 1000 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 11110111 10010011 -37 -20037 -7635 -2 0 0111 0111 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 11110110 10001110 -37 -20043 -7638 -1 1 0110 0110 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 11110101 10001001 -37 -20049 -7641 -2 0 0101 0101 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 11110100 10000100 -37 -20055 -7644 -1 1 0100 0100 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 11110011 01111111 -37 -20061 -7647 -2 0 0011 0011 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 11110010 01111010 -37 -20067 -7650 -1 1 0010 0010 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 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0 8 9 +Display: 11010110 11101110 -37 -20235 -7734 -1 1 0110 0110 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log.linuxaarch64 b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log.linuxaarch64 new file mode 100644 index 000000000..d0ebd06c2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/golden/datatypes.log.linuxaarch64 @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 11111101 10110001 -37 -20001 -7617 254 0 1101 1101 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 11111100 10101100 -37 -20007 -7620 255 1 1100 1100 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 11111011 10100111 -37 -20013 -7623 254 0 1011 1011 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 11111010 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01110101 -37 -20073 -7653 254 0 0001 0001 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 11110000 01110000 -37 -20079 -7656 255 1 0000 0000 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 11101111 01101011 -37 -20085 -7659 254 0 1111 1111 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 11101110 01100110 -37 -20091 -7662 255 1 1110 1110 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 11101101 01100001 -37 -20097 -7665 254 0 1101 1101 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 11101100 01011100 -37 -20103 -7668 255 1 1100 1100 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 11101011 01010111 -37 -20109 -7671 254 0 1011 1011 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 11101010 01010010 -37 -20115 -7674 255 1 1010 1010 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 11101001 01001101 -37 -20121 -7677 254 0 1001 1001 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 11101000 01001000 -37 -20127 -7680 255 1 1000 1000 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 11100111 01000011 -37 -20133 -7683 254 0 0111 0111 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 11100110 00111110 -37 -20139 -7686 255 1 0110 0110 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 11100101 00111001 -37 -20145 -7689 254 0 0101 0101 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 11100100 00110100 -37 -20151 -7692 255 1 0100 0100 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 11100011 00101111 -37 -20157 -7695 254 0 0011 0011 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 11100010 00101010 -37 -20163 -7698 255 1 0010 0010 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 11100001 00100101 -37 -20169 -7701 254 0 0001 0001 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 11100000 00100000 -37 -20175 -7704 255 1 0000 0000 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 11011111 00011011 -37 -20181 -7707 254 0 1111 1111 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 11011110 00010110 -37 -20187 -7710 255 1 1110 1110 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 11011101 00010001 -37 -20193 -7713 254 0 1101 1101 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 11011100 00001100 -37 -20199 -7716 255 1 1100 1100 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 11011011 00000111 -37 -20205 -7719 254 0 1011 1011 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 11011010 00000010 -37 -20211 -7722 255 1 1010 1010 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 11011001 11111101 -37 -20217 -7725 254 0 1001 1001 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 11011000 11111000 -37 -20223 -7728 255 1 1000 1000 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 11010111 11110011 -37 -20229 -7731 254 0 0111 0111 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 11010110 11101110 -37 -20235 -7734 255 1 0110 0110 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/main.cpp new file mode 100644 index 000000000..ae4db66ee --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/main.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector8 stimulus_line1; + sc_signal_bool_vector8 stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> stimulus_line8; + sc_signal_bool_vector4 stimulus_line9; + sc_signal_logic_vector4 stimulus_line10; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector8 result_line1; + sc_signal_bool_vector8 result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + sc_signal<bool> result_line7; + sc_signal_bool_vector4 result_line8; + sc_signal_logic_vector4 result_line9; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.cpp new file mode 100644 index 000000000..384030f0d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + bool tmp8; + sc_unsigned tmp9(4); + sc_unsigned tmp10(4); + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + tmp8 = "0"; + tmp9 = "0b0001"; + tmp10 = "0b0010"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + out_value8.write(tmp8); + out_value9.write(tmp9); + out_value10.write(tmp10); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << " " << tmp8 << " " << tmp9 << " " << tmp10 <<endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + tmp8 = !tmp8; + tmp9 = tmp9 + 1; + tmp10 = tmp10 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.h new file mode 100644 index 000000000..8c700d060 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/stimulus.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_value8 ; + sc_signal_bool_vector4& out_value9 ; // Output port + sc_signal_logic_vector4& out_value10; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALUE8, + sc_signal_bool_vector4& OUT_VALUE9, + sc_signal_logic_vector4& OUT_VALUE10, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_value10 (OUT_VALUE10), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.h new file mode 100644 index 000000000..59a19b5f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/golden/not_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/golden/not_1.log new file mode 100644 index 000000000..299c670c9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/golden/not_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : -2 4294967294 11111110 11111110 11111110 at 17 ns +Display : -4 4294967292 11111100 11111100 11111100 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : -13 4294967283 11110011 11110011 11110011 at 28 ns +Display : -4 4294967292 11111100 11111100 11111100 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : -24 4294967272 11101000 11101000 11101000 at 39 ns +Display : -4 4294967292 11111100 11111100 11111100 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : -35 4294967261 11011101 11011101 11011101 at 50 ns +Display : -4 4294967292 11111100 11111100 11111100 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : -46 4294967250 11010010 11010010 11010010 at 61 ns +Display : -4 4294967292 11111100 11111100 11111100 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : -57 4294967239 11000111 11000111 11000111 at 72 ns +Display : -4 4294967292 11111100 11111100 11111100 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : -68 4294967228 10111100 10111100 10111100 at 83 ns +Display : -4 4294967292 11111100 11111100 11111100 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : -79 4294967217 10110001 10110001 10110001 at 94 ns +Display : -4 4294967292 11111100 11111100 11111100 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : -90 4294967206 10100110 10100110 10100110 at 105 ns +Display : -4 4294967292 11111100 11111100 11111100 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : -101 4294967195 10011011 10011011 10011011 at 116 ns +Display : -4 4294967292 11111100 11111100 11111100 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : -112 4294967184 10010000 10010000 10010000 at 127 ns +Display : -4 4294967292 11111100 11111100 11111100 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : -123 4294967173 10000101 10000101 10000101 at 138 ns +Display : -4 4294967292 11111100 11111100 11111100 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/main.cpp new file mode 100644 index 000000000..1a4d8f4e7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/main.cpp @@ -0,0 +1,100 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "not_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + not_1 not1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.cpp new file mode 100644 index 000000000..a96e400e5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + not_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "not_1.h" + +void not_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = ~ tmp1 ; + tmp2 = ~ tmp2 ; + tmp3 = ~ tmp3 ; + tmp4 = ~ tmp4 ; + tmp5 = ~ tmp5 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 = ~(0x03); + tmp2 = ~(0x03); + tmp3 = ~(tmp3_tmp); + tmp4 = ~(0x03); + tmp5 = ~(0x03); + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.f new file mode 100644 index 000000000..07b7b0d72 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.f @@ -0,0 +1,4 @@ +not_1/display.cpp +not_1/main.cpp +not_1/not_1.cpp +not_1/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.h new file mode 100644 index 000000000..7366fd3c8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/not_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + not_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( not_1 ) +{ + SC_HAS_PROCESS( not_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + not_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.cpp new file mode 100644 index 000000000..b7e17113f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/not_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.cpp new file mode 100644 index 000000000..eeacba45c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.cpp @@ -0,0 +1,123 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + int tmp7[2]; + char tmp8[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmp7[0] = 12; + tmp7[1] = 0; + tmp8[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmp8[0] = in_value7.read(); + + out_ack.write(true); + + //execute mixed data type or operations + + // signed(8) <- signed(8) & unsigned(8) + tmp1r = tmp1 | tmp2; + // unsigned(8) <- char & long + tmp2r = tmp6 | tmp3; + // long <- int & char + tmp3r = tmp4 | tmp6; + // int <- int & short + tmp4r = tmp4 | tmp5; + // short <- short & const + tmp5r = tmp5 | 5; + // char <- char_array[0] & int_array[1] + tmp6r = tmp8[0] | tmp7[1]; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.f new file mode 100644 index 000000000..c767ce1c2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/datatypes.cpp +datatypes/display.cpp +datatypes/main.cpp +datatypes/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.h new file mode 100644 index 000000000..3332046ad --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/datatypes.h @@ -0,0 +1,127 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.cpp new file mode 100644 index 000000000..258461c24 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<100){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.h new file mode 100644 index 000000000..3c2ece81a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/display.h @@ -0,0 +1,88 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/golden/datatypes.log new file mode 100644 index 000000000..d6f00f117 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/golden/datatypes.log @@ -0,0 +1,204 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A +Display: 01010111 01101110 -123420 -106528 20005 A +Stimuli: 87 3 12345683 -123453 20006 $ B +Display: 01010111 01110111 -123417 -106521 20007 B +Stimuli: 89 4 12345688 -123450 20012 $ C +Display: 01011101 01111100 -123418 -106514 20013 C +Stimuli: 91 5 12345693 -123447 20018 $ D +Display: 01011111 01111101 -123411 -106501 20023 D +Stimuli: 93 6 12345698 -123444 20024 $ E +Display: 01011111 01100110 -123412 -106500 20029 E +Stimuli: 95 7 12345703 -123441 20030 $ F +Display: 01011111 01100111 -123409 -106497 20031 F +Stimuli: 97 8 12345708 -123438 20036 $ G +Display: 01101001 01101100 -123402 -106538 20037 G +Stimuli: 99 9 12345713 -123435 20042 $ H +Display: 01101011 01110101 -123403 -106529 20047 H +Stimuli: 101 10 12345718 -123432 20048 $ I +Display: 01101111 01110110 -123396 -106536 20053 I +Stimuli: 103 11 12345723 -123429 20054 $ J +Display: 01101111 01111111 -123393 -106529 20055 J +Stimuli: 105 12 12345728 -123426 20060 $ K +Display: 01101101 10100100 -123394 -106530 20061 K +Stimuli: 107 13 12345733 -123423 20066 $ L +Display: 01101111 10100101 -123419 -106525 20071 L +Stimuli: 109 14 12345738 -123420 20072 $ M +Display: 01101111 10101110 -123420 -106516 20077 M +Stimuli: 111 15 12345743 -123417 20078 $ N +Display: 01101111 10101111 -123417 -106513 20079 N +Stimuli: 113 16 12345748 -123414 20084 $ O +Display: 01110001 10110100 -123410 -106498 20085 O +Stimuli: 115 17 12345753 -123411 20090 $ P +Display: 01110011 10111101 -123411 -106497 20095 P +Stimuli: 117 18 12345758 -123408 20096 $ Q +Display: 01110111 10111110 -123404 -106512 20101 Q +Stimuli: 119 19 12345763 -123405 20102 $ R +Display: 01110111 10100111 -123401 -106505 20103 R +Stimuli: 121 20 12345768 -123402 20108 $ S +Display: 01111101 10101100 -123402 -106498 20109 S +Stimuli: 123 21 12345773 -123399 20114 $ T +Display: 01111111 10101101 -123395 -106501 20119 T +Stimuli: 125 22 12345778 -123396 20120 $ U +Display: 01111111 10110110 -123396 -106500 20125 U +Stimuli: 127 23 12345783 -123393 20126 $ V +Display: 01111111 10110111 -123393 -106497 20127 V +Stimuli: -127 24 12345788 -123390 20132 $ W +Display: 10011001 10111100 -123354 -106842 20133 W +Stimuli: -125 25 12345793 -123387 20138 $ X +Display: 10011011 11100101 -123355 -106833 20143 X +Stimuli: -123 26 12345798 -123384 20144 $ Y +Display: 10011111 11100110 -123348 -106824 20149 Y +Stimuli: -121 27 12345803 -123381 20150 $ Z +Display: 10011111 11101111 -123345 -106817 20151 Z +Stimuli: -119 28 12345808 -123378 20156 $ [ +Display: 10011101 11110100 -123346 -106818 20157 [ +Stimuli: -117 29 12345813 -123375 20162 $ \ +Display: 10011111 11110101 -123339 -106797 20167 \ +Stimuli: -115 30 12345818 -123372 20168 $ ] +Display: 10011111 11111110 -123340 -106788 20173 ] +Stimuli: -113 31 12345823 -123369 20174 $ ^ +Display: 10011111 11111111 -123337 -106785 20175 ^ +Stimuli: -111 32 12345828 -123366 20180 $ _ +Display: 10110001 11100100 -123330 -106786 20181 _ +Stimuli: -109 33 12345833 -123363 20186 $ ` +Display: 10110011 11101101 -123331 -106785 20191 ` +Stimuli: -107 34 12345838 -123360 20192 $ a +Display: 10110111 11101110 -123356 -106784 20197 a +Stimuli: -105 35 12345843 -123357 20198 $ b +Display: 10110111 11110111 -123353 -106777 20199 b +Stimuli: -103 36 12345848 -123354 20204 $ c +Display: 10111101 11111100 -123354 -106770 20205 c +Stimuli: -101 37 12345853 -123351 20210 $ d +Display: 10111111 11111101 -123347 -106757 20215 d +Stimuli: -99 38 12345858 -123348 20216 $ e +Display: 10111111 00100110 -123348 -106756 20221 e +Stimuli: -97 39 12345863 -123345 20222 $ f +Display: 10111111 00100111 -123345 -106753 20223 f +Stimuli: -95 40 12345868 -123342 20228 $ g +Display: 10101001 00101100 -123338 -106698 20229 g +Stimuli: -93 41 12345873 -123339 20234 $ h +Display: 10101011 00110101 -123339 -106689 20239 h +Stimuli: -91 42 12345878 -123336 20240 $ i +Display: 10101111 00110110 -123332 -106696 20245 i +Stimuli: -89 43 12345883 -123333 20246 $ j +Display: 10101111 00111111 -123329 -106689 20247 j +Stimuli: -87 44 12345888 -123330 20252 $ k +Display: 10101101 00100100 -123330 -106690 20253 k +Stimuli: -85 45 12345893 -123327 20258 $ l +Display: 10101111 00100101 -123291 -106653 20263 l +Stimuli: -83 46 12345898 -123324 20264 $ m +Display: 10101111 00101110 -123292 -106644 20269 m +Stimuli: -81 47 12345903 -123321 20270 $ n +Display: 10101111 00101111 -123289 -106641 20271 n +Stimuli: -79 48 12345908 -123318 20276 $ o +Display: 10110001 00110100 -123282 -106626 20277 o +Stimuli: -77 49 12345913 -123315 20282 $ p +Display: 10110011 00111101 -123283 -106625 20287 p +Stimuli: -75 50 12345918 -123312 20288 $ q +Display: 10110111 00111110 -123276 -106672 20293 q +Stimuli: -73 51 12345923 -123309 20294 $ r +Display: 10110111 01100111 -123273 -106665 20295 r +Stimuli: -71 52 12345928 -123306 20300 $ s +Display: 10111101 01101100 -123274 -106658 20301 s +Stimuli: -69 53 12345933 -123303 20306 $ t +Display: 10111111 01101101 -123267 -106661 20311 t +Stimuli: -67 54 12345938 -123300 20312 $ u +Display: 10111111 01110110 -123268 -106660 20317 u +Stimuli: -65 55 12345943 -123297 20318 $ v +Display: 10111111 01110111 -123265 -106657 20319 v +Stimuli: -63 56 12345948 -123294 20324 $ w +Display: 11111001 01111100 -123290 -106650 20325 w +Stimuli: -61 57 12345953 -123291 20330 $ x +Display: 11111011 01100101 -123291 -106641 20335 x +Stimuli: -59 58 12345958 -123288 20336 $ y +Display: 11111111 01100110 -123284 -106632 20341 y +Stimuli: -57 59 12345963 -123285 20342 $ z +Display: 11111111 01101111 -123281 -106625 20343 z +Stimuli: -55 60 12345968 -123282 20348 $ { +Display: 11111101 01110100 -123282 -106626 20349 { +Stimuli: -53 61 12345973 -123279 20354 $ | +Display: 11111111 01110101 -123275 -106509 20359 | +Stimuli: -51 62 12345978 -123276 20360 $ } +Display: 11111111 01111110 -123276 -106500 20365 } +Stimuli: -49 63 12345983 -123273 20366 $ ~ +Display: 11111111 01111111 -123273 -106497 20367 ~ +Stimuli: -47 64 12345988 -123270 20372 $ +Display: 11010001 10100100 -123266 -106498 20373 +Stimuli: -45 65 12345993 -123267 20378 $ € +Display: 11010011 10101101 -123267 -106497 20383 € +Stimuli: -43 66 12345998 -123264 20384 $ +Display: 11010111 10101110 -123228 -106592 20389 +Stimuli: -41 67 12346003 -123261 20390 $ ‚ +Display: 11010111 10110111 -123225 -106585 20391 ‚ +Stimuli: -39 68 12346008 -123258 20396 $ ƒ +Display: 11011101 10111100 -123226 -106578 20397 ƒ +Stimuli: -37 69 12346013 -123255 20402 $ „ +Display: 11011111 10111101 -123219 -106565 20407 „ +Stimuli: -35 70 12346018 -123252 20408 $ … +Display: 11011111 10100110 -123220 -106564 20413 … +Stimuli: -33 71 12346023 -123249 20414 $ † +Display: 11011111 10100111 -123217 -106561 20415 † +Stimuli: -31 72 12346028 -123246 20420 $ ‡ +Display: 11101001 10101100 -123210 -106538 20421 ‡ +Stimuli: -29 73 12346033 -123243 20426 $ ˆ +Display: 11101011 10110101 -123211 -106529 20431 ˆ +Stimuli: -27 74 12346038 -123240 20432 $ ‰ +Display: 11101111 10110110 -123204 -106536 20437 ‰ +Stimuli: -25 75 12346043 -123237 20438 $ Š +Display: 11101111 10111111 -123201 -106529 20439 Š +Stimuli: -23 76 12346048 -123234 20444 $ ‹ +Display: 11101101 11100100 -123202 -106530 20445 ‹ +Stimuli: -21 77 12346053 -123231 20450 $ Œ +Display: 11101111 11100101 -123227 -106525 20455 Œ +Stimuli: -19 78 12346058 -123228 20456 $ +Display: 11101111 11101110 -123228 -106516 20461 +Stimuli: -17 79 12346063 -123225 20462 $ Ž +Display: 11101111 11101111 -123225 -106513 20463 Ž +Stimuli: -15 80 12346068 -123222 20468 $ +Display: 11110001 11110100 -123218 -106498 20469 +Stimuli: -13 81 12346073 -123219 20474 $ +Display: 11110011 11111101 -123219 -106497 20479 +Stimuli: -11 82 12346078 -123216 20480 $ ‘ +Display: 11110111 11111110 -123212 -106832 20485 ‘ +Stimuli: -9 83 12346083 -123213 20486 $ ’ +Display: 11110111 11100111 -123209 -106825 20487 ’ +Stimuli: -7 84 12346088 -123210 20492 $ “ +Display: 11111101 11101100 -123210 -106818 20493 “ +Stimuli: -5 85 12346093 -123207 20498 $ ” +Display: 11111111 11101101 -123203 -106821 20503 ” +Stimuli: -3 86 12346098 -123204 20504 $ • +Display: 11111111 11110110 -123204 -106820 20509 • +Stimuli: -1 87 12346103 -123201 20510 $ – +Display: 11111111 11110111 -123201 -106817 20511 – +Stimuli: 1 88 12346108 -123198 20516 $ — +Display: 01011001 11111100 -123162 -106778 20517 — +Stimuli: 3 89 12346113 -123195 20522 $ ˜ +Display: 01011011 00100101 -123163 -106769 20527 ˜ +Stimuli: 5 90 12346118 -123192 20528 $ ™ +Display: 01011111 00100110 -123156 -106760 20533 ™ +Stimuli: 7 91 12346123 -123189 20534 $ š +Display: 01011111 00101111 -123153 -106753 20535 š +Stimuli: 9 92 12346128 -123186 20540 $ › +Display: 01011101 00110100 -123154 -106754 20541 › +Stimuli: 11 93 12346133 -123183 20546 $ œ +Display: 01011111 00110101 -123147 -106797 20551 œ +Stimuli: 13 94 12346138 -123180 20552 $ +Display: 01011111 00111110 -123148 -106788 20557 +Stimuli: 15 95 12346143 -123177 20558 $ ž +Display: 01011111 00111111 -123145 -106785 20559 ž +Stimuli: 17 96 12346148 -123174 20564 $ Ÿ +Display: 01110001 00100100 -123138 -106786 20565 Ÿ +Stimuli: 19 97 12346153 -123171 20570 $ +Display: 01110011 00101101 -123139 -106785 20575 +Stimuli: 21 98 12346158 -123168 20576 $ ¡ +Display: 01110111 00101110 -123164 -106784 20581 ¡ +Stimuli: 23 99 12346163 -123165 20582 $ ¢ +Display: 01110111 00110111 -123161 -106777 20583 ¢ +Stimuli: 25 100 12346168 -123162 20588 $ £ +Display: 01111101 00111100 -123162 -106770 20589 £ +Stimuli: 27 101 12346173 -123159 20594 $ ¤ +Display: 01111111 00111101 -123155 -106757 20599 ¤ +Stimuli: 29 102 12346178 -123156 20600 $ ¥ + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/main.cpp new file mode 100644 index 000000000..319d97eb5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/main.cpp @@ -0,0 +1,113 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Stan Liao, Synopsys, Inc., 1999-10-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + input_valid = 0; + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.cpp new file mode 100644 index 000000000..aff6ff983 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.h new file mode 100644 index 000000000..fbb96b57b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/stimulus.h @@ -0,0 +1,94 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h new file mode 100644 index 000000000..59a19b5f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log new file mode 100644 index 000000000..d5f651425 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/golden/or_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : 31 31 00001111 00011111 00011111 at 17 ns +Display : 31 31 00001111 00011111 00011111 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : 31 31 00001111 00011111 00011111 at 28 ns +Display : 31 31 00001111 00011111 00011111 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : 31 31 00011111 00011111 00011111 at 39 ns +Display : 31 31 00011111 00011111 00011111 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : 63 63 00101111 00111111 00111111 at 50 ns +Display : 63 63 00101111 00111111 00111111 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : 63 63 00101111 00111111 00111111 at 61 ns +Display : 63 63 00101111 00111111 00111111 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : 63 63 00111111 00111111 00111111 at 72 ns +Display : 63 63 00111111 00111111 00111111 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : 95 95 01001111 01011111 01011111 at 83 ns +Display : 95 95 01001111 01011111 01011111 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : 95 95 01001111 01011111 01011111 at 94 ns +Display : 95 95 01001111 01011111 01011111 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : 95 95 01011111 01011111 01011111 at 105 ns +Display : 95 95 01011111 01011111 01011111 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : 127 127 01101111 01111111 01111111 at 116 ns +Display : 127 127 01101111 01111111 01111111 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : 127 127 01101111 01111111 01111111 at 127 ns +Display : 127 127 01101111 01111111 01111111 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : 127 127 01111111 01111111 01111111 at 138 ns +Display : 127 127 01111111 01111111 01111111 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp new file mode 100644 index 000000000..fb587275d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "or_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + or_1 or1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp new file mode 100644 index 000000000..e65fdbaf1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + or_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "or_1.h" + +void or_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = tmp1 | 0x0f | 0x12; + tmp2 = tmp2 | 0x0f | 0x13 ; + tmp3 = tmp3 | tmp3_tmp; + tmp4 = tmp4 | 0x0f | 0x14 ; + tmp5 = tmp5 | 0x0f | 0x15 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 |= 0x03; + tmp2 |= 0x03; + tmp3 |= tmp3_tmp; + tmp4 |= 0x03; + tmp5 |= 0x03; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f new file mode 100644 index 000000000..8b7bff4d2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.f @@ -0,0 +1,4 @@ +or_1/display.cpp +or_1/main.cpp +or_1/or_1.cpp +or_1/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h new file mode 100644 index 000000000..99285a543 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/or_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + or_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( or_1 ) +{ + SC_HAS_PROCESS( or_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + or_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp new file mode 100644 index 000000000..b7e17113f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/or_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.cpp new file mode 100644 index 000000000..7cb14c66c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.cpp @@ -0,0 +1,100 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "bitwidth.h" + +void bitwidth::entry(){ + + sc_bigint<4> tmp1; + sc_biguint<4> tmp2; + sc_bigint<6> tmp3; + sc_biguint<6> tmp4; + sc_bigint<8> tmp5; + sc_biguint<8> tmp6; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + //execute simple operations + // expected bitwidth 4 4 4 signed + tmp1 = tmp1 << tmp2; + // expected bitwidth 4 6 6 signed + tmp3 = tmp1 << tmp2; + // expected bitwidth 4 4 6 signed + tmp6 = tmp2 << tmp6; + // expected bitwidth 8 8 6 signed + tmp4 = tmp5 << tmp6; + // expected bitwidth 6 8 4 unsigned + tmp2 = tmp4 << tmp6; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.f new file mode 100644 index 000000000..53a59162e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.f @@ -0,0 +1,4 @@ +bitwidth/stimulus.cpp +bitwidth/display.cpp +bitwidth/bitwidth.cpp +bitwidth/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.h new file mode 100644 index 000000000..e088b3a4a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/bitwidth.h @@ -0,0 +1,121 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bitwidth.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( bitwidth ) +{ + SC_HAS_PROCESS( bitwidth ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector4& in_value1; // Input port + const sc_signal_bool_vector4& in_value2; // Input port + const sc_signal_bool_vector6& in_value3; // Input port + const sc_signal_bool_vector6& in_value4; // Input port + const sc_signal_bool_vector8& in_value5; // Input port + const sc_signal_bool_vector8& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal_bool_vector4& out_value1; // Output port + sc_signal_bool_vector4& out_value2; // Output port + sc_signal_bool_vector6& out_value3; // Output port + sc_signal_bool_vector6& out_value4; // Output port + sc_signal_bool_vector8& out_value5; // Output port + sc_signal_bool_vector8& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + bitwidth ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector4& IN_VALUE1, + const sc_signal_bool_vector4& IN_VALUE2, + const sc_signal_bool_vector6& IN_VALUE3, + const sc_signal_bool_vector6& IN_VALUE4, + const sc_signal_bool_vector8& IN_VALUE5, + const sc_signal_bool_vector8& IN_VALUE6, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector4& OUT_VALUE1, + sc_signal_bool_vector4& OUT_VALUE2, + sc_signal_bool_vector6& OUT_VALUE3, + sc_signal_bool_vector6& OUT_VALUE4, + sc_signal_bool_vector8& OUT_VALUE5, + sc_signal_bool_vector8& OUT_VALUE6, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/common.h new file mode 100644 index 000000000..2a49981d9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<6> > sc_signal_bool_vector6; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.cpp new file mode 100644 index 000000000..17eba10b1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.cpp @@ -0,0 +1,63 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << in_data6.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 12) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.h new file mode 100644 index 000000000..922ed13a9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/display.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector4& in_data1; // Input port + const sc_signal_bool_vector4& in_data2; // Input port + const sc_signal_bool_vector6& in_data3; // Input port + const sc_signal_bool_vector6& in_data4; // Input port + const sc_signal_bool_vector8& in_data5; // Input port + const sc_signal_bool_vector8& in_data6; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector4& IN_DATA1, + const sc_signal_bool_vector4& IN_DATA2, + const sc_signal_bool_vector6& IN_DATA3, + const sc_signal_bool_vector6& IN_DATA4, + const sc_signal_bool_vector8& IN_DATA5, + const sc_signal_bool_vector8& IN_DATA6, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_data6(IN_DATA6), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/golden/bitwidth.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/golden/bitwidth.log new file mode 100644 index 000000000..ad7d0b4fd --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/golden/bitwidth.log @@ -0,0 +1,27 @@ +SystemC Simulation +Stimuli : 1 1 1 1 1 1 at 23 ns +Display : 0010 0000 000100 000100 00000001 00000010 at 27 ns +Stimuli : 3 3 3 3 3 3 at 44 ns +Display : 1000 0000 000000 000000 00000011 00011000 at 48 ns +Stimuli : 5 5 5 5 5 5 at 65 ns +Display : 0000 0000 000000 000000 00000101 10100000 at 69 ns +Stimuli : 7 7 7 7 7 7 at 86 ns +Display : 0000 0000 000000 000000 00000111 10000000 at 90 ns +Stimuli : -7 9 9 9 9 9 at 107 ns +Display : 0000 1001 000000 001001 00001001 00000000 at 111 ns +Stimuli : -5 11 11 11 11 11 at 128 ns +Display : 0000 1011 000000 001011 00001011 00000000 at 132 ns +Stimuli : -3 13 13 13 13 13 at 149 ns +Display : 0000 1101 000000 001101 00001101 00000000 at 153 ns +Stimuli : -1 15 15 15 15 15 at 170 ns +Display : 0000 1111 000000 001111 00001111 00000000 at 174 ns +Stimuli : 1 1 17 17 17 17 at 191 ns +Display : 0010 0001 000100 010001 00010001 00000000 at 195 ns +Stimuli : 3 3 19 19 19 19 at 212 ns +Display : 1000 0011 000000 010011 00010011 00000000 at 216 ns +Stimuli : 5 5 21 21 21 21 at 233 ns +Display : 0000 0101 000000 010101 00010101 00000000 at 237 ns +Stimuli : 7 7 23 23 23 23 at 254 ns +Display : 0000 0111 000000 010111 00010111 00000000 at 258 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/main.cpp new file mode 100644 index 000000000..8a7ff91be --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/main.cpp @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "bitwidth.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector4 stimulus_line1; + sc_signal_bool_vector4 stimulus_line2; + sc_signal_bool_vector6 stimulus_line3; + sc_signal_bool_vector6 stimulus_line4; + sc_signal_bool_vector8 stimulus_line5; + sc_signal_bool_vector8 stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal_bool_vector4 result_line1; + sc_signal_bool_vector4 result_line2; + sc_signal_bool_vector6 result_line3; + sc_signal_bool_vector6 result_line4; + sc_signal_bool_vector8 result_line5; + sc_signal_bool_vector8 result_line6; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid); + + bitwidth bitwidth1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.cpp new file mode 100644 index 000000000..3d7567c14 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + sc_signed send_value1(4); + sc_unsigned send_value2(4); + sc_signed send_value3(6); + sc_unsigned send_value4(6); + sc_signed send_value5(8); + sc_unsigned send_value6(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value1 = 1; + send_value2 = 1; + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + send_value6 = 1; + out_stimulus1.write(1); + out_stimulus2.write(1); + out_stimulus3.write(1); + out_stimulus4.write(1); + out_stimulus5.write(1); + out_stimulus6.write(1); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(20); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_stimulus6.write( send_value6 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " + << send_value6 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+2; + send_value2 = send_value2+2; + send_value3 = send_value3+2; + send_value4 = send_value4+2; + send_value5 = send_value5+2; + send_value6 = send_value6+2; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.h new file mode 100644 index 000000000..fa0b64302 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/bitwidth/stimulus.h @@ -0,0 +1,84 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector4& out_stimulus1; + sc_signal_bool_vector4& out_stimulus2; + sc_signal_bool_vector6& out_stimulus3; + sc_signal_bool_vector6& out_stimulus4; + sc_signal_bool_vector8& out_stimulus5; + sc_signal_bool_vector8& out_stimulus6; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector4& OUT_STIMULUS1, + sc_signal_bool_vector4& OUT_STIMULUS2, + sc_signal_bool_vector6& OUT_STIMULUS3, + sc_signal_bool_vector6& OUT_STIMULUS4, + sc_signal_bool_vector8& OUT_STIMULUS5, + sc_signal_bool_vector8& OUT_STIMULUS6, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_stimulus6(OUT_STIMULUS6), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.cpp new file mode 100644 index 000000000..67ed1a1ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.cpp @@ -0,0 +1,150 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" +#define true 1 +#define false 0 + +void datatypes::entry() + +{ + + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + unsigned int tmp7[2]; + char tmp8[2]; + +// define sc_bool_vector + sc_bv<4> tmp10; + tmp10[3] = 0; tmp10[2] = 1; tmp10[1] = 0; tmp10[0] = 1; + +// define 2 dimentional array + sc_bv<1> tmp11[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// + +// initialization of sc_array + + tmp7[0] = 3; + tmp7[1] = 12; + tmp8[0] = 'S'; + tmp8[1] = 'C'; + tmp11[0][0] = "1"; + tmp11[1][0] = "0"; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + out_ack.write(true); + + //execute mixed data type shift left operations + tmp1r = tmp1 << (tmp7[0] % 8); + tmp2r = tmp2 << 2; + tmp3r = tmp3 << 1; + tmp4r = tmp4 << (tmp7[1] % 16); + tmp5r = tmp3 << ((unsigned int)(tmp1.to_int()) % 32); + tmp6r = tmp6 << 1; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + //execute mixed data type shift left operations + tmp1r = tmp1 << (tmp7[0] % 8); + tmp2r = tmp2 << (unsigned int)(tmp4 % 8); + tmp3r = tmp3 << (short)(tmp5 % 32); + tmp4r = tmp4 << 2; + tmp5r = tmp3 << ((unsigned int)(tmp5) % 16); + tmp6r = tmp6 << (tmp2.to_uint() % 32); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.h new file mode 100644 index 000000000..6def13c41 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/datatypes.h @@ -0,0 +1,126 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.cpp new file mode 100644 index 000000000..15e132440 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.cpp @@ -0,0 +1,50 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + while(true){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << " " << in_value5.read() << " " << (int)in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.h new file mode 100644 index 000000000..5e938dbf5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/display.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/golden/datatypes.log new file mode 100644 index 000000000..217bb37d8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/golden/datatypes.log @@ -0,0 +1,203 @@ +SystemC Simulation +Stimuli: -37 1 1 -1 20000 +Display: 11011000 00000100 2 -4096 0 -92 +Stimuli: -36 2 2 0 20001 +Display: 11100000 00001000 4 0 0 -90 +Stimuli: -35 3 3 1 20002 +Display: 11101000 00001100 6 4096 0 -88 +Stimuli: -34 4 4 2 20003 +Display: 11110000 00010000 8 8192 0 -86 +Stimuli: -33 5 5 3 20004 +Display: 11111000 00010100 10 12288 0 -84 +Stimuli: -32 6 6 4 20005 +Display: 00000000 00011000 12 16384 6 -82 +Stimuli: -31 7 7 5 20006 +Display: 00001000 00011100 14 20480 14 -80 +Stimuli: -30 8 8 6 20007 +Display: 00010000 00100000 16 24576 32 -78 +Stimuli: -29 9 9 7 20008 +Display: 00011000 00100100 18 28672 72 -76 +Stimuli: -28 10 10 8 20009 +Display: 00100000 00101000 20 32768 160 -74 +Stimuli: -27 11 11 9 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+Stimuli: 55 93 93 91 20092 +Display: 10111000 01110100 186 372736 0 92 +Stimuli: 56 94 94 92 20093 +Display: 11000000 01111000 188 376832 0 94 +Stimuli: 57 95 95 93 20094 +Display: 11001000 01111100 190 380928 0 96 +Stimuli: 58 96 96 94 20095 +Display: 11010000 10000000 192 385024 0 98 +Stimuli: 59 97 97 95 20096 +Display: 11011000 10000100 194 389120 0 100 +Stimuli: 60 98 98 96 20097 +Display: 11100000 10001000 196 393216 0 102 +Stimuli: 61 99 99 97 20098 +Display: 11101000 10001100 198 397312 0 104 +Stimuli: 62 100 100 98 20099 +Display: 11110000 10010000 200 401408 0 106 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/golden/datatypes.log.linuxaarch64 b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/golden/datatypes.log.linuxaarch64 new file mode 100644 index 000000000..81d9eaa88 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/golden/datatypes.log.linuxaarch64 @@ -0,0 +1,203 @@ +SystemC Simulation +Stimuli: -37 1 1 -1 20000 +Display: 11011000 00000100 2 -4096 0 164 +Stimuli: -36 2 2 0 20001 +Display: 11100000 00001000 4 0 0 166 +Stimuli: -35 3 3 1 20002 +Display: 11101000 00001100 6 4096 0 168 +Stimuli: -34 4 4 2 20003 +Display: 11110000 00010000 8 8192 0 170 +Stimuli: -33 5 5 3 20004 +Display: 11111000 00010100 10 12288 0 172 +Stimuli: -32 6 6 4 20005 +Display: 00000000 00011000 12 16384 6 174 +Stimuli: -31 7 7 5 20006 +Display: 00001000 00011100 14 20480 14 176 +Stimuli: -30 8 8 6 20007 +Display: 00010000 00100000 16 24576 32 178 +Stimuli: -29 9 9 7 20008 +Display: 00011000 00100100 18 28672 72 180 +Stimuli: -28 10 10 8 20009 +Display: 00100000 00101000 20 32768 160 182 +Stimuli: -27 11 11 9 20010 +Display: 00101000 00101100 22 36864 352 184 +Stimuli: -26 12 12 10 20011 +Display: 00110000 00110000 24 40960 768 186 +Stimuli: -25 13 13 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266240 0 40 +Stimuli: 30 68 68 66 20067 +Display: 11110000 00010000 136 270336 0 42 +Stimuli: 31 69 69 67 20068 +Display: 11111000 00010100 138 274432 0 44 +Stimuli: 32 70 70 68 20069 +Display: 00000000 00011000 140 278528 70 46 +Stimuli: 33 71 71 69 20070 +Display: 00001000 00011100 142 282624 142 48 +Stimuli: 34 72 72 70 20071 +Display: 00010000 00100000 144 286720 288 50 +Stimuli: 35 73 73 71 20072 +Display: 00011000 00100100 146 290816 584 52 +Stimuli: 36 74 74 72 20073 +Display: 00100000 00101000 148 294912 1184 54 +Stimuli: 37 75 75 73 20074 +Display: 00101000 00101100 150 299008 2400 56 +Stimuli: 38 76 76 74 20075 +Display: 00110000 00110000 152 303104 4864 58 +Stimuli: 39 77 77 75 20076 +Display: 00111000 00110100 154 307200 9856 60 +Stimuli: 40 78 78 76 20077 +Display: 01000000 00111000 156 311296 19968 62 +Stimuli: 41 79 79 77 20078 +Display: 01001000 00111100 158 315392 -25088 64 +Stimuli: 42 80 80 78 20079 +Display: 01010000 01000000 160 319488 16384 66 +Stimuli: 43 81 81 79 20080 +Display: 01011000 01000100 162 323584 -30720 68 +Stimuli: 44 82 82 80 20081 +Display: 01100000 01001000 164 327680 8192 70 +Stimuli: 45 83 83 81 20082 +Display: 01101000 01001100 166 331776 24576 72 +Stimuli: 46 84 84 82 20083 +Display: 01110000 01010000 168 335872 0 74 +Stimuli: 47 85 85 83 20084 +Display: 01111000 01010100 170 339968 -32768 76 +Stimuli: 48 86 86 84 20085 +Display: 10000000 01011000 172 344064 0 78 +Stimuli: 49 87 87 85 20086 +Display: 10001000 01011100 174 348160 0 80 +Stimuli: 50 88 88 86 20087 +Display: 10010000 01100000 176 352256 0 82 +Stimuli: 51 89 89 87 20088 +Display: 10011000 01100100 178 356352 0 84 +Stimuli: 52 90 90 88 20089 +Display: 10100000 01101000 180 360448 0 86 +Stimuli: 53 91 91 89 20090 +Display: 10101000 01101100 182 364544 0 88 +Stimuli: 54 92 92 90 20091 +Display: 10110000 01110000 184 368640 0 90 +Stimuli: 55 93 93 91 20092 +Display: 10111000 01110100 186 372736 0 92 +Stimuli: 56 94 94 92 20093 +Display: 11000000 01111000 188 376832 0 94 +Stimuli: 57 95 95 93 20094 +Display: 11001000 01111100 190 380928 0 96 +Stimuli: 58 96 96 94 20095 +Display: 11010000 10000000 192 385024 0 98 +Stimuli: 59 97 97 95 20096 +Display: 11011000 10000100 194 389120 0 100 +Stimuli: 60 98 98 96 20097 +Display: 11100000 10001000 196 393216 0 102 +Stimuli: 61 99 99 97 20098 +Display: 11101000 10001100 198 397312 0 104 +Stimuli: 62 100 100 98 20099 +Display: 11110000 10010000 200 401408 0 106 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/main.cpp new file mode 100644 index 000000000..813f5f29d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/main.cpp @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.cpp new file mode 100644 index 000000000..1263da802 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + + int counter = 0; + + tmp1 = "0b11011011"; + tmp2 = "0b00000001"; + tmp3 = 1; + tmp4 = -1; + tmp5 = 20000; + tmp6 = 'R'; + + while(counter<100){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " << tmp5 << " " << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 1; + tmp5 = tmp5 + 1; + tmp6 = tmp6 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + counter++; + wait(); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.h new file mode 100644 index 000000000..6f7aeefc8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/stimulus.h @@ -0,0 +1,90 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.cpp new file mode 100644 index 000000000..79d2a0f86 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.cpp @@ -0,0 +1,50 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + while(true){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.h new file mode 100644 index 000000000..5e938dbf5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/display.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/golden/sharing.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/golden/sharing.log Binary files differnew file mode 100644 index 000000000..9666885d8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/golden/sharing.log diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/main.cpp new file mode 100644 index 000000000..ffb011ab2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/main.cpp @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "sharing.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack); + + sharing sharing1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.cpp new file mode 100644 index 000000000..392ac6ca5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.cpp @@ -0,0 +1,150 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "sharing.h" +#define true 1 +#define false 0 + +void sharing::entry() + +{ + + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + unsigned int tmp7[2]; + char tmp8[2]; + +// define sc_bool_vector + sc_bv<4> tmp10; + tmp10[3] = 0; tmp10[2] = 1; tmp10[1] = 0; tmp10[0] = 1; + +// define 2 dimentional array + sc_bv<1> tmp11[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// + +// initialization of sc_array + + tmp7[0] = 3; + tmp7[1] = 12; + tmp8[0] = 'S'; + tmp8[1] = 'C'; + tmp11[0][0] = "1"; + tmp11[1][0] = "0"; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + out_ack.write(true); + + //execute mixed data type shit left operations + tmp1r = tmp1 << (tmp7[0] % 8); + tmp2r = tmp2 << 2; + tmp3r = tmp3 << 1; + tmp4r = tmp4 << (tmp7[1] % 32); + tmp5r = tmp3 << ((unsigned int)tmp1.to_int() % 32); + tmp6r = tmp6 << 1; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + //execute mixed data type shift left operations + tmp1r = tmp1 << (tmp7[0] % 8); + tmp2r = tmp2 << (tmp4 % 8); + tmp3r = tmp3 << (tmp5 % 32); + tmp4r = tmp4 << 2; + tmp5r = tmp3 << ((unsigned int)(tmp5) % 32); + tmp6r = tmp6 << (tmp2.to_uint() % 8); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.f new file mode 100644 index 000000000..998e0f309 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.f @@ -0,0 +1,4 @@ +sharing/display.cpp +sharing/main.cpp +sharing/sharing.cpp +sharing/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.h new file mode 100644 index 000000000..5552db43a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/sharing.h @@ -0,0 +1,126 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( sharing ) +{ + SC_HAS_PROCESS( sharing ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + sharing( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.cpp new file mode 100644 index 000000000..1263da802 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + + int counter = 0; + + tmp1 = "0b11011011"; + tmp2 = "0b00000001"; + tmp3 = 1; + tmp4 = -1; + tmp5 = 20000; + tmp6 = 'R'; + + while(counter<100){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " << tmp5 << " " << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 1; + tmp5 = tmp5 + 1; + tmp6 = tmp6 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + counter++; + wait(); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.h new file mode 100644 index 000000000..6f7aeefc8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/stimulus.h @@ -0,0 +1,90 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.cpp new file mode 100644 index 000000000..79d2a0f86 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.cpp @@ -0,0 +1,50 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + while(true){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read() << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << endl; + do { wait(); } while ( in_valid == true); + } + +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.h new file mode 100644 index 000000000..5e938dbf5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/display.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_value1; // Output port + const sc_signal_bool_vector& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log new file mode 100644 index 000000000..acc069982 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log @@ -0,0 +1,203 @@ +SystemC Simulation +Stimuli: -37 1 1 -1 20000 +Display: 11111011 00000000 0 -1 0 ) +Stimuli: -36 2 2 0 20001 +Display: 11111011 00000000 1 0 0 ) +Stimuli: -35 3 3 1 20002 +Display: 11111011 00000000 1 0 0 * +Stimuli: -34 4 4 2 20003 +Display: 11111011 00000001 2 0 0 * +Stimuli: -33 5 5 3 20004 +Display: 11111011 00000001 2 0 0 + +Stimuli: -32 6 6 4 20005 +Display: 11111100 00000001 3 0 6 + +Stimuli: -31 7 7 5 20006 +Display: 11111100 00000001 3 0 3 , +Stimuli: -30 8 8 6 20007 +Display: 11111100 00000010 4 0 2 , +Stimuli: -29 9 9 7 20008 +Display: 11111100 00000010 4 0 1 - +Stimuli: -28 10 10 8 20009 +Display: 11111100 00000010 5 1 0 - +Stimuli: -27 11 11 9 20010 +Display: 11111100 00000010 5 1 0 . +Stimuli: -26 12 12 10 20011 +Display: 11111100 00000011 6 1 0 . +Stimuli: -25 13 13 11 20012 +Display: 11111100 00000011 6 1 0 / +Stimuli: -24 14 14 12 20013 +Display: 11111101 00000011 7 1 0 / +Stimuli: -23 15 15 13 20014 +Display: 11111101 00000011 7 1 0 0 +Stimuli: -22 16 16 14 20015 +Display: 11111101 00000100 8 1 0 0 +Stimuli: -21 17 17 15 20016 +Display: 11111101 00000100 8 1 0 1 +Stimuli: -20 18 18 16 20017 +Display: 11111101 00000100 9 2 0 1 +Stimuli: -19 19 19 17 20018 +Display: 11111101 00000100 9 2 0 2 +Stimuli: -18 20 20 18 20019 +Display: 11111101 00000101 10 2 0 2 +Stimuli: -17 21 21 19 20020 +Display: 11111101 00000101 10 2 0 3 +Stimuli: -16 22 22 20 20021 +Display: 11111110 00000101 11 2 0 3 +Stimuli: -15 23 23 21 20022 +Display: 11111110 00000101 11 2 0 4 +Stimuli: -14 24 24 22 20023 +Display: 11111110 00000110 12 2 0 4 +Stimuli: -13 25 25 23 20024 +Display: 11111110 00000110 12 2 0 5 +Stimuli: -12 26 26 24 20025 +Display: 11111110 00000110 13 3 0 5 +Stimuli: -11 27 27 25 20026 +Display: 11111110 00000110 13 3 0 6 +Stimuli: -10 28 28 26 20027 +Display: 11111110 00000111 14 3 0 6 +Stimuli: -9 29 29 27 20028 +Display: 11111110 00000111 14 3 0 7 +Stimuli: -8 30 30 28 20029 +Display: 11111111 00000111 15 3 0 7 +Stimuli: -7 31 31 29 20030 +Display: 11111111 00000111 15 3 0 8 +Stimuli: -6 32 32 30 20031 +Display: 11111111 00001000 16 3 0 8 +Stimuli: -5 33 33 31 20032 +Display: 11111111 00001000 16 3 0 9 +Stimuli: -4 34 34 32 20033 +Display: 11111111 00001000 17 4 0 9 +Stimuli: -3 35 35 33 20034 +Display: 11111111 00001000 17 4 0 : +Stimuli: -2 36 36 34 20035 +Display: 11111111 00001001 18 4 0 : +Stimuli: -1 37 37 35 20036 +Display: 11111111 00001001 18 4 0 ; +Stimuli: 0 38 38 36 20037 +Display: 00000000 00001001 19 4 38 ; +Stimuli: 1 39 39 37 20038 +Display: 00000000 00001001 19 4 19 < +Stimuli: 2 40 40 38 20039 +Display: 00000000 00001010 20 4 10 < +Stimuli: 3 41 41 39 20040 +Display: 00000000 00001010 20 4 5 = +Stimuli: 4 42 42 40 20041 +Display: 00000000 00001010 21 5 2 = +Stimuli: 5 43 43 41 20042 +Display: 00000000 00001010 21 5 1 > +Stimuli: 6 44 44 42 20043 +Display: 00000000 00001011 22 5 0 > +Stimuli: 7 45 45 43 20044 +Display: 00000000 00001011 22 5 0 ? +Stimuli: 8 46 46 44 20045 +Display: 00000001 00001011 23 5 0 ? +Stimuli: 9 47 47 45 20046 +Display: 00000001 00001011 23 5 0 À +Stimuli: 10 48 48 46 20047 +Display: 00000001 00001100 24 5 0 À +Stimuli: 11 49 49 47 20048 +Display: 00000001 00001100 24 5 0 Á +Stimuli: 12 50 50 48 20049 +Display: 00000001 00001100 25 6 0 Á +Stimuli: 13 51 51 49 20050 +Display: 00000001 00001100 25 6 0 Â +Stimuli: 14 52 52 50 20051 +Display: 00000001 00001101 26 6 0 Â +Stimuli: 15 53 53 51 20052 +Display: 00000001 00001101 26 6 0 Ã +Stimuli: 16 54 54 52 20053 +Display: 00000010 00001101 27 6 0 Ã +Stimuli: 17 55 55 53 20054 +Display: 00000010 00001101 27 6 0 Ä +Stimuli: 18 56 56 54 20055 +Display: 00000010 00001110 28 6 0 Ä +Stimuli: 19 57 57 55 20056 +Display: 00000010 00001110 28 6 0 Å +Stimuli: 20 58 58 56 20057 +Display: 00000010 00001110 29 7 0 Å +Stimuli: 21 59 59 57 20058 +Display: 00000010 00001110 29 7 0 Æ +Stimuli: 22 60 60 58 20059 +Display: 00000010 00001111 30 7 0 Æ +Stimuli: 23 61 61 59 20060 +Display: 00000010 00001111 30 7 0 Ç +Stimuli: 24 62 62 60 20061 +Display: 00000011 00001111 31 7 0 Ç +Stimuli: 25 63 63 61 20062 +Display: 00000011 00001111 31 7 0 È +Stimuli: 26 64 64 62 20063 +Display: 00000011 00010000 32 7 0 È +Stimuli: 27 65 65 63 20064 +Display: 00000011 00010000 32 7 0 É +Stimuli: 28 66 66 64 20065 +Display: 00000011 00010000 33 8 0 É +Stimuli: 29 67 67 65 20066 +Display: 00000011 00010000 33 8 0 Ê +Stimuli: 30 68 68 66 20067 +Display: 00000011 00010001 34 8 0 Ê +Stimuli: 31 69 69 67 20068 +Display: 00000011 00010001 34 8 0 Ë +Stimuli: 32 70 70 68 20069 +Display: 00000100 00010001 35 8 70 Ë +Stimuli: 33 71 71 69 20070 +Display: 00000100 00010001 35 8 35 Ì +Stimuli: 34 72 72 70 20071 +Display: 00000100 00010010 36 8 18 Ì +Stimuli: 35 73 73 71 20072 +Display: 00000100 00010010 36 8 9 Í +Stimuli: 36 74 74 72 20073 +Display: 00000100 00010010 37 9 4 Í +Stimuli: 37 75 75 73 20074 +Display: 00000100 00010010 37 9 2 Î +Stimuli: 38 76 76 74 20075 +Display: 00000100 00010011 38 9 1 Î +Stimuli: 39 77 77 75 20076 +Display: 00000100 00010011 38 9 0 Ï +Stimuli: 40 78 78 76 20077 +Display: 00000101 00010011 39 9 0 Ï +Stimuli: 41 79 79 77 20078 +Display: 00000101 00010011 39 9 0 Ð +Stimuli: 42 80 80 78 20079 +Display: 00000101 00010100 40 9 0 Ð +Stimuli: 43 81 81 79 20080 +Display: 00000101 00010100 40 9 0 Ñ +Stimuli: 44 82 82 80 20081 +Display: 00000101 00010100 41 10 0 Ñ +Stimuli: 45 83 83 81 20082 +Display: 00000101 00010100 41 10 0 Ò +Stimuli: 46 84 84 82 20083 +Display: 00000101 00010101 42 10 0 Ò +Stimuli: 47 85 85 83 20084 +Display: 00000101 00010101 42 10 0 Ó +Stimuli: 48 86 86 84 20085 +Display: 00000110 00010101 43 10 0 Ó +Stimuli: 49 87 87 85 20086 +Display: 00000110 00010101 43 10 0 Ô +Stimuli: 50 88 88 86 20087 +Display: 00000110 00010110 44 10 0 Ô +Stimuli: 51 89 89 87 20088 +Display: 00000110 00010110 44 10 0 Õ +Stimuli: 52 90 90 88 20089 +Display: 00000110 00010110 45 11 0 Õ +Stimuli: 53 91 91 89 20090 +Display: 00000110 00010110 45 11 0 Ö +Stimuli: 54 92 92 90 20091 +Display: 00000110 00010111 46 11 0 Ö +Stimuli: 55 93 93 91 20092 +Display: 00000110 00010111 46 11 0 × +Stimuli: 56 94 94 92 20093 +Display: 00000111 00010111 47 11 0 × +Stimuli: 57 95 95 93 20094 +Display: 00000111 00010111 47 11 0 Ø +Stimuli: 58 96 96 94 20095 +Display: 00000111 00011000 48 11 0 Ø +Stimuli: 59 97 97 95 20096 +Display: 00000111 00011000 48 11 0 Ù +Stimuli: 60 98 98 96 20097 +Display: 00000111 00011000 49 12 0 Ù +Stimuli: 61 99 99 97 20098 +Display: 00000111 00011000 49 12 0 Ú +Stimuli: 62 100 100 98 20099 +Display: 00000111 00011001 50 12 0 Ú + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log.linuxaarch64 b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log.linuxaarch64 new file mode 100644 index 000000000..7faa47515 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/golden/sharing.log.linuxaarch64 @@ -0,0 +1,203 @@ +SystemC Simulation +Stimuli: -37 1 1 -1 20000 +Display: 11111011 00000000 0 -1 0 ) +Stimuli: -36 2 2 0 20001 +Display: 11111011 00000000 1 0 0 ) +Stimuli: -35 3 3 1 20002 +Display: 11111011 00000000 1 0 0 * +Stimuli: -34 4 4 2 20003 +Display: 11111011 00000001 2 0 0 * +Stimuli: -33 5 5 3 20004 +Display: 11111011 00000001 2 0 0 + +Stimuli: -32 6 6 4 20005 +Display: 11111100 00000001 3 0 6 + +Stimuli: -31 7 7 5 20006 +Display: 11111100 00000001 3 0 3 , +Stimuli: -30 8 8 6 20007 +Display: 11111100 00000010 4 0 2 , +Stimuli: -29 9 9 7 20008 +Display: 11111100 00000010 4 0 1 - +Stimuli: -28 10 10 8 20009 +Display: 11111100 00000010 5 1 0 - +Stimuli: -27 11 11 9 20010 +Display: 11111100 00000010 5 1 0 . +Stimuli: -26 12 12 10 20011 +Display: 11111100 00000011 6 1 0 . +Stimuli: -25 13 13 11 20012 +Display: 11111100 00000011 6 1 0 / +Stimuli: -24 14 14 12 20013 +Display: 11111101 00000011 7 1 0 / +Stimuli: -23 15 15 13 20014 +Display: 11111101 00000011 7 1 0 0 +Stimuli: -22 16 16 14 20015 +Display: 11111101 00000100 8 1 0 0 +Stimuli: -21 17 17 15 20016 +Display: 11111101 00000100 8 1 0 1 +Stimuli: -20 18 18 16 20017 +Display: 11111101 00000100 9 2 0 1 +Stimuli: -19 19 19 17 20018 +Display: 11111101 00000100 9 2 0 2 +Stimuli: -18 20 20 18 20019 +Display: 11111101 00000101 10 2 0 2 +Stimuli: -17 21 21 19 20020 +Display: 11111101 00000101 10 2 0 3 +Stimuli: -16 22 22 20 20021 +Display: 11111110 00000101 11 2 0 3 +Stimuli: -15 23 23 21 20022 +Display: 11111110 00000101 11 2 0 4 +Stimuli: -14 24 24 22 20023 +Display: 11111110 00000110 12 2 0 4 +Stimuli: -13 25 25 23 20024 +Display: 11111110 00000110 12 2 0 5 +Stimuli: -12 26 26 24 20025 +Display: 11111110 00000110 13 3 0 5 +Stimuli: -11 27 27 25 20026 +Display: 11111110 00000110 13 3 0 6 +Stimuli: -10 28 28 26 20027 +Display: 11111110 00000111 14 3 0 6 +Stimuli: -9 29 29 27 20028 +Display: 11111110 00000111 14 3 0 7 +Stimuli: -8 30 30 28 20029 +Display: 11111111 00000111 15 3 0 7 +Stimuli: -7 31 31 29 20030 +Display: 11111111 00000111 15 3 0 8 +Stimuli: -6 32 32 30 20031 +Display: 11111111 00001000 16 3 0 8 +Stimuli: -5 33 33 31 20032 +Display: 11111111 00001000 16 3 0 9 +Stimuli: -4 34 34 32 20033 +Display: 11111111 00001000 17 4 0 9 +Stimuli: -3 35 35 33 20034 +Display: 11111111 00001000 17 4 0 : +Stimuli: -2 36 36 34 20035 +Display: 11111111 00001001 18 4 0 : +Stimuli: -1 37 37 35 20036 +Display: 11111111 00001001 18 4 0 ; +Stimuli: 0 38 38 36 20037 +Display: 00000000 00001001 19 4 38 ; +Stimuli: 1 39 39 37 20038 +Display: 00000000 00001001 19 4 19 < +Stimuli: 2 40 40 38 20039 +Display: 00000000 00001010 20 4 10 < +Stimuli: 3 41 41 39 20040 +Display: 00000000 00001010 20 4 5 = +Stimuli: 4 42 42 40 20041 +Display: 00000000 00001010 21 5 2 = +Stimuli: 5 43 43 41 20042 +Display: 00000000 00001010 21 5 1 > +Stimuli: 6 44 44 42 20043 +Display: 00000000 00001011 22 5 0 > +Stimuli: 7 45 45 43 20044 +Display: 00000000 00001011 22 5 0 ? +Stimuli: 8 46 46 44 20045 +Display: 00000001 00001011 23 5 0 ? +Stimuli: 9 47 47 45 20046 +Display: 00000001 00001011 23 5 0 @ +Stimuli: 10 48 48 46 20047 +Display: 00000001 00001100 24 5 0 @ +Stimuli: 11 49 49 47 20048 +Display: 00000001 00001100 24 5 0 A +Stimuli: 12 50 50 48 20049 +Display: 00000001 00001100 25 6 0 A +Stimuli: 13 51 51 49 20050 +Display: 00000001 00001100 25 6 0 B +Stimuli: 14 52 52 50 20051 +Display: 00000001 00001101 26 6 0 B +Stimuli: 15 53 53 51 20052 +Display: 00000001 00001101 26 6 0 C +Stimuli: 16 54 54 52 20053 +Display: 00000010 00001101 27 6 0 C +Stimuli: 17 55 55 53 20054 +Display: 00000010 00001101 27 6 0 D +Stimuli: 18 56 56 54 20055 +Display: 00000010 00001110 28 6 0 D +Stimuli: 19 57 57 55 20056 +Display: 00000010 00001110 28 6 0 E +Stimuli: 20 58 58 56 20057 +Display: 00000010 00001110 29 7 0 E +Stimuli: 21 59 59 57 20058 +Display: 00000010 00001110 29 7 0 F +Stimuli: 22 60 60 58 20059 +Display: 00000010 00001111 30 7 0 F +Stimuli: 23 61 61 59 20060 +Display: 00000010 00001111 30 7 0 G +Stimuli: 24 62 62 60 20061 +Display: 00000011 00001111 31 7 0 G +Stimuli: 25 63 63 61 20062 +Display: 00000011 00001111 31 7 0 H +Stimuli: 26 64 64 62 20063 +Display: 00000011 00010000 32 7 0 H +Stimuli: 27 65 65 63 20064 +Display: 00000011 00010000 32 7 0 I +Stimuli: 28 66 66 64 20065 +Display: 00000011 00010000 33 8 0 I +Stimuli: 29 67 67 65 20066 +Display: 00000011 00010000 33 8 0 J +Stimuli: 30 68 68 66 20067 +Display: 00000011 00010001 34 8 0 J +Stimuli: 31 69 69 67 20068 +Display: 00000011 00010001 34 8 0 K +Stimuli: 32 70 70 68 20069 +Display: 00000100 00010001 35 8 70 K +Stimuli: 33 71 71 69 20070 +Display: 00000100 00010001 35 8 35 L +Stimuli: 34 72 72 70 20071 +Display: 00000100 00010010 36 8 18 L +Stimuli: 35 73 73 71 20072 +Display: 00000100 00010010 36 8 9 M +Stimuli: 36 74 74 72 20073 +Display: 00000100 00010010 37 9 4 M +Stimuli: 37 75 75 73 20074 +Display: 00000100 00010010 37 9 2 N +Stimuli: 38 76 76 74 20075 +Display: 00000100 00010011 38 9 1 N +Stimuli: 39 77 77 75 20076 +Display: 00000100 00010011 38 9 0 O +Stimuli: 40 78 78 76 20077 +Display: 00000101 00010011 39 9 0 O +Stimuli: 41 79 79 77 20078 +Display: 00000101 00010011 39 9 0 P +Stimuli: 42 80 80 78 20079 +Display: 00000101 00010100 40 9 0 P +Stimuli: 43 81 81 79 20080 +Display: 00000101 00010100 40 9 0 Q +Stimuli: 44 82 82 80 20081 +Display: 00000101 00010100 41 10 0 Q +Stimuli: 45 83 83 81 20082 +Display: 00000101 00010100 41 10 0 R +Stimuli: 46 84 84 82 20083 +Display: 00000101 00010101 42 10 0 R +Stimuli: 47 85 85 83 20084 +Display: 00000101 00010101 42 10 0 S +Stimuli: 48 86 86 84 20085 +Display: 00000110 00010101 43 10 0 S +Stimuli: 49 87 87 85 20086 +Display: 00000110 00010101 43 10 0 T +Stimuli: 50 88 88 86 20087 +Display: 00000110 00010110 44 10 0 T +Stimuli: 51 89 89 87 20088 +Display: 00000110 00010110 44 10 0 U +Stimuli: 52 90 90 88 20089 +Display: 00000110 00010110 45 11 0 U +Stimuli: 53 91 91 89 20090 +Display: 00000110 00010110 45 11 0 V +Stimuli: 54 92 92 90 20091 +Display: 00000110 00010111 46 11 0 V +Stimuli: 55 93 93 91 20092 +Display: 00000110 00010111 46 11 0 W +Stimuli: 56 94 94 92 20093 +Display: 00000111 00010111 47 11 0 W +Stimuli: 57 95 95 93 20094 +Display: 00000111 00010111 47 11 0 X +Stimuli: 58 96 96 94 20095 +Display: 00000111 00011000 48 11 0 X +Stimuli: 59 97 97 95 20096 +Display: 00000111 00011000 48 11 0 Y +Stimuli: 60 98 98 96 20097 +Display: 00000111 00011000 49 12 0 Y +Stimuli: 61 99 99 97 20098 +Display: 00000111 00011000 49 12 0 Z +Stimuli: 62 100 100 98 20099 +Display: 00000111 00011001 50 12 0 Z + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/main.cpp new file mode 100644 index 000000000..ffb011ab2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/main.cpp @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "sharing.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stimulus_line1; + sc_signal_bool_vector stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector result_line1; + sc_signal_bool_vector result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + + output_valid = 0; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack); + + sharing sharing1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.cpp new file mode 100644 index 000000000..2b1dc2eb4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.cpp @@ -0,0 +1,150 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "sharing.h" +#define true 1 +#define false 0 + +void sharing::entry() + +{ + + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + +// define 1 dimensional array + unsigned int tmp7[2]; + char tmp8[2]; + +// define sc_bool_vector + sc_bv<4> tmp10; + tmp10[3] = 0; tmp10[2] = 1; tmp10[1] = 0; tmp10[0] = 1; + +// define 2 dimentional array + sc_bv<1> tmp11[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// + +// initialization of sc_array + + tmp7[0] = 3; + tmp7[1] = 12; + tmp8[0] = 'S'; + tmp8[1] = 'C'; + tmp11[0][0] = "1"; + tmp11[1][0] = "0"; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + + out_ack.write(true); + + //execute mixed data type addition operations + tmp1r = tmp1 >> (tmp7[0] % 9); + tmp2r = tmp2 >> 2; + tmp3r = tmp3 >> 1; + tmp4r = tmp4 >> (tmp7[1] % 9); + tmp5r = tmp3 >> (((unsigned int)tmp1.to_int()) % 32); + tmp6r = tmp6 >> 1; + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + //execute mixed data type addition operations + tmp1r = tmp1 >> (tmp7[0] % 9); + tmp2r = tmp2 >> (tmp4 % 9); + tmp3r = tmp3 >> (tmp5 % 33); + tmp4r = tmp4 >> 2; + tmp5r = tmp3 >> (((unsigned int)tmp5) % 33); + tmp6r = tmp6 >> (tmp2.to_uint() % 9); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.f new file mode 100644 index 000000000..998e0f309 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.f @@ -0,0 +1,4 @@ +sharing/display.cpp +sharing/main.cpp +sharing/sharing.cpp +sharing/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.h new file mode 100644 index 000000000..5552db43a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/sharing.h @@ -0,0 +1,126 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + sharing.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( sharing ) +{ + SC_HAS_PROCESS( sharing ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; // Input port + const sc_signal_bool_vector& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + sharing( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.cpp new file mode 100644 index 000000000..1263da802 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + + int counter = 0; + + tmp1 = "0b11011011"; + tmp2 = "0b00000001"; + tmp3 = 1; + tmp4 = -1; + tmp5 = 20000; + tmp6 = 'R'; + + while(counter<100){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " << tmp5 << " " << endl; + tmp1 = tmp1 + 1; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 1; + tmp4 = tmp4 + 1; + tmp5 = tmp5 + 1; + tmp6 = tmp6 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + counter++; + wait(); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.h new file mode 100644 index 000000000..6f7aeefc8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/stimulus.h @@ -0,0 +1,90 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& out_value1; // Output port + sc_signal_bool_vector& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/common.h new file mode 100644 index 000000000..8976a26a2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/common.h @@ -0,0 +1,47 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector4; +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector8; +typedef sc_signal<sc_lv<4> > sc_signal_logic_vector4; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.cpp new file mode 100644 index 000000000..5b863a7ed --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.cpp @@ -0,0 +1,142 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() + +{ + sc_bigint<8> tmp1; + sc_bigint<8> tmp1r; + sc_biguint<8> tmp2; + sc_biguint<8> tmp2r; + long tmp3; + long tmp3r; + int tmp4; + int tmp4r; + short tmp5; + short tmp5r; + char tmp6; + char tmp6r; + bool tmp7; + bool tmp7r; + sc_bv<4> tmp8; + sc_bv<4> tmp8r; + sc_lv<4> tmp9; + sc_lv<4> tmp9r; + +// define 1 dimensional array + int tmpa[2]; + char tmpb[2]; + +// reset_loop + if (reset.read() == true) { + out_valid.write(false); + out_ack.write(false); + wait(); + } else wait(); + +// +// main loop +// +// initialization of sc_array + + tmpa[0] = 12; + tmpa[1] = 127; + tmpb[1] = 'G'; + + + while(1) { + while(in_valid.read()==false) wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + tmp6 = in_value6.read(); + tmpb[0] = in_value7.read(); + tmp7 = in_value8.read(); + tmp8 = in_value9.read(); + tmp9 = in_value10.read(); + + out_ack.write(true); + + //execute mixed data type xor operations + + // signed(8) <- signed(8) ^ unsigned(8) + tmp1r = tmp1 ^ tmp2; + // unsigned(8) <- char ^ long + tmp2r = tmp6 ^ tmp3; + // long <- int ^ char + tmp3r = tmp4 ^ tmp6; + // int <- int ^ short + tmp4r = tmp4 ^ tmp5; + // short <- short ^ const + tmp5r = tmp5 ^ 5; + // char <- char_array[0] ^ int_array[1] + tmp6r = tmpb[0] ^ tmpa[1]; + // bool <- bool ^ bool; + tmp7r = tmp7 ^ tmp7; + // sc_bool_vector(4) <- sc_bool_vector(4) ^ sc_logic_vector(4) + tmp8r = tmp8 ^ tmp9; + // sc_logic_vector(4) <- sc_bool_vector(4) ^ "0111" + tmp9r = tmp9 ^ sc_bv<4>( "0111" ); + + //write outputs + out_value1.write(tmp1r); + out_value2.write(tmp2r); + out_value3.write(tmp3r); + out_value4.write(tmp4r); + out_value5.write(tmp5r); + out_value6.write(tmp6r); + out_value7.write(tmp7r); + out_value8.write(tmp8r); + out_value9.write(tmp9r); + + out_valid.write(true); + wait(); + out_ack.write(false); + out_valid.write(false); + + } + +} // End + + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.f new file mode 100644 index 000000000..64f4c05f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/stimulus.cpp +datatypes/display.cpp +datatypes/datatypes.cpp +datatypes/main.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.h new file mode 100644 index 000000000..9aba0ab1f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/datatypes.h @@ -0,0 +1,146 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + //==================================================================== + // [C] Always Needed Member Function + // -- constructor + // -- entry + //==================================================================== + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector8& in_value1; // Input port + const sc_signal_bool_vector8& in_value2; // Input port + const sc_signal<long>& in_value3; // Input port + const sc_signal<int>& in_value4; // Input port + const sc_signal<short>& in_value5; // Input port + const sc_signal<char>& in_value6; // Input port + const sc_signal<char>& in_value7; // Input port + const sc_signal<bool>& in_value8 ; + const sc_signal_bool_vector4& in_value9 ; // Input port + const sc_signal_logic_vector4& in_value10; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<bool>& out_ack; // Output port + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<bool>& out_value7; // Output port + sc_signal_bool_vector4& out_value8; // Output port + sc_signal_logic_vector4& out_value9; // Output port + sc_signal<bool>& out_valid; // Output port + + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<char>& IN_VALUE7, + const sc_signal<bool>& IN_VALUE8, + const sc_signal_bool_vector4& IN_VALUE9, + const sc_signal_logic_vector4& IN_VALUE10, + const sc_signal<bool>& IN_VALID, + + sc_signal<bool>& OUT_ACK, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<bool>& OUT_VALUE7, + sc_signal_bool_vector4& OUT_VALUE8, + sc_signal_logic_vector4& OUT_VALUE9, + sc_signal<bool>& OUT_VALID + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_value10 (IN_VALUE10), + in_valid (IN_VALID), + out_ack (OUT_ACK), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + +//Process Functionality: Described in the member function below + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.cpp new file mode 100644 index 000000000..0c6fdf20e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry() { + + int counter = 0; + while(counter++<40){ + do { wait(); } while ( in_valid == false); + cout << "Display: " << in_value1.read() << " " << in_value2.read() << " " << in_value3.read( +) << " " << in_value4.read() << " " << in_value5.read() << " " << in_value6.read() << " " << in_value7.read() << " " << in_value8.read() << " " << in_value9.read() <<endl; + do { wait(); } while ( in_valid == true); + } + sc_stop(); +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.h new file mode 100644 index 000000000..dc73106ac --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/display.h @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector8& in_value1; // Output port + const sc_signal_bool_vector8& in_value2; // Output port + const sc_signal<long>& in_value3; // Output port + const sc_signal<int>& in_value4; // Output port + const sc_signal<short>& in_value5; // Output port + const sc_signal<char>& in_value6; // Output port + const sc_signal<bool>& in_value7; // Output port + const sc_signal_bool_vector4& in_value8; // Output port + const sc_signal_logic_vector4& in_value9; // Output port + const sc_signal<bool>& in_valid; // Output port + + // + // Constructor + // + + display( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal_bool_vector8& IN_VALUE1, + const sc_signal_bool_vector8& IN_VALUE2, + const sc_signal<long>& IN_VALUE3, + const sc_signal<int>& IN_VALUE4, + const sc_signal<short>& IN_VALUE5, + const sc_signal<char>& IN_VALUE6, + const sc_signal<bool>& IN_VALUE7, + const sc_signal_bool_vector4& IN_VALUE8, + const sc_signal_logic_vector4& IN_VALUE9, + const sc_signal<bool>& IN_VALID + ) + : + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_value6 (IN_VALUE6), + in_value7 (IN_VALUE7), + in_value8 (IN_VALUE8), + in_value9 (IN_VALUE9), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + + + void entry(); +}; + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/golden/datatypes.log new file mode 100644 index 000000000..05838b4cf --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/golden/datatypes.log @@ -0,0 +1,84 @@ +SystemC Simulation +Stimuli: 85 2 12345678 -123456 20000 $ A 1 1 2 +Display: 01010111 01101010 -123420 -109600 20005 > 0 0011 0101 +Stimuli: 87 3 12345683 -123453 20006 $ B 0 2 3 +Display: 01010100 01110111 -123417 -109595 20003 = 0 0001 0100 +Stimuli: 89 4 12345688 -123450 20012 $ C 1 3 4 +Display: 01011101 01111100 -123422 -109590 20009 < 0 0111 0011 +Stimuli: 91 5 12345693 -123447 20018 $ D 0 4 5 +Display: 01011110 01111001 -123411 -109573 20023 ; 0 0001 0010 +Stimuli: 93 6 12345698 -123444 20024 $ E 1 5 6 +Display: 01011011 01000110 -123416 -109580 20029 : 0 0011 0001 +Stimuli: 95 7 12345703 -123441 20030 $ F 0 6 7 +Display: 01011000 01000011 -123413 -109583 20027 9 0 0001 0000 +Stimuli: 97 8 12345708 -123438 20036 $ G 1 7 8 +Display: 01101001 01001000 -123402 -109674 20033 8 0 1111 1111 +Stimuli: 99 9 12345713 -123435 20042 $ H 0 8 9 +Display: 01101010 01010101 -123407 -109665 20047 7 0 0001 1110 +Stimuli: 101 10 12345718 -123432 20048 $ I 1 9 10 +Display: 01101111 01010010 -123396 -109688 20053 6 0 0011 1101 +Stimuli: 103 11 12345723 -123429 20054 $ J 0 10 11 +Display: 01101100 01011111 -123393 -109683 20051 5 0 0001 1100 +Stimuli: 105 12 12345728 -123426 20060 $ K 1 11 12 +Display: 01100101 10100100 -123398 -109694 20057 4 0 0111 1011 +Stimuli: 107 13 12345733 -123423 20066 $ L 0 12 13 +Display: 01100110 10100001 -123451 -109693 20071 3 0 0001 1010 +Stimuli: 109 14 12345738 -123420 20072 $ M 1 13 14 +Display: 01100011 10101110 -123456 -109684 20077 2 0 0011 1001 +Stimuli: 111 15 12345743 -123417 20078 $ N 0 14 15 +Display: 01100000 10101011 -123453 -109687 20075 1 0 0001 1000 +Stimuli: 113 16 12345748 -123414 20084 $ O 1 15 0 +Display: 01100001 10110000 -123442 -109666 20081 0 0 1111 0111 +Stimuli: 115 17 12345753 -123411 20090 $ P 0 0 1 +Display: 01100010 10111101 -123447 -109673 20095 / 0 0001 0110 +Stimuli: 117 18 12345758 -123408 20096 $ Q 1 1 2 +Display: 01100111 10111010 -123436 -109712 20101 . 0 0011 0101 +Stimuli: 119 19 12345763 -123405 20102 $ R 0 2 3 +Display: 01100100 10000111 -123433 -109707 20099 - 0 0001 0100 +Stimuli: 121 20 12345768 -123402 20108 $ S 1 3 4 +Display: 01101101 10001100 -123438 -109702 20105 , 0 0111 0011 +Stimuli: 123 21 12345773 -123399 20114 $ T 0 4 5 +Display: 01101110 10001001 -123427 -109717 20119 + 0 0001 0010 +Stimuli: 125 22 12345778 -123396 20120 $ U 1 5 6 +Display: 01101011 10010110 -123432 -109724 20125 * 0 0011 0001 +Stimuli: 127 23 12345783 -123393 20126 $ V 0 6 7 +Display: 01101000 10010011 -123429 -109727 20123 ) 0 0001 0000 +Stimuli: -127 24 12345788 -123390 20132 $ W 1 7 8 +Display: 10011001 10011000 -123354 -110426 20129 ( 0 1111 1111 +Stimuli: -125 25 12345793 -123387 20138 $ X 0 8 9 +Display: 10011010 11100101 -123359 -110417 20143 ' 0 0001 1110 +Stimuli: -123 26 12345798 -123384 20144 $ Y 1 9 10 +Display: 10011111 11100010 -123348 -110408 20149 & 0 0011 1101 +Stimuli: -121 27 12345803 -123381 20150 $ Z 0 10 11 +Display: 10011100 11101111 -123345 -110403 20147 % 0 0001 1100 +Stimuli: -119 28 12345808 -123378 20156 $ [ 1 11 12 +Display: 10010101 11110100 -123350 -110414 20153 $ 0 0111 1011 +Stimuli: -117 29 12345813 -123375 20162 $ \ 0 12 13 +Display: 10010110 11110001 -123339 -110381 20167 # 0 0001 1010 +Stimuli: -115 30 12345818 -123372 20168 $ ] 1 13 14 +Display: 10010011 11111110 -123344 -110372 20173 " 0 0011 1001 +Stimuli: -113 31 12345823 -123369 20174 $ ^ 0 14 15 +Display: 10010000 11111011 -123341 -110375 20171 ! 0 0001 1000 +Stimuli: -111 32 12345828 -123366 20180 $ _ 1 15 0 +Display: 10110001 11000000 -123330 -110386 20177 0 1111 0111 +Stimuli: -109 33 12345833 -123363 20186 $ ` 0 0 1 +Display: 10110010 11001101 -123335 -110393 20191 0 0001 0110 +Stimuli: -107 34 12345838 -123360 20192 $ a 1 1 2 +Display: 10110111 11001010 -123388 -110400 20197 0 0011 0101 +Stimuli: -105 35 12345843 -123357 20198 $ b 0 2 3 +Display: 10110100 11010111 -123385 -110395 20195 0 0001 0100 +Stimuli: -103 36 12345848 -123354 20204 $ c 1 3 4 +Display: 10111101 11011100 -123390 -110390 20201 0 0111 0011 +Stimuli: -101 37 12345853 -123351 20210 $ d 0 4 5 +Display: 10111110 11011001 -123379 -110373 20215 0 0001 0010 +Stimuli: -99 38 12345858 -123348 20216 $ e 1 5 6 +Display: 10111011 00100110 -123384 -110380 20221 0 0011 0001 +Stimuli: -97 39 12345863 -123345 20222 $ f 0 6 7 +Display: 10111000 00100011 -123381 -110383 20219 0 0001 0000 +Stimuli: -95 40 12345868 -123342 20228 $ g 1 7 8 +Display: 10001001 00101000 -123370 -110282 20225 0 1111 1111 +Stimuli: -93 41 12345873 -123339 20234 $ h 0 8 9 +Display: 10001010 00110101 -123375 -110273 20239 0 0001 1110 +Stimuli: -91 42 12345878 -123336 20240 $ i 1 9 10 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/main.cpp new file mode 100644 index 000000000..ae4db66ee --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/main.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "datatypes.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector8 stimulus_line1; + sc_signal_bool_vector8 stimulus_line2; + sc_signal<long> stimulus_line3; + sc_signal<int> stimulus_line4; + sc_signal<short> stimulus_line5; + sc_signal<char> stimulus_line6; + sc_signal<char> stimulus_line7; + sc_signal<bool> stimulus_line8; + sc_signal_bool_vector4 stimulus_line9; + sc_signal_logic_vector4 stimulus_line10; + sc_signal<bool> input_valid; + sc_signal<bool> ack; + sc_signal<bool> output_valid; + sc_signal_bool_vector8 result_line1; + sc_signal_bool_vector8 result_line2; + sc_signal<long> result_line3; + sc_signal<int> result_line4; + sc_signal<short> result_line5; + sc_signal<char> result_line6; + sc_signal<bool> result_line7; + sc_signal_bool_vector4 result_line8; + sc_signal_logic_vector4 result_line9; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack); + + datatypes datatypes1( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + stimulus_line6, + stimulus_line7, + stimulus_line8, + stimulus_line9, + stimulus_line10, + input_valid, + ack, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + display display1( "display_block", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + result_line6, + result_line7, + result_line8, + result_line9, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.cpp new file mode 100644 index 000000000..384030f0d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + reset.write(true); + wait(); + reset.write(false); + + sc_signed tmp1(8); + sc_signed tmp2(8); + long tmp3; + int tmp4; + short tmp5; + char tmp6; + char tmp7; + bool tmp8; + sc_unsigned tmp9(4); + sc_unsigned tmp10(4); + + tmp1 = "0b01010101"; + tmp2 = "0b00000010"; + tmp3 = 12345678; + tmp4 = -123456; + tmp5 = 20000; + tmp6 = '$'; + tmp7 = 'A'; + tmp8 = "0"; + tmp9 = "0b0001"; + tmp10 = "0b0010"; + + while(true){ + out_valid.write(true); + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_value6.write(tmp6); + out_value7.write(tmp7); + out_value8.write(tmp8); + out_value9.write(tmp9); + out_value10.write(tmp10); + cout << "Stimuli: " << tmp1 << " " << tmp2 << " " << tmp3 << " " << tmp4 << " " + << tmp5 << " " << tmp6 << " " << tmp7 << " " << tmp8 << " " << tmp9 << " " << tmp10 <<endl; + tmp1 = tmp1 + 2; + tmp2 = tmp2 + 1; + tmp3 = tmp3 + 5; + tmp4 = tmp4 + 3; + tmp5 = tmp5 + 6; + tmp7 = tmp7 + 1; + tmp8 = !tmp8; + tmp9 = tmp9 + 1; + tmp10 = tmp10 + 1; + do { wait(); } while (in_ack==false); + out_valid.write(false); + wait(); + } +} +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.h new file mode 100644 index 000000000..8c700d060 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/stimulus.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector8& out_value1; // Output port + sc_signal_bool_vector8& out_value2; // Output port + sc_signal<long>& out_value3; // Output port + sc_signal<int>& out_value4; // Output port + sc_signal<short>& out_value5; // Output port + sc_signal<char>& out_value6; // Output port + sc_signal<char>& out_value7; // Output port + sc_signal<bool>& out_value8 ; + sc_signal_bool_vector4& out_value9 ; // Output port + sc_signal_logic_vector4& out_value10; // Output port + sc_signal<bool>& out_valid; // Output port + const sc_signal<bool>& in_ack; + + // + // Constructor + // + + stimulus( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + sc_signal<bool>& RESET, + sc_signal_bool_vector8& OUT_VALUE1, + sc_signal_bool_vector8& OUT_VALUE2, + sc_signal<long>& OUT_VALUE3, + sc_signal<int>& OUT_VALUE4, + sc_signal<short>& OUT_VALUE5, + sc_signal<char>& OUT_VALUE6, + sc_signal<char>& OUT_VALUE7, + sc_signal<bool>& OUT_VALUE8, + sc_signal_bool_vector4& OUT_VALUE9, + sc_signal_logic_vector4& OUT_VALUE10, + sc_signal<bool>& OUT_VALID, + const sc_signal<bool>& IN_ACK + ) + : + reset (RESET), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_value6 (OUT_VALUE6), + out_value7 (OUT_VALUE7), + out_value8 (OUT_VALUE8), + out_value9 (OUT_VALUE9), + out_value10 (OUT_VALUE10), + out_valid (OUT_VALID), + in_ack (IN_ACK) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + }; + void entry(); +}; +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/common.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/common.h new file mode 100644 index 000000000..1af56c523 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<8> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.cpp new file mode 100644 index 000000000..966569d48 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.h new file mode 100644 index 000000000..cf3a89370 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& in_data1; // Input port + const sc_signal<unsigned int>& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal_bool_vector& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& IN_DATA1, + const sc_signal<unsigned int>& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal_bool_vector& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/golden/xor_1.log b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/golden/xor_1.log new file mode 100644 index 000000000..71803889d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/golden/xor_1.log @@ -0,0 +1,39 @@ +SystemC Simulation +Stimuli : 1 1 00000001 1 1 at 13 ns +Display : 28 29 00001110 00011010 00011011 at 17 ns +Display : 31 30 00001101 00011001 00011000 at 20 ns +Stimuli : 12 12 00001100 12 12 at 24 ns +Display : 17 16 00000011 00010111 00010110 at 28 ns +Display : 18 19 00000000 00010100 00010101 at 31 ns +Stimuli : 23 23 00010111 23 23 at 35 ns +Display : 10 11 00011000 00001100 00001101 at 39 ns +Display : 9 8 00011011 00001111 00001110 at 42 ns +Stimuli : 34 34 00100010 34 34 at 46 ns +Display : 63 62 00101101 00111001 00111000 at 50 ns +Display : 60 61 00101110 00111010 00111011 at 53 ns +Stimuli : 45 45 00101101 45 45 at 57 ns +Display : 48 49 00100010 00110110 00110111 at 61 ns +Display : 51 50 00100001 00110101 00110100 at 64 ns +Stimuli : 56 56 00111000 56 56 at 68 ns +Display : 37 36 00110111 00100011 00100010 at 72 ns +Display : 38 39 00110100 00100000 00100001 at 75 ns +Stimuli : 67 67 01000011 67 67 at 79 ns +Display : 94 95 01001100 01011000 01011001 at 83 ns +Display : 93 92 01001111 01011011 01011010 at 86 ns +Stimuli : 78 78 01001110 78 78 at 90 ns +Display : 83 82 01000001 01010101 01010100 at 94 ns +Display : 80 81 01000010 01010110 01010111 at 97 ns +Stimuli : 89 89 01011001 89 89 at 101 ns +Display : 68 69 01010110 01000010 01000011 at 105 ns +Display : 71 70 01010101 01000001 01000000 at 108 ns +Stimuli : 100 100 01100100 100 100 at 112 ns +Display : 121 120 01101011 01111111 01111110 at 116 ns +Display : 122 123 01101000 01111100 01111101 at 119 ns +Stimuli : 111 111 01101111 111 111 at 123 ns +Display : 114 115 01100000 01110100 01110101 at 127 ns +Display : 113 112 01100011 01110111 01110110 at 130 ns +Stimuli : 122 122 01111010 122 122 at 134 ns +Display : 103 102 01110101 01100001 01100000 at 138 ns +Display : 100 101 01110110 01100010 01100011 at 141 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/main.cpp new file mode 100644 index 000000000..ba25bdac8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/main.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" +#include "display.h" +#include "xor_1.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<int> stimulus_line1; + sc_signal<unsigned int> stimulus_line2; + sc_signal_bool_vector stimulus_line3; + sc_signal_bool_vector stimulus_line4; + sc_signal_bool_vector stimulus_line5; + sc_signal<bool> input_valid; + sc_signal<bool> output_valid; + sc_signal<int> result_line1; + sc_signal<unsigned int> result_line2; + sc_signal_bool_vector result_line3; + sc_signal_bool_vector result_line4; + sc_signal_bool_vector result_line5; + + stimulus stimulus1("stimulus_block", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid); + + xor_1 xor1 ( "process_body", + clock, + reset, + stimulus_line1, + stimulus_line2, + stimulus_line3, + stimulus_line4, + stimulus_line5, + input_valid, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + display display1 ( "display", + clock, + result_line1, + result_line2, + result_line3, + result_line4, + result_line5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.cpp new file mode 100644 index 000000000..b7e17113f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + signed int send_value1 = 1; + unsigned int send_value2 = 1; + sc_lv<8> send_value3; + sc_signed send_value4(8); + sc_unsigned send_value5(8); + + + // sending some reset values + reset.write(true); + out_valid.write(false); + send_value3 = 1; + send_value4 = 1; + send_value5 = 1; + out_stimulus1.write(0); + out_stimulus2.write(0); + out_stimulus3.write(0); + out_stimulus4.write(0); + out_stimulus5.write(0); + wait(3); + reset.write(false); + // sending normal mode values + while(true){ + wait(10); + out_stimulus1.write( send_value1 ); + out_stimulus2.write( send_value2 ); + out_stimulus3.write( send_value3 ); + out_stimulus4.write( send_value4 ); + out_stimulus5.write( send_value5 ); + out_valid.write( true ); + cout << "Stimuli : " << send_value1 << " " + << send_value2 << " " + << send_value3 << " " + << send_value4 << " " + << send_value5 << " " << " at " + << sc_time_stamp() << endl; + send_value1 = send_value1+11; + send_value2 = send_value2+11; + send_value3 = send_value3.to_int()+11; + send_value4 = send_value4+11; + send_value5 = send_value5+11; + wait(); + out_valid.write( false ); + } +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.h new file mode 100644 index 000000000..9bd211ba6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& out_stimulus1; + sc_signal<unsigned int>& out_stimulus2; + sc_signal_bool_vector& out_stimulus3; + sc_signal_bool_vector& out_stimulus4; + sc_signal_bool_vector& out_stimulus5; + sc_signal<bool>& out_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& OUT_STIMULUS1, + sc_signal<unsigned int>& OUT_STIMULUS2, + sc_signal_bool_vector& OUT_STIMULUS3, + sc_signal_bool_vector& OUT_STIMULUS4, + sc_signal_bool_vector& OUT_STIMULUS5, + sc_signal<bool>& OUT_VALID + ) + : + reset(RESET), + out_stimulus1(OUT_STIMULUS1), + out_stimulus2(OUT_STIMULUS2), + out_stimulus3(OUT_STIMULUS3), + out_stimulus4(OUT_STIMULUS4), + out_stimulus5(OUT_STIMULUS5), + out_valid(OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.cpp b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.cpp new file mode 100644 index 000000000..623e1b2f9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + xor_1.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "xor_1.h" + +void xor_1::entry(){ + + signed int tmp1; + unsigned int tmp2; + sc_lv<8> tmp3; + sc_lv<8> tmp3_tmp; + sc_bigint<8> tmp4; + sc_biguint<8> tmp5; + + // reset_loop + if (reset.read() == true) { + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + // + while(1) { + while(in_valid.read()==false) wait(); + wait(); + + //reading the inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execute simple operations + tmp3_tmp = 0x0f; + tmp1 = tmp1 ^ 0x0f ^ 0x12; + tmp2 = tmp2 ^ 0x0f ^ 0x13 ; + tmp3 = tmp3 ^ tmp3_tmp; + tmp4 = tmp4 ^ 0x0f ^ 0x14 ; + tmp5 = tmp5 ^ 0x0f ^ 0x15 ; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + + //execute simple operations + tmp3_tmp = 0x03; + tmp1 ^= 0x03; + tmp2 ^= 0x03; + tmp3 ^= tmp3_tmp; + tmp4 ^= 0x03; + tmp5 ^= 0x03; + wait(); + + // write outputs + out_value1.write(tmp1); + out_value2.write(tmp2); + out_value3.write(tmp3); + out_value4.write(tmp4); + out_value5.write(tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.f b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.f new file mode 100644 index 000000000..aa5cf3860 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.f @@ -0,0 +1,4 @@ +xor_1/display.cpp +xor_1/main.cpp +xor_1/stimulus.cpp +xor_1/xor_1.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.h b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.h new file mode 100644 index 000000000..d56813a54 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/xor_1/xor_1.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + xor_1.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( xor_1 ) +{ + SC_HAS_PROCESS( xor_1 ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal<int>& in_value1; // Input port + const sc_signal<unsigned int>& in_value2; // Input port + const sc_signal_bool_vector& in_value3; // Input port + const sc_signal_bool_vector& in_value4; // Input port + const sc_signal_bool_vector& in_value5; // Input port + const sc_signal<bool>& in_valid; // Input port + sc_signal<int>& out_value1; // Output port + sc_signal<unsigned int>& out_value2; // Output port + sc_signal_bool_vector& out_value3; // Output port + sc_signal_bool_vector& out_value4; // Output port + sc_signal_bool_vector& out_value5; // Output port + sc_signal<bool>& out_valid; // Output port + + // + // Constructor + // + + xor_1 ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<int>& IN_VALUE1, + const sc_signal<unsigned int>& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal_bool_vector& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal<int>& OUT_VALUE1, + sc_signal<unsigned int>& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal_bool_vector& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Output port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.cpp new file mode 100644 index 000000000..b25ae0fa6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.cpp @@ -0,0 +1,171 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + balancing.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-10-25 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "balancing.h" + + +void balancing::entry(){ + + sc_biguint<4> tmp1; + sc_bigint<4> tmp2; + sc_biguint<4> tmp3; + unsigned int tmpint; + sc_unsigned out_tmp2(12); + sc_unsigned out_tmp3(12); + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_valid1.write(false); + out_valid2.write(false); + out_valid3.write(false); + out_tmp2 = 0; + out_tmp3 = 0; + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read(); + + //easy, just a bunch of different waits + out_valid1.write(true); + tmpint = tmp1.to_uint(); + switch (tmpint) { + case 4 : + wait(); + wait(); + wait(); + wait(); + out_value1.write(3); + wait(); + case 3 : + out_value1.write(2); + wait(); + wait(); + wait(); + case 2 : + out_value1.write(1); + wait(); + wait(); + default : + out_value1.write(tmp1); + wait(); + }; + out_valid1.write(false); + wait(); + + //the first branch should be pushed out in latency due to long delay + tmp2 = in_value2.read(); + tmp1 = tmp2; + out_valid2.write(true); + wait(); + tmpint = tmp1.to_uint(); + switch (tmpint) { + case 0 : + case 1 : + case 2 : + case 3 : + //long operation should extent latency + out_tmp2 = tmp2*tmp2*tmp2; + wait(); + case 4 : + case 5 : + case 6 : + case 7 : + //short operation should not extent latency + out_tmp2 = 4; + wait(); + case 8 | 9 | 10 | 11: + //wait statements should extent latency + out_tmp2 = 1; + wait(); + wait(); + wait(); + }; + wait(); + + out_value2.write( sc_biguint<4>( out_tmp2 ) ); + out_valid2.write(false); + wait(); + + //the first branch should be pushed out in latency due to long delay + tmp3 = in_value3.read(); + out_valid3.write(true); + wait(); + tmpint = tmp3.to_uint(); + switch (tmpint) { + case 0 : + case 1 : + case 2 : + case 3 : + //long operation should extent latency + out_tmp2 = tmp2*tmp2*tmp2; + wait(); + case 4 : + case 5 : + case 6 : + case 7 : + //short operation should not extent latency + out_tmp2 = 4; + case 8 : + case 9 : + case 10 : + case 11 : + //wait statements should extent latency + out_tmp2 = 1; + wait(); + wait(); + wait(); + }; + wait(); + out_value3.write( sc_biguint<4>( out_tmp3 ) ); + wait(); + out_valid3.write(false); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.f b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.f new file mode 100644 index 000000000..0a6488983 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.f @@ -0,0 +1,4 @@ +balancing/balancing.cpp +balancing/display.cpp +balancing/main.cpp +balancing/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.h new file mode 100644 index 000000000..a27e68018 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/balancing.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + balancing.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( balancing ) +{ + SC_HAS_PROCESS( balancing ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal<bool>& out_valid1; + sc_signal<bool>& out_valid2; + sc_signal<bool>& out_valid3; + + // + // Constructor + // + + balancing( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal<bool>& IN_VALID, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal<bool>& OUT_VALID1, + sc_signal<bool>& OUT_VALID2, + sc_signal<bool>& OUT_VALID3 + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_valid1 (OUT_VALID1), + out_valid2 (OUT_VALID2), + out_valid3 (OUT_VALID3) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.cpp new file mode 100644 index 000000000..55ff8cb26 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.cpp @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(i++<20) { + // Reading Data, and Counter i,j is counted up. + while (in_valid1.read()==false) wait(); + while (in_valid1.read()==true) { + cout << "Display : in_data1 " << in_data1.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid2.read()==false) wait(); + while (in_valid2.read()==true) { + cout << "Display : in_data2 " << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid3.read()==false) wait(); + while (in_valid3.read()==true) { + cout << "Display : in_data3 " << in_data3.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + }; + sc_stop(); +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.h new file mode 100644 index 000000000..f42a6b294 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal<bool>& in_valid1; + const sc_signal<bool>& in_valid2; + const sc_signal<bool>& in_valid3; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal<bool>& IN_VALID1, + const sc_signal<bool>& IN_VALID2, + const sc_signal<bool>& IN_VALID3 + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_valid1(IN_VALID1), + in_valid2(IN_VALID2), + in_valid3(IN_VALID3) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/golden/balancing.log b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/golden/balancing.log new file mode 100644 index 000000000..264e09ae0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/golden/balancing.log @@ -0,0 +1,163 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 at 2 ns +Display : in_data1 0000 at 4 ns +Display : in_data2 0000 at 6 ns +Display : in_data2 0000 at 7 ns +Display : in_data2 0000 at 8 ns +Display : in_data2 0000 at 9 ns +Display : in_data2 0000 at 10 ns +Display : in_data2 0000 at 11 ns +Display : in_data2 0000 at 12 ns +Display : in_data3 0000 at 14 ns +Display : in_data3 0000 at 15 ns +Display : in_data3 0000 at 16 ns +Display : in_data3 0000 at 17 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 at 18 ns +Display : in_data3 0000 at 18 ns +Display : in_data3 0000 at 19 ns +Display : in_data3 0000 at 20 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 at 34 ns +Display : in_data1 0001 at 36 ns +Display : in_data1 0001 at 37 ns +Display : in_data1 0010 at 38 ns +Display : in_data2 0001 at 40 ns +Display : in_data2 0001 at 41 ns +Display : in_data2 0001 at 42 ns +Display : in_data2 0001 at 43 ns +Display : in_data2 0001 at 44 ns +Display : in_data2 0001 at 45 ns +Display : in_data2 0001 at 46 ns +Display : in_data3 0000 at 48 ns +Display : in_data3 0000 at 49 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 at 50 ns +Display : in_data3 0000 at 50 ns +Display : in_data3 0000 at 51 ns +Display : in_data3 0000 at 52 ns +Display : in_data3 0000 at 53 ns +Display : in_data3 0000 at 54 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 at 66 ns +Display : in_data1 0010 at 68 ns +Display : in_data1 0010 at 69 ns +Display : in_data1 0010 at 70 ns +Display : in_data1 0010 at 71 ns +Display : in_data1 0011 at 72 ns +Display : in_data1 0010 at 73 ns +Display : in_data1 0010 at 74 ns +Display : in_data1 0010 at 75 ns +Display : in_data1 0001 at 76 ns +Display : in_data1 0001 at 77 ns +Display : in_data1 0100 at 78 ns +Display : in_data2 0001 at 80 ns +Display : in_data2 0001 at 81 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 at 82 ns +Display : in_data2 0001 at 82 ns +Display : in_data2 0001 at 83 ns +Display : in_data2 0001 at 84 ns +Display : in_data2 0001 at 85 ns +Display : in_data3 0000 at 87 ns +Display : in_data3 0000 at 88 ns +Display : in_data3 0000 at 89 ns +Display : in_data3 0000 at 90 ns +Display : in_data3 0000 at 91 ns +Display : in_data3 0000 at 92 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 at 98 ns +Display : in_data1 0110 at 100 ns +Display : in_data2 0001 at 102 ns +Display : in_data2 0001 at 103 ns +Display : in_data2 0001 at 104 ns +Display : in_data2 0001 at 105 ns +Display : in_data2 0001 at 106 ns +Display : in_data2 0001 at 107 ns +Display : in_data3 0000 at 109 ns +Display : in_data3 0000 at 110 ns +Display : in_data3 0000 at 111 ns +Display : in_data3 0000 at 112 ns +Display : in_data3 0000 at 113 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 at 114 ns +Display : in_data3 0000 at 114 ns +Display : in_data1 0111 at 116 ns +Display : in_data2 0001 at 118 ns +Display : in_data2 0001 at 119 ns +Display : in_data2 0001 at 120 ns +Display : in_data2 0001 at 121 ns +Display : in_data2 0001 at 122 ns +Display : in_data2 0001 at 123 ns +Display : in_data3 0000 at 125 ns +Display : in_data3 0000 at 126 ns +Display : in_data3 0000 at 127 ns +Display : in_data3 0000 at 128 ns +Display : in_data3 0000 at 129 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 at 130 ns +Display : in_data3 0000 at 130 ns +Display : in_data1 1000 at 132 ns +Display : in_data2 0001 at 134 ns +Display : in_data2 0001 at 135 ns +Display : in_data3 0000 at 137 ns +Display : in_data3 0000 at 138 ns +Display : in_data3 0000 at 139 ns +Display : in_data3 0000 at 140 ns +Display : in_data3 0000 at 141 ns +Display : in_data3 0000 at 142 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 at 146 ns +Display : in_data1 1001 at 148 ns +Display : in_data2 0001 at 150 ns +Display : in_data2 0001 at 151 ns +Display : in_data3 0000 at 153 ns +Display : in_data3 0000 at 154 ns +Display : in_data3 0000 at 155 ns +Display : in_data3 0000 at 156 ns +Display : in_data3 0000 at 157 ns +Display : in_data3 0000 at 158 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 at 162 ns +Display : in_data1 1010 at 164 ns +Display : in_data2 0001 at 166 ns +Display : in_data2 0001 at 167 ns +Display : in_data3 0000 at 169 ns +Display : in_data3 0000 at 170 ns +Display : in_data3 0000 at 171 ns +Display : in_data3 0000 at 172 ns +Display : in_data3 0000 at 173 ns +Display : in_data3 0000 at 174 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 at 178 ns +Display : in_data1 1011 at 180 ns +Display : in_data2 0001 at 182 ns +Display : in_data2 0001 at 183 ns +Display : in_data2 0001 at 184 ns +Display : in_data2 0001 at 185 ns +Display : in_data2 0001 at 186 ns +Display : in_data3 0000 at 188 ns +Display : in_data3 0000 at 189 ns +Display : in_data3 0000 at 190 ns +Display : in_data3 0000 at 191 ns +Display : in_data3 0000 at 192 ns +Display : in_data3 0000 at 193 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 at 194 ns +Display : in_data1 1100 at 196 ns +Display : in_data2 0001 at 198 ns +Display : in_data2 0001 at 199 ns +Display : in_data3 0000 at 201 ns +Display : in_data3 0000 at 202 ns +Display : in_data3 0000 at 203 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 at 210 ns +Display : in_data1 1101 at 212 ns +Display : in_data2 0001 at 214 ns +Display : in_data2 0001 at 215 ns +Display : in_data3 0000 at 217 ns +Display : in_data3 0000 at 218 ns +Display : in_data3 0000 at 219 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 at 226 ns +Display : in_data1 1110 at 228 ns +Display : in_data2 0001 at 230 ns +Display : in_data2 0001 at 231 ns +Display : in_data3 0000 at 233 ns +Display : in_data3 0000 at 234 ns +Display : in_data3 0000 at 235 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 at 242 ns +Display : in_data1 1111 at 244 ns +Display : in_data2 0001 at 246 ns +Display : in_data2 0001 at 247 ns +Display : in_data3 0000 at 249 ns +Display : in_data3 0000 at 250 ns +Display : in_data3 0000 at 251 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/main.cpp new file mode 100644 index 000000000..177cebdfb --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "balancing.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal<bool> output_valid1; + sc_signal<bool> output_valid2; + sc_signal<bool> output_valid3; + + + balancing balancing1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + input_valid, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.cpp new file mode 100644 index 000000000..65f97f5d6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " << i + << " at " << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(15); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.h new file mode 100644 index 000000000..a03d3e296 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/stimulus.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.cpp new file mode 100644 index 000000000..2d6ece6cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + + +void datatypes::entry() { + + sc_biguint<4> tmp1; + sc_bigint<4> tmp2; + sc_lv<4> tmp3; + sc_bv<4> tmp4; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_value4.write(0); + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + // reading inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + + //checking if condition on a range of bits + if (tmp1.range(1,3) == 4) { + out_value1.write(3); + } else if (tmp1.range(3,1) == 4) { + out_value1.write(2); + } else { + out_value1.write(tmp1); + }; + wait(); + + if (tmp2[2]) { + out_value2.write(3); + } else if ((bool)tmp1[1]==true) { + out_value2.write(2); + } else { + out_value2.write(tmp2); + }; + wait(); + + if (tmp3.range(1,3)=="000" || ((tmp3.range(3,1).to_uint()!=4) && + tmp3.range(3,1).to_uint()!=5 && tmp3.range(3,1).to_uint()!=6 && + tmp3.range(3,1).to_uint()!=7)) { + out_value3.write(1); + } else { + out_value3.write(tmp3); + }; + + if (tmp4.range(1,3)=="000" || (tmp4.range(3,1).to_uint()!=4 && + tmp4.range(3,1).to_uint()!=5 && tmp4.range(3,1).to_uint()!=6 && + tmp4.range(3,1).to_uint()!=7)) { + out_value4.write(1); + } else { + out_value4.write(tmp4); + }; + + out_valid.write(true); + wait(); + out_valid.write(false); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.f new file mode 100644 index 000000000..c767ce1c2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/datatypes.cpp +datatypes/display.cpp +datatypes/main.cpp +datatypes/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.h new file mode 100644 index 000000000..ac098dc52 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/datatypes.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal_bool_vector& in_value4; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal_bool_vector& out_value4; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal<bool>& OUT_VALID // Input port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_valid (OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.cpp new file mode 100644 index 000000000..530b46ce3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << " at " << sc_time_stamp() << endl; + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.h new file mode 100644 index 000000000..5fcc3c5b3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/display.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/golden/datatypes.log new file mode 100644 index 000000000..f183028c3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/golden/datatypes.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 stim4= 0 2 ns +Display : 0000 0000 0001 0001 at 6 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 stim4= 1 13 ns +Display : 0001 0001 0001 0001 at 17 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 stim4= 2 24 ns +Display : 0011 0010 0001 0001 at 28 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 stim4= 3 35 ns +Display : 0011 0010 0001 0001 at 39 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 stim4= 4 46 ns +Display : 0100 0011 0001 0001 at 50 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 stim4= 5 57 ns +Display : 0101 0011 0001 0001 at 61 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 stim4= 6 68 ns +Display : 0110 0011 0001 0001 at 72 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 stim4= 7 79 ns +Display : 0111 0011 0001 0001 at 83 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 stim4= 8 90 ns +Display : 0010 1000 1000 1000 at 94 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 stim4= 9 101 ns +Display : 0010 1001 1001 1001 at 105 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 stim4= 10 112 ns +Display : 1010 0010 1010 1010 at 116 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 stim4= 11 123 ns +Display : 1011 0010 1011 1011 at 127 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 stim4= 12 134 ns +Display : 1100 0011 1100 1100 at 138 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 stim4= 13 145 ns +Display : 1101 0011 1101 1101 at 149 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 stim4= 14 156 ns +Display : 1110 0011 1110 1110 at 160 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 stim4= 15 167 ns +Display : 1111 0011 1111 1111 at 171 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/main.cpp new file mode 100644 index 000000000..b7e9c4496 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal_bool_vector stim4; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal_bool_vector result4; + sc_signal<bool> output_valid; + + + + datatypes datatypes1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid, + result1, + result2, + result3, + result4, + output_valid + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + result4, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.cpp new file mode 100644 index 000000000..c3d3dea5a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.cpp @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + stim4.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + stim4.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " + << i << " stim4= " << i << " " + << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(10); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.h new file mode 100644 index 000000000..058da3946 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/stimulus.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal_bool_vector& stim4; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal_bool_vector& STIM4, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + stim4(STIM4), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.cpp new file mode 100644 index 000000000..f089446c8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.cpp @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(i++<20) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid1.read()==false) wait(); + while (in_valid1.read()==true) { + cout << "Display : in_data1 " << in_data1.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid2.read()==false) wait(); + while (in_valid2.read()==true) { + cout << "Display : in_data2 " << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid3.read()==false) wait(); + while (in_valid3.read()==true) { + cout << "Display : in_data3 " << in_data3.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + }; + sc_stop(); +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.h new file mode 100644 index 000000000..f42a6b294 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal<bool>& in_valid1; + const sc_signal<bool>& in_valid2; + const sc_signal<bool>& in_valid3; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal<bool>& IN_VALID1, + const sc_signal<bool>& IN_VALID2, + const sc_signal<bool>& IN_VALID3 + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_valid1(IN_VALID1), + in_valid2(IN_VALID2), + in_valid3(IN_VALID3) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.cpp new file mode 100644 index 000000000..90972a738 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.cpp @@ -0,0 +1,168 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + fsm.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "fsm.h" + +void fsm::entry(){ + + sc_biguint<4> tmp1; + sc_biguint<4> tmp2; + sc_biguint<4> tmp3; + sc_unsigned out_tmp2(12); + sc_unsigned out_tmp3(12); + + unsigned int tmpint; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_valid1.write(false); + out_valid2.write(false); + out_valid3.write(false); + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read(); + + //easy, just a bunch of different waits + out_valid1.write(true); + tmpint = tmp1.to_uint(); + wait(); + switch (tmpint) { + case 4 : + wait(); + wait(); + wait(); + wait(); + out_value1.write(3); + wait(); + break; + case 3 : + out_value1.write(2); + wait(); + wait(); + wait(); + break; + case 2 : + out_value1.write(1); + wait(); + wait(); + break; + default : + out_value1.write(tmp1); + wait(); + break; + }; + out_valid1.write(false); + wait(); + + //the first branch should be pushed out in latency due to long delay + tmp2 = in_value2.read(); + out_valid2.write(true); + wait(); + tmpint = tmp2.to_uint(); + switch (tmpint) { + case 0 : + case 1 : + case 2 : + case 3 : + //long operation should extent latency + out_tmp2 = tmp2*tmp2*tmp2; + wait(); + break; + case 4 : + case 5 : + case 6 : + case 7 : + //short operation should not extent latency + out_tmp2 = 4; + wait(); + break; + case 8 : + case 9 : + case 10 : + case 11 : + //wait statements should extent latency + out_tmp2 = 1; + wait(); + wait(); + wait(); + break; + }; + + out_value2.write( sc_biguint<4>( out_tmp2 ) ); + out_valid2.write(false); + wait(); + + // and just another short case, maybe later to check unbalanched case + tmp3 = in_value3.read(); + out_valid3.write(true); + wait(); + tmpint = tmp3.to_uint(); + switch (tmpint) { + case 0 : + case 1 : + case 2 : + case 3 : + //long operation should extent latency + out_tmp3 = tmp3*tmp3*tmp3; + wait(); + break; + default : + //short operation should not extent latency + out_tmp3 = 4; + wait(); + break; + }; + out_value3.write( sc_biguint<4>( out_tmp3 ) ); + wait(); + out_valid3.write(false); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.f b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.f new file mode 100644 index 000000000..c9b315fc7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.f @@ -0,0 +1,4 @@ +fsm/display.cpp +fsm/fsm.cpp +fsm/main.cpp +fsm/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.h new file mode 100644 index 000000000..ee5feb351 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/fsm.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + fsm.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( fsm ) +{ + SC_HAS_PROCESS( fsm ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal<bool>& out_valid1; + sc_signal<bool>& out_valid2; + sc_signal<bool>& out_valid3; + + // + // Constructor + // + + fsm( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal<bool>& IN_VALID, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal<bool>& OUT_VALID1, + sc_signal<bool>& OUT_VALID2, + sc_signal<bool>& OUT_VALID3 + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_valid1 (OUT_VALID1), + out_valid2 (OUT_VALID2), + out_valid3 (OUT_VALID3) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/golden/fsm.log b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/golden/fsm.log new file mode 100644 index 000000000..89ea6bcd6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/golden/fsm.log @@ -0,0 +1,142 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 at 2 ns +Display : in_data1 0000 at 4 ns +Display : in_data1 0000 at 5 ns +Display : in_data2 0000 at 7 ns +Display : in_data2 0000 at 8 ns +Display : in_data3 0000 at 10 ns +Display : in_data3 0000 at 11 ns +Display : in_data3 0000 at 12 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 at 18 ns +Display : in_data1 0000 at 20 ns +Display : in_data1 0001 at 21 ns +Display : in_data2 0000 at 23 ns +Display : in_data2 0000 at 24 ns +Display : in_data3 0000 at 26 ns +Display : in_data3 0000 at 27 ns +Display : in_data3 0001 at 28 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 at 34 ns +Display : in_data1 0001 at 36 ns +Display : in_data1 0001 at 37 ns +Display : in_data1 0001 at 38 ns +Display : in_data2 0001 at 40 ns +Display : in_data2 0001 at 41 ns +Display : in_data3 0001 at 43 ns +Display : in_data3 0001 at 44 ns +Display : in_data3 1000 at 45 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 at 50 ns +Display : in_data1 0001 at 52 ns +Display : in_data1 0010 at 53 ns +Display : in_data1 0010 at 54 ns +Display : in_data1 0010 at 55 ns +Display : in_data2 1000 at 57 ns +Display : in_data2 1000 at 58 ns +Display : in_data3 1000 at 60 ns +Display : in_data3 1000 at 61 ns +Display : in_data3 1011 at 62 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 at 66 ns +Display : in_data1 0010 at 68 ns +Display : in_data1 0010 at 69 ns +Display : in_data1 0010 at 70 ns +Display : in_data1 0010 at 71 ns +Display : in_data1 0010 at 72 ns +Display : in_data1 0011 at 73 ns +Display : in_data2 1011 at 75 ns +Display : in_data2 1011 at 76 ns +Display : in_data3 1011 at 78 ns +Display : in_data3 1011 at 79 ns +Display : in_data3 0100 at 80 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 at 82 ns +Display : in_data1 0011 at 84 ns +Display : in_data1 0101 at 85 ns +Display : in_data2 0100 at 87 ns +Display : in_data2 0100 at 88 ns +Display : in_data3 0100 at 90 ns +Display : in_data3 0100 at 91 ns +Display : in_data3 0100 at 92 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 at 98 ns +Display : in_data1 0101 at 100 ns +Display : in_data1 0110 at 101 ns +Display : in_data2 0100 at 103 ns +Display : in_data2 0100 at 104 ns +Display : in_data3 0100 at 106 ns +Display : in_data3 0100 at 107 ns +Display : in_data3 0100 at 108 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 at 114 ns +Display : in_data1 0110 at 116 ns +Display : in_data1 0111 at 117 ns +Display : in_data2 0100 at 119 ns +Display : in_data2 0100 at 120 ns +Display : in_data3 0100 at 122 ns +Display : in_data3 0100 at 123 ns +Display : in_data3 0100 at 124 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 at 130 ns +Display : in_data1 0111 at 132 ns +Display : in_data1 1000 at 133 ns +Display : in_data2 0100 at 135 ns +Display : in_data2 0100 at 136 ns +Display : in_data2 0100 at 137 ns +Display : in_data2 0100 at 138 ns +Display : in_data3 0100 at 140 ns +Display : in_data3 0100 at 141 ns +Display : in_data3 0100 at 142 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 at 146 ns +Display : in_data1 1000 at 148 ns +Display : in_data1 1001 at 149 ns +Display : in_data2 0001 at 151 ns +Display : in_data2 0001 at 152 ns +Display : in_data2 0001 at 153 ns +Display : in_data2 0001 at 154 ns +Display : in_data3 0100 at 156 ns +Display : in_data3 0100 at 157 ns +Display : in_data3 0100 at 158 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 at 162 ns +Display : in_data1 1001 at 164 ns +Display : in_data1 1010 at 165 ns +Display : in_data2 0001 at 167 ns +Display : in_data2 0001 at 168 ns +Display : in_data2 0001 at 169 ns +Display : in_data2 0001 at 170 ns +Display : in_data3 0100 at 172 ns +Display : in_data3 0100 at 173 ns +Display : in_data3 0100 at 174 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 at 178 ns +Display : in_data1 1010 at 180 ns +Display : in_data1 1011 at 181 ns +Display : in_data2 0001 at 183 ns +Display : in_data2 0001 at 184 ns +Display : in_data2 0001 at 185 ns +Display : in_data2 0001 at 186 ns +Display : in_data3 0100 at 188 ns +Display : in_data3 0100 at 189 ns +Display : in_data3 0100 at 190 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 at 194 ns +Display : in_data1 1011 at 196 ns +Display : in_data1 1100 at 197 ns +Display : in_data2 0001 at 199 ns +Display : in_data3 0100 at 201 ns +Display : in_data3 0100 at 202 ns +Display : in_data3 0100 at 203 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 at 210 ns +Display : in_data1 1100 at 212 ns +Display : in_data1 1101 at 213 ns +Display : in_data2 0001 at 215 ns +Display : in_data3 0100 at 217 ns +Display : in_data3 0100 at 218 ns +Display : in_data3 0100 at 219 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 at 226 ns +Display : in_data1 1101 at 228 ns +Display : in_data1 1110 at 229 ns +Display : in_data2 0001 at 231 ns +Display : in_data3 0100 at 233 ns +Display : in_data3 0100 at 234 ns +Display : in_data3 0100 at 235 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 at 242 ns +Display : in_data1 1110 at 244 ns +Display : in_data1 1111 at 245 ns +Display : in_data2 0001 at 247 ns +Display : in_data3 0100 at 249 ns +Display : in_data3 0100 at 250 ns +Display : in_data3 0100 at 251 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/main.cpp new file mode 100644 index 000000000..5280ddd17 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "fsm.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal<bool> output_valid1; + sc_signal<bool> output_valid2; + sc_signal<bool> output_valid3; + + + fsm fsm1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + input_valid, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.cpp new file mode 100644 index 000000000..65f97f5d6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " << i + << " at " << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(15); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.h new file mode 100644 index 000000000..a03d3e296 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/stimulus.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.cpp new file mode 100644 index 000000000..0135a0381 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.cpp @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.h new file mode 100644 index 000000000..74d4c67ba --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/display.h @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/golden/inlining.log b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/golden/inlining.log new file mode 100644 index 000000000..3a3a8c358 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/golden/inlining.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 stim4= 0 2 ns +Display : 0000 0000 at 6 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 stim4= 1 13 ns +Display : 0000 0001 at 17 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 stim4= 2 24 ns +Display : 0000 0010 at 28 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 stim4= 3 35 ns +Display : 0000 0011 at 39 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 stim4= 4 46 ns +Display : 0100 0100 at 50 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 stim4= 5 57 ns +Display : 0101 0101 at 61 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 stim4= 6 68 ns +Display : 0110 0110 at 72 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 stim4= 7 79 ns +Display : 0111 0111 at 83 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 stim4= 8 90 ns +Display : 1000 1000 at 94 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 stim4= 9 101 ns +Display : 1001 1001 at 105 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 stim4= 10 112 ns +Display : 1010 1010 at 116 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 stim4= 11 123 ns +Display : 1011 1011 at 127 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 stim4= 12 134 ns +Display : 1100 1100 at 138 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 stim4= 13 145 ns +Display : 1101 1101 at 149 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 stim4= 14 156 ns +Display : 1110 1110 at 160 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 stim4= 15 167 ns +Display : 1111 1111 at 171 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.cpp new file mode 100644 index 000000000..08da0e3ba --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.cpp @@ -0,0 +1,112 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + inlining.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "inlining.h" + +// list of defines +#define clock(a) wait(a) +#define intu4(a) sc_biguint<4> a; +#define vec4(a) sc_lv<4> a; +#define my_case(a, b, c) switch (a) { \ + case 0: \ + case 1: \ + case 2: \ + case 3: \ + b = 0; \ + break; \ + default : \ + b = c; \ + break; \ + }; +#define my_wait_case(a, b, c) switch (a) { \ + case 0: \ + case 1: \ + case 2: \ + case 3: \ + b = 0; \ + wait(); \ + break; \ + default : \ + b = c; \ + wait(); \ + break; \ + }; + +void inlining::entry(){ + + int tmp1; + int tmp2; + vec4(tmp3); + sc_bv<4> tmp4; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_valid.write(false); + clock(1); + } else clock(1); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read().to_int(); + tmp2 = in_value2.read().to_int(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + + //execution + my_wait_case(tmp1, tmp3, tmp4); + out_value1.write(tmp3); + clock(1); + + my_case(tmp2, tmp3, tmp4); + out_value2.write(tmp4); + out_valid.write(true); + clock(1); + out_valid.write(false); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.f b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.f new file mode 100644 index 000000000..fc00870e2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.f @@ -0,0 +1,4 @@ +inlining/display.cpp +inlining/inlining.cpp +inlining/main.cpp +inlining/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.h new file mode 100644 index 000000000..70380e24e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/inlining.h @@ -0,0 +1,93 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + inlining.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( inlining ) +{ + SC_HAS_PROCESS( inlining ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1 ; + const sc_signal_bool_vector& in_value2 ; + const sc_signal_bool_vector& in_value3 ; + const sc_signal_bool_vector& in_value4 ; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + inlining( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<bool>& OUT_VALID // Input port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_valid (OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + // + void entry (); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/main.cpp new file mode 100644 index 000000000..c859cafce --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/main.cpp @@ -0,0 +1,92 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "inlining.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal_bool_vector stim4; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal<bool> output_valid; + + + + inlining inlining1 ( + "process_body", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid, + result1, + result2, + output_valid + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid + ); + + display display1 ("display", + clock, + result1, + result2, + output_valid + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.cpp new file mode 100644 index 000000000..c3d3dea5a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.cpp @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + stim4.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + stim4.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " + << i << " stim4= " << i << " " + << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(10); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.h new file mode 100644 index 000000000..058da3946 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/stimulus.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal_bool_vector& stim4; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal_bool_vector& STIM4, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + stim4(STIM4), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/balancing.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/balancing.cpp new file mode 100644 index 000000000..13ee2a807 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/balancing.cpp @@ -0,0 +1,135 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + balancing.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "balancing.h" + +void balancing::entry(){ + + sc_biguint<4> tmp1; + sc_biguint<4> tmp2; + sc_biguint<4> tmp3; + sc_unsigned out_tmp2(12); + sc_unsigned out_tmp3(12); + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_valid1.write(false); + out_valid2.write(false); + out_valid3.write(false); + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read(); + + //easy, just a bunch of different waits + out_valid1.write(true); + if (tmp1 == 4) { + wait(); + wait(); + wait(); + wait(); + out_value1.write(3); + wait(); + } else if (tmp1 == 3) { + out_value1.write(2); + wait(); + wait(); + wait(); + } else if (tmp1 == 2) { + out_value1.write(1); + wait(); + wait(); + } else { + out_value1.write(tmp1); + wait(); + }; + out_valid1.write(false); + wait(); + + //the first branch should be pushed out in latency due to long delay + tmp2 = in_value2.read(); + out_valid2.write(true); + wait(); + if (tmp2<4) { + //long operation should extent latency + out_tmp2 = tmp2*tmp2*tmp2; + wait(); + } else if (tmp2<8) { + //short operation should not extent latency + out_tmp2 = 4; + wait(); + } else if (tmp2<12) { + //wait statements should extent latency + out_tmp2 = 1; + wait(); + wait(); + wait(); + }; + wait(); + + out_value2.write( sc_biguint<4>( out_tmp2 ) ); + out_valid2.write(false); + wait(); + + //if branch without else + tmp3 = in_value3.read(); + out_valid3.write(true); + wait(); + if (tmp3<8) { + out_tmp3 = 4; + wait(); + } + + out_value3.write( sc_biguint<4>( out_tmp3 ) ); + wait(); + out_valid3.write(false); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/balancing.f b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/balancing.f new file mode 100644 index 000000000..2d727063d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/balancing.f @@ -0,0 +1,4 @@ +balancing/main.cpp +balancing/stimulus.cpp +balancing/display.cpp +balancing/balancing.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/balancing.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/balancing.h new file mode 100644 index 000000000..d32742dc6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/balancing.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + balancing.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( balancing ) +{ + SC_HAS_PROCESS( balancing ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal<bool>& out_valid1; + sc_signal<bool>& out_valid2; + sc_signal<bool>& out_valid3; + + // + // Constructor + // + + balancing( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal<bool>& IN_VALID, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal<bool>& OUT_VALID1, + sc_signal<bool>& OUT_VALID2, + sc_signal<bool>& OUT_VALID3 + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_valid1 (OUT_VALID1), + out_valid2 (OUT_VALID2), + out_valid3 (OUT_VALID3) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/display.cpp new file mode 100644 index 000000000..f61b61003 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/display.cpp @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(i++<20) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid1.read()==false) wait(); + while (in_valid1.read()==true) { + cout << "Display : in_data1 " << in_data1.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid2.read()==false) wait(); + while (in_valid2.read()==true) { + cout << "Display : in_data2 " << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid3.read()==false) wait(); + while (in_valid3.read()==true) { + cout << "Display : in_data3 " << in_data3.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + }; + sc_stop(); +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/display.h new file mode 100644 index 000000000..5860d2d9f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal<bool>& in_valid1; + const sc_signal<bool>& in_valid2; + const sc_signal<bool>& in_valid3; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal<bool>& IN_VALID1, + const sc_signal<bool>& IN_VALID2, + const sc_signal<bool>& IN_VALID3 + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_valid1(IN_VALID1), + in_valid2(IN_VALID2), + in_valid3(IN_VALID3) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/golden/balancing.log b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/golden/balancing.log new file mode 100644 index 000000000..b3ca99775 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/golden/balancing.log @@ -0,0 +1,134 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 at 2 ns +Display : in_data1 0000 at 4 ns +Display : in_data2 0000 at 6 ns +Display : in_data2 0000 at 7 ns +Display : in_data2 0000 at 8 ns +Display : in_data3 0000 at 10 ns +Display : in_data3 0000 at 11 ns +Display : in_data3 0100 at 12 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 at 18 ns +Display : in_data1 0001 at 20 ns +Display : in_data2 0000 at 22 ns +Display : in_data2 0000 at 23 ns +Display : in_data2 0000 at 24 ns +Display : in_data3 0100 at 26 ns +Display : in_data3 0100 at 27 ns +Display : in_data3 0100 at 28 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 at 34 ns +Display : in_data1 0001 at 36 ns +Display : in_data1 0001 at 37 ns +Display : in_data2 0001 at 39 ns +Display : in_data2 0001 at 40 ns +Display : in_data2 0001 at 41 ns +Display : in_data3 0100 at 43 ns +Display : in_data3 0100 at 44 ns +Display : in_data3 0100 at 45 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 at 50 ns +Display : in_data1 0010 at 52 ns +Display : in_data1 0010 at 53 ns +Display : in_data1 0010 at 54 ns +Display : in_data2 1000 at 56 ns +Display : in_data2 1000 at 57 ns +Display : in_data2 1000 at 58 ns +Display : in_data3 0100 at 60 ns +Display : in_data3 0100 at 61 ns +Display : in_data3 0100 at 62 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 at 66 ns +Display : in_data1 0010 at 68 ns +Display : in_data1 0010 at 69 ns +Display : in_data1 0010 at 70 ns +Display : in_data1 0010 at 71 ns +Display : in_data1 0011 at 72 ns +Display : in_data2 1011 at 74 ns +Display : in_data2 1011 at 75 ns +Display : in_data2 1011 at 76 ns +Display : in_data3 0100 at 78 ns +Display : in_data3 0100 at 79 ns +Display : in_data3 0100 at 80 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 at 82 ns +Display : in_data1 0101 at 84 ns +Display : in_data2 0100 at 86 ns +Display : in_data2 0100 at 87 ns +Display : in_data2 0100 at 88 ns +Display : in_data3 0100 at 90 ns +Display : in_data3 0100 at 91 ns +Display : in_data3 0100 at 92 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 at 98 ns +Display : in_data1 0110 at 100 ns +Display : in_data2 0100 at 102 ns +Display : in_data2 0100 at 103 ns +Display : in_data2 0100 at 104 ns +Display : in_data3 0100 at 106 ns +Display : in_data3 0100 at 107 ns +Display : in_data3 0100 at 108 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 at 114 ns +Display : in_data1 0111 at 116 ns +Display : in_data2 0100 at 118 ns +Display : in_data2 0100 at 119 ns +Display : in_data2 0100 at 120 ns +Display : in_data3 0100 at 122 ns +Display : in_data3 0100 at 123 ns +Display : in_data3 0100 at 124 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 at 130 ns +Display : in_data1 1000 at 132 ns +Display : in_data2 0100 at 134 ns +Display : in_data2 0100 at 135 ns +Display : in_data2 0100 at 136 ns +Display : in_data2 0100 at 137 ns +Display : in_data2 0100 at 138 ns +Display : in_data3 0100 at 140 ns +Display : in_data3 0100 at 141 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 at 146 ns +Display : in_data1 1001 at 148 ns +Display : in_data2 0001 at 150 ns +Display : in_data2 0001 at 151 ns +Display : in_data2 0001 at 152 ns +Display : in_data2 0001 at 153 ns +Display : in_data2 0001 at 154 ns +Display : in_data3 0100 at 156 ns +Display : in_data3 0100 at 157 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 at 162 ns +Display : in_data1 1010 at 164 ns +Display : in_data2 0001 at 166 ns +Display : in_data2 0001 at 167 ns +Display : in_data2 0001 at 168 ns +Display : in_data2 0001 at 169 ns +Display : in_data2 0001 at 170 ns +Display : in_data3 0100 at 172 ns +Display : in_data3 0100 at 173 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 at 178 ns +Display : in_data1 1011 at 180 ns +Display : in_data2 0001 at 182 ns +Display : in_data2 0001 at 183 ns +Display : in_data2 0001 at 184 ns +Display : in_data2 0001 at 185 ns +Display : in_data2 0001 at 186 ns +Display : in_data3 0100 at 188 ns +Display : in_data3 0100 at 189 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 at 194 ns +Display : in_data1 1100 at 196 ns +Display : in_data2 0001 at 198 ns +Display : in_data2 0001 at 199 ns +Display : in_data3 0100 at 201 ns +Display : in_data3 0100 at 202 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 at 210 ns +Display : in_data1 1101 at 212 ns +Display : in_data2 0001 at 214 ns +Display : in_data2 0001 at 215 ns +Display : in_data3 0100 at 217 ns +Display : in_data3 0100 at 218 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 at 226 ns +Display : in_data1 1110 at 228 ns +Display : in_data2 0001 at 230 ns +Display : in_data2 0001 at 231 ns +Display : in_data3 0100 at 233 ns +Display : in_data3 0100 at 234 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 at 242 ns +Display : in_data1 1111 at 244 ns +Display : in_data2 0001 at 246 ns +Display : in_data2 0001 at 247 ns +Display : in_data3 0100 at 249 ns +Display : in_data3 0100 at 250 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/main.cpp new file mode 100644 index 000000000..01e223141 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "balancing.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal<bool> output_valid1; + sc_signal<bool> output_valid2; + sc_signal<bool> output_valid3; + + + balancing balancing1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + input_valid, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/stimulus.cpp new file mode 100644 index 000000000..53a319114 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/stimulus.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " << i + << " at " << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(15); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/stimulus.h new file mode 100644 index 000000000..1bc242809 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/stimulus.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/conditions.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/conditions.cpp new file mode 100644 index 000000000..5ecc74334 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/conditions.cpp @@ -0,0 +1,129 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + conditions.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "conditions.h" + +void conditions::entry(){ + + sc_biguint<4> tmp1; + sc_bigint<4> tmp2; + sc_biguint<4> tmp2a; + sc_lv<4> tmp3; + sc_bv<4> tmp4; + int tmp5; + bool cond_tmp; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_value4.write(0); + out_value5.write(0); + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + // complex condition on variables + if ((tmp1==4) && (tmp2<6) || (tmp5+tmp4.to_int()==6)) { + out_value1.write(4); + } else { + out_value1.write(tmp1); + }; + wait(); + + // complex conditions on signal reads + if ((in_value1.read().to_uint()==4) && (in_value2.read().to_int()<6) || + (in_value4.read().to_int()+in_value5.read()==6)) { + out_value2.write(4); + } else { + out_value2.write(tmp1); + }; + wait(); + + //reading inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + // complex conditions outside the if; does it matter for timing? + cond_tmp = (tmp1==4) && (tmp2<6) || (tmp5+tmp4.to_int()==6); + if (cond_tmp) { + out_value3.write(4); + } else { + out_value3.write(tmp1); + }; + wait(); + + // arithmetic if can only be done when using the same datatypes + // therefor the temporary assignment + tmp2a = 0; + out_value4.write((tmp3.to_int()==4) && (tmp1<6) || + (tmp5+tmp2.to_int()==6)?tmp2a:tmp1); + wait(); + + // arithmetic if can only be done when using the same datatypes + // therefor the temporary assignment + tmp5 = tmp2.to_int(); + out_value5.write((in_value3.read().to_int()==4) && + (in_value1.read().to_int()<6) || + (in_value5.read()+in_value2.read().to_int()==6)? + 0:tmp5); + out_valid.write(true); + wait(); + out_valid.write(false); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/conditions.f b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/conditions.f new file mode 100644 index 000000000..ed7a236e6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/conditions.f @@ -0,0 +1,4 @@ +conditions/display.cpp +conditions/stimulus.cpp +conditions/main.cpp +conditions/conditions.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/conditions.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/conditions.h new file mode 100644 index 000000000..f2ceadb83 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/conditions.h @@ -0,0 +1,108 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + conditions.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( conditions ) +{ + SC_HAS_PROCESS( conditions ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal_bool_vector& in_value4; + const sc_signal<int>& in_value5 ; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal_bool_vector& out_value4; + sc_signal<int>& out_value5; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + conditions( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal<int>& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal<int>& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Input port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/display.cpp new file mode 100644 index 000000000..fc643330d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/display.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/display.h new file mode 100644 index 000000000..36001ab41 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal<int>& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal<int>& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/golden/conditions.log b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/golden/conditions.log new file mode 100644 index 000000000..3432fae28 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/golden/conditions.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 stim4= 0 stim5= 0 2 ns +Display : 0000 0000 0000 0000 0 at 8 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 stim4= 1 stim5= 1 13 ns +Display : 0001 0001 0001 0001 1 at 19 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 stim4= 2 stim5= 2 24 ns +Display : 0010 0010 0010 0010 2 at 30 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 stim4= 3 stim5= 3 35 ns +Display : 0100 0100 0100 0000 0 at 41 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 stim4= 4 stim5= 4 46 ns +Display : 0100 0100 0100 0000 0 at 52 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 stim4= 5 stim5= 5 57 ns +Display : 0101 0101 0101 0101 5 at 63 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 stim4= 6 stim5= 6 68 ns +Display : 0110 0110 0110 0110 6 at 74 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 stim4= 7 stim5= 7 79 ns +Display : 0111 0111 0111 0111 7 at 85 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 stim4= 8 stim5= 8 90 ns +Display : 1000 1000 1000 1000 -8 at 96 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 stim4= 9 stim5= 9 101 ns +Display : 1001 1001 1001 1001 -7 at 107 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 stim4= 10 stim5= 10 112 ns +Display : 1010 1010 1010 1010 -6 at 118 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 stim4= 11 stim5= 11 123 ns +Display : 0100 0100 0100 0000 0 at 129 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 stim4= 12 stim5= 12 134 ns +Display : 1100 1100 1100 1100 -4 at 140 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 stim4= 13 stim5= 13 145 ns +Display : 1101 1101 1101 1101 -3 at 151 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 stim4= 14 stim5= 14 156 ns +Display : 1110 1110 1110 1110 -2 at 162 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 stim4= 15 stim5= 15 167 ns +Display : 1111 1111 1111 1111 -1 at 173 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/main.cpp new file mode 100644 index 000000000..bbb3a183b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/main.cpp @@ -0,0 +1,106 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "conditions.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal_bool_vector stim4; + sc_signal<int> stim5; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal_bool_vector result4; + sc_signal<int> result5; + sc_signal<bool> output_valid; + + + + conditions conditions1 ( + "process_body", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + stim5, + input_valid, + result1, + result2, + result3, + result4, + result5, + output_valid + ); + + stimulus stimulus1 ( + "stimulus", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + stim5, + input_valid + ); + + display display1 ( + "display", + clock, + result1, + result2, + result3, + result4, + result5, + output_valid + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/stimulus.cpp new file mode 100644 index 000000000..f45313792 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/stimulus.cpp @@ -0,0 +1,73 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + stim4.write(0); + stim5.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + stim4.write(i); + stim5.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " + << i << " stim4= " << i << " stim5= " << i << " " + << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(10); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/stimulus.h new file mode 100644 index 000000000..813c53e1b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/conditions/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal_bool_vector& stim4; + sc_signal<int>& stim5; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal_bool_vector& STIM4, + sc_signal<int>& STIM5, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + stim4(STIM4), + stim5(STIM5), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/datatypes.cpp new file mode 100644 index 000000000..145f7181d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/datatypes.cpp @@ -0,0 +1,119 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" + +void datatypes::entry() { + + sc_biguint<4> tmp1; + sc_bigint<4> tmp2; + sc_lv<4> tmp3; + sc_bv<4> tmp4; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_value4.write(0); + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + // reading inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + + // checking if condition on a range of bits + if (tmp1.range(1,3) == 4) { + out_value1.write(3); + } else if (tmp1.range(3,1) == 4) { + out_value1.write(2); + } else { + out_value1.write(tmp1); + }; + wait(); + + // checking if condition on bit part + if (tmp2[2]) { + out_value2.write(3); + } else if ((bool)tmp1[1]==true) { + out_value2.write(2); + } else { + out_value2.write(tmp2); + }; + wait(); + + // checking if condition on a range of bits in complex condition + if (tmp3.range(1,3)=="000" || ((tmp3.range(3,1).to_uint()!=4) && + tmp3.range(3,1).to_uint()!=5 && tmp3.range(3,1).to_uint()!=6 && + tmp3.range(3,1).to_uint()!=7)) { + out_value3.write(1); + } else { + out_value3.write(tmp3); + }; + + // checking if condition on a range of bits in complex condition + // on signal reads inside condition + if (in_value4.read().range(1,3)=="000" || + (in_value4.read().range(3,1).to_uint()!=4 && + in_value4.read().range(3,1).to_uint()!=5 && + in_value4.read().range(3,1).to_uint()!=6 && + in_value4.read().range(3,1).to_uint()!=7)) { + out_value4.write(1); + } else { + out_value4.write(tmp4); + }; + + out_valid.write(true); + wait(); + out_valid.write(false); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/datatypes.f new file mode 100644 index 000000000..be086769d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/datatypes.f @@ -0,0 +1,4 @@ +datatypes/display.cpp +datatypes/main.cpp +datatypes/stimulus.cpp +datatypes/datatypes.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/datatypes.h new file mode 100644 index 000000000..43be41785 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/datatypes.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( datatypes ) +{ + SC_HAS_PROCESS( datatypes ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal_bool_vector& in_value4; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal_bool_vector& out_value4; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + datatypes( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal<bool>& OUT_VALID // Input port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_valid (OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/display.cpp new file mode 100644 index 000000000..ceaa882b1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/display.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << " at " << sc_time_stamp() << endl; + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/display.h new file mode 100644 index 000000000..3ff6b921c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/display.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/golden/datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/golden/datatypes.log new file mode 100644 index 000000000..f183028c3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/golden/datatypes.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 stim4= 0 2 ns +Display : 0000 0000 0001 0001 at 6 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 stim4= 1 13 ns +Display : 0001 0001 0001 0001 at 17 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 stim4= 2 24 ns +Display : 0011 0010 0001 0001 at 28 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 stim4= 3 35 ns +Display : 0011 0010 0001 0001 at 39 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 stim4= 4 46 ns +Display : 0100 0011 0001 0001 at 50 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 stim4= 5 57 ns +Display : 0101 0011 0001 0001 at 61 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 stim4= 6 68 ns +Display : 0110 0011 0001 0001 at 72 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 stim4= 7 79 ns +Display : 0111 0011 0001 0001 at 83 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 stim4= 8 90 ns +Display : 0010 1000 1000 1000 at 94 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 stim4= 9 101 ns +Display : 0010 1001 1001 1001 at 105 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 stim4= 10 112 ns +Display : 1010 0010 1010 1010 at 116 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 stim4= 11 123 ns +Display : 1011 0010 1011 1011 at 127 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 stim4= 12 134 ns +Display : 1100 0011 1100 1100 at 138 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 stim4= 13 145 ns +Display : 1101 0011 1101 1101 at 149 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 stim4= 14 156 ns +Display : 1110 0011 1110 1110 at 160 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 stim4= 15 167 ns +Display : 1111 0011 1111 1111 at 171 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/main.cpp new file mode 100644 index 000000000..0eee3db1c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "datatypes.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal_bool_vector stim4; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal_bool_vector result4; + sc_signal<bool> output_valid; + + + + datatypes datatypes1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid, + result1, + result2, + result3, + result4, + output_valid + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + result4, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/stimulus.cpp new file mode 100644 index 000000000..2e897dacc --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/stimulus.cpp @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + stim4.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + stim4.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " + << i << " stim4= " << i << " " + << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(10); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/stimulus.h new file mode 100644 index 000000000..a82afff4c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/stimulus.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal_bool_vector& stim4; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal_bool_vector& STIM4, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + stim4(STIM4), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/display.cpp new file mode 100644 index 000000000..f61b61003 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/display.cpp @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(i++<20) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid1.read()==false) wait(); + while (in_valid1.read()==true) { + cout << "Display : in_data1 " << in_data1.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid2.read()==false) wait(); + while (in_valid2.read()==true) { + cout << "Display : in_data2 " << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + while (in_valid3.read()==false) wait(); + while (in_valid3.read()==true) { + cout << "Display : in_data3 " << in_data3.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + }; + }; + sc_stop(); +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/display.h new file mode 100644 index 000000000..5860d2d9f --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal<bool>& in_valid1; + const sc_signal<bool>& in_valid2; + const sc_signal<bool>& in_valid3; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal<bool>& IN_VALID1, + const sc_signal<bool>& IN_VALID2, + const sc_signal<bool>& IN_VALID3 + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_valid1(IN_VALID1), + in_valid2(IN_VALID2), + in_valid3(IN_VALID3) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/fsm.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/fsm.cpp new file mode 100644 index 000000000..6735f4d22 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/fsm.cpp @@ -0,0 +1,138 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + fsm.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-10-25 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "fsm.h" + +void fsm::entry(){ + + sc_biguint<4> tmp1; + sc_biguint<4> tmp2; + sc_biguint<4> tmp3; + sc_unsigned out_tmp2(12); + sc_unsigned out_tmp3(12); + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_valid1.write(false); + out_valid2.write(false); + out_valid3.write(false); + out_tmp3 = 0; + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read(); + //easy, just a bunch of different waits + out_valid1.write(true); + wait(); + if (tmp1 == 4) { + wait(); + wait(); + wait(); + wait(); + out_value1.write(3); + wait(); + } else if (tmp1 == 3) { + out_value1.write(2); + wait(); + wait(); + wait(); + } else if (tmp1 == 2) { + out_value1.write(1); + wait(); + wait(); + } else { + out_value1.write(tmp1); + wait(); + }; + out_valid1.write(false); + wait(); + + //the first branch should be pushed out in latency due to long delay + tmp2 = in_value2.read(); + out_valid2.write(true); + wait(); + if (tmp2<4) { + //long operation should extent latency + out_tmp2 = tmp2*tmp2*tmp2; + wait(); + } else if (tmp2<8) { + //short operation should not extent latency + out_tmp2 = 4; + wait(); + } else if (tmp2<12) { + //wait statements should extent latency + out_tmp2 = 1; + wait(); + wait(); + wait(); + } else { + wait(); + }; + wait(); + + out_value2.write( sc_biguint<4>( out_tmp2 ) ); + out_valid2.write(false); + wait(); + + // if branch without else maybe check later + tmp3 = in_value3.read(); + out_valid3.write(true); +// wait(); +// if (tmp3<8) { +// out_tmp3 = 4; +// wait(); +// } + + out_value3.write( sc_biguint<4>( out_tmp3 ) ); + wait(); + out_valid3.write(false); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/fsm.f b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/fsm.f new file mode 100644 index 000000000..67fa931e6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/fsm.f @@ -0,0 +1,4 @@ +fsm/main.cpp +fsm/stimulus.cpp +fsm/display.cpp +fsm/fsm.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/fsm.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/fsm.h new file mode 100644 index 000000000..9f67e156c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/fsm.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + fsm.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( fsm ) +{ + SC_HAS_PROCESS( fsm ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal<bool>& out_valid1; + sc_signal<bool>& out_valid2; + sc_signal<bool>& out_valid3; + + // + // Constructor + // + + fsm( + sc_module_name NAME, // reference name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal<bool>& IN_VALID, + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal<bool>& OUT_VALID1, + sc_signal<bool>& OUT_VALID2, + sc_signal<bool>& OUT_VALID3 + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_valid1 (OUT_VALID1), + out_valid2 (OUT_VALID2), + out_valid3 (OUT_VALID3) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/golden/fsm.log b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/golden/fsm.log new file mode 100644 index 000000000..03ef8acfe --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/golden/fsm.log @@ -0,0 +1,130 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 at 2 ns +Display : in_data1 0000 at 4 ns +Display : in_data1 0000 at 5 ns +Display : in_data2 0000 at 7 ns +Display : in_data2 0000 at 8 ns +Display : in_data2 0000 at 9 ns +Display : in_data3 0000 at 11 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 at 18 ns +Display : in_data1 0000 at 20 ns +Display : in_data1 0001 at 21 ns +Display : in_data2 0000 at 23 ns +Display : in_data2 0000 at 24 ns +Display : in_data2 0000 at 25 ns +Display : in_data3 0000 at 27 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 at 34 ns +Display : in_data1 0001 at 36 ns +Display : in_data1 0001 at 37 ns +Display : in_data1 0001 at 38 ns +Display : in_data2 0001 at 40 ns +Display : in_data2 0001 at 41 ns +Display : in_data2 0001 at 42 ns +Display : in_data3 0000 at 44 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 at 50 ns +Display : in_data1 0001 at 52 ns +Display : in_data1 0010 at 53 ns +Display : in_data1 0010 at 54 ns +Display : in_data1 0010 at 55 ns +Display : in_data2 1000 at 57 ns +Display : in_data2 1000 at 58 ns +Display : in_data2 1000 at 59 ns +Display : in_data3 0000 at 61 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 at 66 ns +Display : in_data1 0010 at 68 ns +Display : in_data1 0010 at 69 ns +Display : in_data1 0010 at 70 ns +Display : in_data1 0010 at 71 ns +Display : in_data1 0010 at 72 ns +Display : in_data1 0011 at 73 ns +Display : in_data2 1011 at 75 ns +Display : in_data2 1011 at 76 ns +Display : in_data2 1011 at 77 ns +Display : in_data3 0000 at 79 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 at 82 ns +Display : in_data1 0011 at 84 ns +Display : in_data1 0101 at 85 ns +Display : in_data2 0100 at 87 ns +Display : in_data2 0100 at 88 ns +Display : in_data2 0100 at 89 ns +Display : in_data3 0000 at 91 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 at 98 ns +Display : in_data1 0101 at 100 ns +Display : in_data1 0110 at 101 ns +Display : in_data2 0100 at 103 ns +Display : in_data2 0100 at 104 ns +Display : in_data2 0100 at 105 ns +Display : in_data3 0000 at 107 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 at 114 ns +Display : in_data1 0110 at 116 ns +Display : in_data1 0111 at 117 ns +Display : in_data2 0100 at 119 ns +Display : in_data2 0100 at 120 ns +Display : in_data2 0100 at 121 ns +Display : in_data3 0000 at 123 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 at 130 ns +Display : in_data1 0111 at 132 ns +Display : in_data1 1000 at 133 ns +Display : in_data2 0100 at 135 ns +Display : in_data2 0100 at 136 ns +Display : in_data2 0100 at 137 ns +Display : in_data2 0100 at 138 ns +Display : in_data2 0100 at 139 ns +Display : in_data3 0000 at 141 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 at 146 ns +Display : in_data1 1000 at 148 ns +Display : in_data1 1001 at 149 ns +Display : in_data2 0001 at 151 ns +Display : in_data2 0001 at 152 ns +Display : in_data2 0001 at 153 ns +Display : in_data2 0001 at 154 ns +Display : in_data2 0001 at 155 ns +Display : in_data3 0000 at 157 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 at 162 ns +Display : in_data1 1001 at 164 ns +Display : in_data1 1010 at 165 ns +Display : in_data2 0001 at 167 ns +Display : in_data2 0001 at 168 ns +Display : in_data2 0001 at 169 ns +Display : in_data2 0001 at 170 ns +Display : in_data2 0001 at 171 ns +Display : in_data3 0000 at 173 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 at 178 ns +Display : in_data1 1010 at 180 ns +Display : in_data1 1011 at 181 ns +Display : in_data2 0001 at 183 ns +Display : in_data2 0001 at 184 ns +Display : in_data2 0001 at 185 ns +Display : in_data2 0001 at 186 ns +Display : in_data2 0001 at 187 ns +Display : in_data3 0000 at 189 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 at 194 ns +Display : in_data1 1011 at 196 ns +Display : in_data1 1100 at 197 ns +Display : in_data2 0001 at 199 ns +Display : in_data2 0001 at 200 ns +Display : in_data2 0001 at 201 ns +Display : in_data3 0000 at 203 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 at 210 ns +Display : in_data1 1100 at 212 ns +Display : in_data1 1101 at 213 ns +Display : in_data2 0001 at 215 ns +Display : in_data2 0001 at 216 ns +Display : in_data2 0001 at 217 ns +Display : in_data3 0000 at 219 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 at 226 ns +Display : in_data1 1101 at 228 ns +Display : in_data1 1110 at 229 ns +Display : in_data2 0001 at 231 ns +Display : in_data2 0001 at 232 ns +Display : in_data2 0001 at 233 ns +Display : in_data3 0000 at 235 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 at 242 ns +Display : in_data1 1110 at 244 ns +Display : in_data1 1111 at 245 ns +Display : in_data2 0001 at 247 ns +Display : in_data2 0001 at 248 ns +Display : in_data2 0001 at 249 ns +Display : in_data3 0000 at 251 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/main.cpp new file mode 100644 index 000000000..68aa873e9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/main.cpp @@ -0,0 +1,95 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "fsm.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal<bool> output_valid1; + sc_signal<bool> output_valid2; + sc_signal<bool> output_valid3; + + + fsm fsm1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + input_valid, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + output_valid1, + output_valid2, + output_valid3 + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/stimulus.cpp new file mode 100644 index 000000000..53a319114 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/stimulus.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " << i + << " at " << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(15); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/stimulus.h new file mode 100644 index 000000000..1bc242809 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/stimulus.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/display.cpp new file mode 100644 index 000000000..fc643330d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/display.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << in_data3.read() << " " + << in_data4.read() << " " + << in_data5.read() << " " + << " at " << sc_time_stamp() << endl; + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/display.h new file mode 100644 index 000000000..36001ab41 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/display.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal_bool_vector& in_data3; // Input port + const sc_signal_bool_vector& in_data4; // Input port + const sc_signal<int>& in_data5; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal_bool_vector& IN_DATA3, + const sc_signal_bool_vector& IN_DATA4, + const sc_signal<int>& IN_DATA5, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_data3(IN_DATA3), + in_data4(IN_DATA4), + in_data5(IN_DATA5), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/golden/if_test.log b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/golden/if_test.log new file mode 100644 index 000000000..505f7d8d8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/golden/if_test.log @@ -0,0 +1,35 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 stim4= 0 stim5= 0 2 ns +Display : 0000 0000 0001 0000 0 at 10 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 stim4= 1 stim5= 1 13 ns +Display : 0001 0000 0001 0000 1 at 20 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 stim4= 2 stim5= 2 24 ns +Display : 0001 0000 0010 0010 2 at 31 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 stim4= 3 stim5= 3 35 ns +Display : 0010 0000 0011 0011 3 at 42 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 stim4= 4 stim5= 4 46 ns +Display : 0011 0000 0100 0100 4 at 53 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 stim4= 5 stim5= 5 57 ns +Display : 0101 0000 0101 0101 5 at 64 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 stim4= 6 stim5= 6 68 ns +Display : 0110 0110 0110 0110 0 at 75 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 stim4= 7 stim5= 7 79 ns +Display : 0111 0111 0111 0111 0 at 86 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 stim4= 8 stim5= 8 90 ns +Display : 1000 0000 1000 1000 0 at 97 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 stim4= 9 stim5= 9 101 ns +Display : 1001 0000 1001 1001 0 at 108 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 stim4= 10 stim5= 10 112 ns +Display : 1010 0000 1010 1010 0 at 119 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 stim4= 11 stim5= 11 123 ns +Display : 1011 0000 1011 1011 0 at 130 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 stim4= 12 stim5= 12 134 ns +Display : 1100 0000 1100 1100 0 at 141 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 stim4= 13 stim5= 13 145 ns +Display : 1101 0000 1101 1101 0 at 152 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 stim4= 14 stim5= 14 156 ns +Display : 1110 0000 1110 1110 0 at 163 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 stim4= 15 stim5= 15 167 ns +Display : 1111 0000 1111 1111 0 at 174 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/if_test.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/if_test.cpp new file mode 100644 index 000000000..c728895ed --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/if_test.cpp @@ -0,0 +1,118 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + if_test.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "if_test.h" + +void if_test::entry(){ + + sc_biguint<4> tmp1; + sc_bigint<4> tmp2; + sc_lv<4> tmp3; + sc_bv<4> tmp4; + int tmp5; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_value3.write(0); + out_value4.write(0); + out_value5.write(0); + out_valid.write(false); + wait(); + } else wait(); + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + tmp5 = in_value5.read(); + + //execution + if (tmp1 == 4) { + out_value1.write(3); + } else if (tmp1 == 3) { + out_value1.write(2); + } else if (tmp1 == 2) { + out_value1.write(1); + } else { + out_value1.write(tmp1); + }; + wait(); + + if (tmp2 < 6 ) { + out_value2.write(0); + wait(); + } else { + out_value2.write(tmp2); + wait(); + }; + + if (tmp3 == "0000" ) { + out_value3.write(1); + wait(); + wait(); + } else { + out_value3.write(tmp3); + wait(); + }; + + if (tmp4 != "0001" ) { + out_value4.write(tmp4); + }; + wait(); + + out_value5.write((tmp5>=6)?0:tmp5); + wait(); + + out_valid.write(true); + wait(); + out_valid.write(false); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/if_test.f b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/if_test.f new file mode 100644 index 000000000..3d00cc5c2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/if_test.f @@ -0,0 +1,4 @@ +if_test/if_test.cpp +if_test/display.cpp +if_test/main.cpp +if_test/stimulus.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/if_test.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/if_test.h new file mode 100644 index 000000000..d1ab3341a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/if_test.h @@ -0,0 +1,108 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + if_test.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( if_test ) +{ + SC_HAS_PROCESS( if_test ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1; + const sc_signal_bool_vector& in_value2; + const sc_signal_bool_vector& in_value3; + const sc_signal_bool_vector& in_value4; + const sc_signal<int>& in_value5 ; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal_bool_vector& out_value3; + sc_signal_bool_vector& out_value4; + sc_signal<int>& out_value5; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + if_test( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal<int>& IN_VALUE5, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal_bool_vector& OUT_VALUE3, + sc_signal_bool_vector& OUT_VALUE4, + sc_signal<int>& OUT_VALUE5, + sc_signal<bool>& OUT_VALID // Input port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_value5 (IN_VALUE5), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_value3 (OUT_VALUE3), + out_value4 (OUT_VALUE4), + out_value5 (OUT_VALUE5), + out_valid (OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + + // + + void entry (); + +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/main.cpp new file mode 100644 index 000000000..bfad98b86 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/main.cpp @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "if_test.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal_bool_vector stim4; + sc_signal<int> stim5; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal_bool_vector result3; + sc_signal_bool_vector result4; + sc_signal<int> result5; + sc_signal<bool> output_valid; + + + + if_test if_test1 ( "process_body", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + stim5, + input_valid, + result1, + result2, + result3, + result4, + result5, + output_valid + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + stim5, + input_valid); + + display display1 ("display", + clock, + result1, + result2, + result3, + result4, + result5, + output_valid); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/stimulus.cpp new file mode 100644 index 000000000..f45313792 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/stimulus.cpp @@ -0,0 +1,73 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + stim4.write(0); + stim5.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + stim4.write(i); + stim5.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " + << i << " stim4= " << i << " stim5= " << i << " " + << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(10); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/stimulus.h new file mode 100644 index 000000000..813c53e1b --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/if_test/stimulus.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal_bool_vector& stim4; + sc_signal<int>& stim5; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal_bool_vector& STIM4, + sc_signal<int>& STIM5, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + stim4(STIM4), + stim5(STIM5), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/common.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/common.h new file mode 100644 index 000000000..2a4edbad5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/common.h @@ -0,0 +1,45 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<4> > sc_signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/display.cpp new file mode 100644 index 000000000..b0ac27b0c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/display.cpp @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + int i = 0; + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (in_valid.read()==false) wait(); + cout << "Display : " << in_data1.read() << " " + << in_data2.read() << " " + << " at " << sc_time_stamp() << endl; + i++; + if(i == 24) sc_stop(); + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/display.h new file mode 100644 index 000000000..ea15269eb --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/display.h @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal_bool_vector& in_data1; // Input port + const sc_signal_bool_vector& in_data2; // Input port + const sc_signal<bool>& in_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal_bool_vector& IN_DATA1, + const sc_signal_bool_vector& IN_DATA2, + const sc_signal<bool>& IN_VALID + ) + : + in_data1(IN_DATA1), + in_data2(IN_DATA2), + in_valid(IN_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/golden/inlining.log b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/golden/inlining.log new file mode 100644 index 000000000..b5ed181e7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/golden/inlining.log @@ -0,0 +1,67 @@ +SystemC Simulation +Stimuli: stim1= 0 stim2= 0 stim3= 0 stim4= 0 2 ns +tmp1 my print 1 +tmp2 my print 0 +Display : 0001 0000 at 5 ns +Stimuli: stim1= 1 stim2= 1 stim3= 1 stim4= 1 13 ns +tmp1 my print 2 +tmp2 my print 1 +Display : 0010 0001 at 16 ns +Stimuli: stim1= 2 stim2= 2 stim3= 2 stim4= 2 24 ns +tmp1 my print 3 +tmp2 my print 2 +Display : 0011 0010 at 27 ns +Stimuli: stim1= 3 stim2= 3 stim3= 3 stim4= 3 35 ns +tmp1 my print 4 +tmp2 my print 3 +Display : 0100 0011 at 38 ns +Stimuli: stim1= 4 stim2= 4 stim3= 4 stim4= 4 46 ns +tmp1 my print 5 +tmp2 my print 4 +Display : 0101 0100 at 49 ns +Stimuli: stim1= 5 stim2= 5 stim3= 5 stim4= 5 57 ns +tmp1 my print 6 +tmp2 my print 5 +Display : 0110 0101 at 60 ns +Stimuli: stim1= 6 stim2= 6 stim3= 6 stim4= 6 68 ns +tmp1 my print 7 +tmp2 my print 6 +Display : 0111 0110 at 71 ns +Stimuli: stim1= 7 stim2= 7 stim3= 7 stim4= 7 79 ns +tmp1 my print 8 +tmp2 my print 7 +Display : 1000 0111 at 82 ns +Stimuli: stim1= 8 stim2= 8 stim3= 8 stim4= 8 90 ns +tmp1 my print 9 +tmp2 my print 8 +Display : 1001 1000 at 93 ns +Stimuli: stim1= 9 stim2= 9 stim3= 9 stim4= 9 101 ns +tmp1 my print 10 +tmp2 my print 9 +Display : 1010 1001 at 104 ns +Stimuli: stim1= 10 stim2= 10 stim3= 10 stim4= 10 112 ns +tmp1 my print 11 +tmp2 my print 10 +Display : 1011 1010 at 115 ns +Stimuli: stim1= 11 stim2= 11 stim3= 11 stim4= 11 123 ns +tmp1 my print 12 +tmp2 my print 11 +Display : 1100 1011 at 126 ns +Stimuli: stim1= 12 stim2= 12 stim3= 12 stim4= 12 134 ns +tmp1 my print 13 +tmp2 my print 12 +Display : 1101 1100 at 137 ns +Stimuli: stim1= 13 stim2= 13 stim3= 13 stim4= 13 145 ns +tmp1 my print 14 +tmp2 my print 13 +Display : 1110 1101 at 148 ns +Stimuli: stim1= 14 stim2= 14 stim3= 14 stim4= 14 156 ns +tmp1 my print 15 +tmp2 my print 14 +Display : 1111 1110 at 159 ns +Stimuli: stim1= 15 stim2= 15 stim3= 15 stim4= 15 167 ns +tmp1 my print 0 +tmp2 my print 15 +Display : 1111 1111 at 170 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/inlining.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/inlining.cpp new file mode 100644 index 000000000..232c6a8e2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/inlining.cpp @@ -0,0 +1,96 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + inlining.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "inlining.h" + +// list of defines +// #define MAXI(a,b) ((a)>(b)?(a):(b)) +#define MAXI(a,b) ( (a) > (b) ? sc_biguint<4>( a ) : sc_biguint<4>( b ) ) +#define clockedge wait() +#define my_print(a) cout << #a << " my print " << a << endl +#define my_if(a, b, c) if (a < 6 ) { \ + b = 0; \ + } else { \ + b = c; \ + }; + +void inlining::entry(){ + + sc_biguint<4> tmp1; + sc_biguint<4> tmp2; + sc_lv<4> tmp3; + sc_bv<4> tmp4; + + // reset_loop + if (reset.read() == true) { + out_value1.write(0); + out_value2.write(0); + out_valid.write(false); + clockedge; + } else clockedge; + + // + // main loop + // + while(1) { + do { wait(); } while (in_valid == false); + + //reading inputs + tmp1 = in_value1.read(); + tmp2 = in_value2.read(); + tmp3 = in_value3.read(); + tmp4 = in_value4.read(); + + //execution + ++tmp1; + out_value1.write(MAXI(tmp1, tmp2)); + my_print(tmp1); + my_print(tmp2); + clockedge; + + my_if(tmp2, tmp3, tmp4); + out_value2.write(tmp4); + out_valid.write(true); + clockedge; + out_valid.write(false); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/inlining.f b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/inlining.f new file mode 100644 index 000000000..4c51c0531 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/inlining.f @@ -0,0 +1,4 @@ +inlining/main.cpp +inlining/stimulus.cpp +inlining/display.cpp +inlining/inlining.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/inlining.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/inlining.h new file mode 100644 index 000000000..457fd7048 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/inlining.h @@ -0,0 +1,93 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + inlining.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( inlining ) +{ + SC_HAS_PROCESS( inlining ); + + sc_in_clk clk; + + const sc_signal<bool>& reset ; + const sc_signal_bool_vector& in_value1 ; + const sc_signal_bool_vector& in_value2 ; + const sc_signal_bool_vector& in_value3 ; + const sc_signal_bool_vector& in_value4 ; + const sc_signal<bool>& in_valid; + sc_signal_bool_vector& out_value1; + sc_signal_bool_vector& out_value2; + sc_signal<bool>& out_valid; + + // + // Constructor + // + + inlining( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal_bool_vector& IN_VALUE1, + const sc_signal_bool_vector& IN_VALUE2, + const sc_signal_bool_vector& IN_VALUE3, + const sc_signal_bool_vector& IN_VALUE4, + const sc_signal<bool>& IN_VALID, // Input port + sc_signal_bool_vector& OUT_VALUE1, + sc_signal_bool_vector& OUT_VALUE2, + sc_signal<bool>& OUT_VALID // Input port + ) + : + reset (RESET), + in_value1 (IN_VALUE1), + in_value2 (IN_VALUE2), + in_value3 (IN_VALUE3), + in_value4 (IN_VALUE4), + in_valid (IN_VALID), + out_value1 (OUT_VALUE1), + out_value2 (OUT_VALUE2), + out_valid (OUT_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + // + void entry (); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/main.cpp new file mode 100644 index 000000000..89a428293 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/main.cpp @@ -0,0 +1,92 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "inlining.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal_bool_vector stim1; + sc_signal_bool_vector stim2; + sc_signal_bool_vector stim3; + sc_signal_bool_vector stim4; + sc_signal<bool> input_valid; + sc_signal_bool_vector result1; + sc_signal_bool_vector result2; + sc_signal<bool> output_valid; + + + + inlining inlining1 ( + "process_body", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid, + result1, + result2, + output_valid + ); + + stimulus stimulus1 ("stimulus", + clock, + reset, + stim1, + stim2, + stim3, + stim4, + input_valid + ); + + display display1 ("display", + clock, + result1, + result2, + output_valid + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/stimulus.cpp new file mode 100644 index 000000000..2e897dacc --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/stimulus.cpp @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + +int i; + + // sending some reset values + reset.write(true); + stim1.write(0); + stim2.write(0); + stim3.write(0); + stim4.write(0); + wait(); + reset.write(false); + wait(); + for (i=0; i<= 15; i++) { + stim1.write(i); + stim2.write(i); + stim3.write(i); + stim4.write(i); + input_valid.write(true); + cout << "Stimuli: stim1= " << i << " stim2= " << i << " stim3= " + << i << " stim4= " << i << " " + << sc_time_stamp() << endl; + wait(); + input_valid.write(false); + wait(10); + } + + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/stimulus.h new file mode 100644 index 000000000..a82afff4c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/stimulus.h @@ -0,0 +1,78 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "common.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal_bool_vector& stim1; + sc_signal_bool_vector& stim2; + sc_signal_bool_vector& stim3; + sc_signal_bool_vector& stim4; + sc_signal<bool>& input_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal_bool_vector& STIM1, + sc_signal_bool_vector& STIM2, + sc_signal_bool_vector& STIM3, + sc_signal_bool_vector& STIM4, + sc_signal<bool>& INPUT_VALID + ) + : + reset(RESET), + stim1(STIM1), + stim2(STIM2), + stim3(STIM3), + stim4(STIM4), + input_valid(INPUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/display.cpp new file mode 100644 index 000000000..336edf69c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/display.cpp @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up. + while (out_valid.read()==false) wait(); + cout << "Display : " << result.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/display.h new file mode 100644 index 000000000..e858eb226 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/display.h @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& result; // Input port + const sc_signal<bool>& out_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& RESULT, + const sc_signal<bool>& OUT_VALID + ) + : + result(RESULT), + out_valid(OUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/for_datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/for_datatypes.cpp new file mode 100644 index 000000000..668c4ee95 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/for_datatypes.cpp @@ -0,0 +1,99 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + for_datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "for_datatypes.h" + +#define max 10 + +void for_datatypes::entry() +{ + + int i; + sc_signed counter_signed(8); + sc_unsigned counter_unsigned(8); + + // reset_loop + if (reset.read()==true) { + result.write(0); + out_valid.write(false); + wait(); + } else wait(); + + //---------- + // main loop + //---------- + while(1) { + + //read inputs + while (in_valid.read()==false) wait(); + + //execution of for loop with integer counter + out_valid.write(true); + wait(); + for (i=1; i<=max; i++) { + result.write(in_value.read()); + wait(); + }; + out_valid.write(false); + wait(4); + + //execution of for loop with signed counter + out_valid.write(true); + wait(); + for (counter_signed=1; counter_signed.to_int()<=max; counter_signed++) { + result.write(in_value.read()); + wait(); + }; + out_valid.write(false); + wait(4); + + //execution of for loop with unsinged counter + out_valid.write(true); + wait(); + for (counter_unsigned=1; counter_unsigned.to_uint()<=max; counter_unsigned++) { + result.write(in_value.read()); + wait(); + }; + out_valid.write(false); + wait(); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/for_datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/for_datatypes.f new file mode 100644 index 000000000..127102844 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/for_datatypes.f @@ -0,0 +1,4 @@ +for_datatypes/stimulus.cpp +for_datatypes/main.cpp +for_datatypes/display.cpp +for_datatypes/for_datatypes.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/for_datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/for_datatypes.h new file mode 100644 index 000000000..dcacddfff --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/for_datatypes.h @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + for_datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( for_datatypes ) +{ + SC_HAS_PROCESS( for_datatypes ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<bool>& in_valid; + const sc_signal<int>& in_value; + sc_signal<bool>& out_valid; + sc_signal<int>& result; + + for_datatypes ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<bool>& IN_VALID, + const sc_signal<int>& IN_VALUE, + sc_signal<bool>& OUT_VALID, + sc_signal<int>& RESULT + ) + : + reset (RESET), + in_valid (IN_VALID), + in_value (IN_VALUE), + out_valid (OUT_VALID), + result (RESULT) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + void entry (); +}; diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/golden/for_datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/golden/for_datatypes.log new file mode 100644 index 000000000..4fb0720f2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/golden/for_datatypes.log @@ -0,0 +1,201 @@ +SystemC Simulation +Stimuli1 : in_valid = true in_value 0 at 6 ns +Stimuli1 : in_valid = true in_value 1 at 7 ns +Stimuli1 : in_valid = true in_value 2 at 8 ns +Display : 0 at 8 ns +Stimuli1 : in_valid = true in_value 3 at 9 ns +Display : 1 at 9 ns +Stimuli1 : in_valid = true in_value 4 at 10 ns +Display : 2 at 10 ns +Stimuli1 : in_valid = true in_value 5 at 11 ns +Display : 3 at 11 ns +Stimuli1 : in_valid = true in_value 6 at 12 ns +Display : 4 at 12 ns +Stimuli1 : in_valid = true in_value 7 at 13 ns +Display : 5 at 13 ns +Stimuli1 : in_valid = true in_value 8 at 14 ns +Display : 6 at 14 ns +Stimuli1 : in_valid = true in_value 9 at 15 ns +Display : 7 at 15 ns +Stimuli1 : in_valid = true in_value 10 at 16 ns +Display : 8 at 16 ns +Display : 9 at 17 ns +Display : 10 at 18 ns +Stimuli2 : in_valid = true in_value 0 at 21 ns +Stimuli2 : in_valid = true in_value 1 at 22 ns +Stimuli2 : in_valid = true in_value 2 at 23 ns +Display : 10 at 23 ns +Stimuli2 : in_valid = true in_value 3 at 24 ns +Display : 1 at 24 ns +Stimuli2 : in_valid = true in_value 4 at 25 ns +Display : 2 at 25 ns +Stimuli2 : in_valid = true in_value 5 at 26 ns +Display : 3 at 26 ns +Stimuli2 : in_valid = true in_value 6 at 27 ns +Display : 4 at 27 ns +Stimuli2 : in_valid = true in_value 7 at 28 ns +Display : 5 at 28 ns +Stimuli2 : in_valid = true in_value 8 at 29 ns +Display : 6 at 29 ns +Stimuli2 : in_valid = true in_value 9 at 30 ns +Display : 7 at 30 ns +Stimuli2 : in_valid = true in_value 10 at 31 ns +Display : 8 at 31 ns +Display : 9 at 32 ns +Display : 10 at 33 ns +Stimuli3 : in_valid = true in_value 0 at 36 ns +Stimuli3 : in_valid = true in_value 1 at 37 ns +Stimuli3 : in_valid = true in_value 2 at 38 ns +Display : 10 at 38 ns +Stimuli3 : in_valid = true in_value 3 at 39 ns +Display : 1 at 39 ns +Stimuli3 : in_valid = true in_value 4 at 40 ns +Display : 2 at 40 ns +Stimuli3 : in_valid = true in_value 5 at 41 ns +Display : 3 at 41 ns +Stimuli3 : in_valid = true in_value 6 at 42 ns +Display : 4 at 42 ns +Stimuli3 : in_valid = true in_value 7 at 43 ns +Display : 5 at 43 ns +Stimuli3 : in_valid = true in_value 8 at 44 ns +Display : 6 at 44 ns +Stimuli3 : in_valid = true in_value 9 at 45 ns +Display : 7 at 45 ns +Stimuli3 : in_valid = true in_value 10 at 46 ns +Display : 8 at 46 ns +Display : 9 at 47 ns +Display : 10 at 48 ns +Stimuli1 : in_valid = true in_value 0 at 57 ns +Stimuli1 : in_valid = true in_value 1 at 58 ns +Stimuli1 : in_valid = true in_value 2 at 59 ns +Display : 10 at 59 ns +Stimuli1 : in_valid = true in_value 3 at 60 ns +Display : 1 at 60 ns +Stimuli1 : in_valid = true in_value 4 at 61 ns +Display : 2 at 61 ns +Stimuli1 : in_valid = true in_value 5 at 62 ns +Display : 3 at 62 ns +Stimuli1 : in_valid = true in_value 6 at 63 ns +Display : 4 at 63 ns +Stimuli1 : in_valid = true in_value 7 at 64 ns +Display : 5 at 64 ns +Stimuli1 : in_valid = true in_value 8 at 65 ns +Display : 6 at 65 ns +Stimuli1 : in_valid = true in_value 9 at 66 ns +Display : 7 at 66 ns +Stimuli1 : in_valid = true in_value 10 at 67 ns +Display : 8 at 67 ns +Display : 9 at 68 ns +Display : 10 at 69 ns +Stimuli2 : in_valid = true in_value 0 at 72 ns +Stimuli2 : in_valid = true in_value 1 at 73 ns +Stimuli2 : in_valid = true in_value 2 at 74 ns +Display : 10 at 74 ns +Stimuli2 : in_valid = true in_value 3 at 75 ns +Display : 1 at 75 ns +Stimuli2 : in_valid = true in_value 4 at 76 ns +Display : 2 at 76 ns +Stimuli2 : in_valid = true in_value 5 at 77 ns +Display : 3 at 77 ns +Stimuli2 : in_valid = true in_value 6 at 78 ns +Display : 4 at 78 ns +Stimuli2 : in_valid = true in_value 7 at 79 ns +Display : 5 at 79 ns +Stimuli2 : in_valid = true in_value 8 at 80 ns +Display : 6 at 80 ns +Stimuli2 : in_valid = true in_value 9 at 81 ns +Display : 7 at 81 ns +Stimuli2 : in_valid = true in_value 10 at 82 ns +Display : 8 at 82 ns +Display : 9 at 83 ns +Display : 10 at 84 ns +Stimuli3 : in_valid = true in_value 0 at 87 ns +Stimuli3 : in_valid = true in_value 1 at 88 ns +Stimuli3 : in_valid = true in_value 2 at 89 ns +Display : 10 at 89 ns +Stimuli3 : in_valid = true in_value 3 at 90 ns +Display : 1 at 90 ns +Stimuli3 : in_valid = true in_value 4 at 91 ns +Display : 2 at 91 ns +Stimuli3 : in_valid = true in_value 5 at 92 ns +Display : 3 at 92 ns +Stimuli3 : in_valid = true in_value 6 at 93 ns +Display : 4 at 93 ns +Stimuli3 : in_valid = true in_value 7 at 94 ns +Display : 5 at 94 ns +Stimuli3 : in_valid = true in_value 8 at 95 ns +Display : 6 at 95 ns +Stimuli3 : in_valid = true in_value 9 at 96 ns +Display : 7 at 96 ns +Stimuli3 : in_valid = true in_value 10 at 97 ns +Display : 8 at 97 ns +Display : 9 at 98 ns +Display : 10 at 99 ns +Stimuli1 : in_valid = true in_value 0 at 108 ns +Stimuli1 : in_valid = true in_value 1 at 109 ns +Stimuli1 : in_valid = true in_value 2 at 110 ns +Display : 10 at 110 ns +Stimuli1 : in_valid = true in_value 3 at 111 ns +Display : 1 at 111 ns +Stimuli1 : in_valid = true in_value 4 at 112 ns +Display : 2 at 112 ns +Stimuli1 : in_valid = true in_value 5 at 113 ns +Display : 3 at 113 ns +Stimuli1 : in_valid = true in_value 6 at 114 ns +Display : 4 at 114 ns +Stimuli1 : in_valid = true in_value 7 at 115 ns +Display : 5 at 115 ns +Stimuli1 : in_valid = true in_value 8 at 116 ns +Display : 6 at 116 ns +Stimuli1 : in_valid = true in_value 9 at 117 ns +Display : 7 at 117 ns +Stimuli1 : in_valid = true in_value 10 at 118 ns +Display : 8 at 118 ns +Display : 9 at 119 ns +Display : 10 at 120 ns +Stimuli2 : in_valid = true in_value 0 at 123 ns +Stimuli2 : in_valid = true in_value 1 at 124 ns +Stimuli2 : in_valid = true in_value 2 at 125 ns +Display : 10 at 125 ns +Stimuli2 : in_valid = true in_value 3 at 126 ns +Display : 1 at 126 ns +Stimuli2 : in_valid = true in_value 4 at 127 ns +Display : 2 at 127 ns +Stimuli2 : in_valid = true in_value 5 at 128 ns +Display : 3 at 128 ns +Stimuli2 : in_valid = true in_value 6 at 129 ns +Display : 4 at 129 ns +Stimuli2 : in_valid = true in_value 7 at 130 ns +Display : 5 at 130 ns +Stimuli2 : in_valid = true in_value 8 at 131 ns +Display : 6 at 131 ns +Stimuli2 : in_valid = true in_value 9 at 132 ns +Display : 7 at 132 ns +Stimuli2 : in_valid = true in_value 10 at 133 ns +Display : 8 at 133 ns +Display : 9 at 134 ns +Display : 10 at 135 ns +Stimuli3 : in_valid = true in_value 0 at 138 ns +Stimuli3 : in_valid = true in_value 1 at 139 ns +Stimuli3 : in_valid = true in_value 2 at 140 ns +Display : 10 at 140 ns +Stimuli3 : in_valid = true in_value 3 at 141 ns +Display : 1 at 141 ns +Stimuli3 : in_valid = true in_value 4 at 142 ns +Display : 2 at 142 ns +Stimuli3 : in_valid = true in_value 5 at 143 ns +Display : 3 at 143 ns +Stimuli3 : in_valid = true in_value 6 at 144 ns +Display : 4 at 144 ns +Stimuli3 : in_valid = true in_value 7 at 145 ns +Display : 5 at 145 ns +Stimuli3 : in_valid = true in_value 8 at 146 ns +Display : 6 at 146 ns +Stimuli3 : in_valid = true in_value 9 at 147 ns +Display : 7 at 147 ns +Stimuli3 : in_valid = true in_value 10 at 148 ns +Display : 8 at 148 ns +Display : 9 at 149 ns +Display : 10 at 150 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/main.cpp new file mode 100644 index 000000000..a306ccd47 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/main.cpp @@ -0,0 +1,82 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "for_datatypes.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<bool> out_valid; + sc_signal<bool> in_valid; + sc_signal<int> result; + sc_signal<int> in_value; + + + for_datatypes for_datatypes1 ( + "process_body", + clock, + reset, + in_valid, + in_value, + out_valid, + result + ); + + stimulus stimulus1 ( + "stimulus", + clock, + reset, + in_value, + in_valid + ); + + display display1 ( + "display", + clock, + result, + out_valid + ); + + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/stimulus.cpp new file mode 100644 index 000000000..af5159663 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/stimulus.cpp @@ -0,0 +1,83 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + int i, j; + + // sending some reset values + reset.write(true); + in_valid.write(false); + in_value.write(0); + wait(); + reset.write(false); + wait(5); + for(i=0; i<3; i++){ + in_valid.write(true); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli1 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(4); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli2 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(4); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli3 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + wait(10); + }; + + wait(15); + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/stimulus.h new file mode 100644 index 000000000..e20114c36 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_datatypes/stimulus.h @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& in_value; + sc_signal<bool>& in_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& IN_VALUE, + sc_signal<bool>& IN_VALID + ) + : + reset (RESET), + in_value (IN_VALUE), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/display.cpp new file mode 100644 index 000000000..05c349065 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up. + while (out_valid.read()==false) wait(); + cout << "Display : " << result.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/display.h new file mode 100644 index 000000000..e858eb226 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/display.h @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-22 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& result; // Input port + const sc_signal<bool>& out_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& RESULT, + const sc_signal<bool>& OUT_VALID + ) + : + result(RESULT), + out_valid(OUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/for_exit.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/for_exit.cpp new file mode 100644 index 000000000..db3ac2bb9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/for_exit.cpp @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + for_exit.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "for_exit.h" + +#define max 10 + +void for_exit::entry() +{ + + int i, inp_tmp; + + // reset_loop + if (reset.read()==true) { + result.write(0); + out_valid.write(false); + wait(); + } else wait(); + + //---------- + // main loop + //---------- + while(1) { + + // read inputs + while (in_valid.read()==false) wait(); + + // execution of for loop with continues + out_valid.write(true); + wait(); + for (i=1; i<=max; i++) { + inp_tmp = in_value.read(); + if (i==8) { + wait(); + continue; + } else if (inp_tmp<5 && i!=1) { + wait(); + continue; + } else { + result.write(inp_tmp); + wait(); + }; + }; + out_valid.write(false); + wait(5); + + // for loop with break + out_valid.write(true); + wait(); + for (i=1; i<=max; i++) { + inp_tmp = in_value.read(); + if (inp_tmp==7) { + wait(); + break; + } else { + result.write(inp_tmp); + wait(); + } + }; + out_valid.write(false); + wait(); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/for_exit.f b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/for_exit.f new file mode 100644 index 000000000..b1509dea5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/for_exit.f @@ -0,0 +1,4 @@ +for_exit/main.cpp +for_exit/stimulus.cpp +for_exit/display.cpp +for_exit/for_exit.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/for_exit.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/for_exit.h new file mode 100644 index 000000000..8d2de9783 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/for_exit.h @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + for_exit.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( for_exit ) +{ + SC_HAS_PROCESS( for_exit ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<bool>& in_valid; + const sc_signal<int>& in_value; + sc_signal<bool>& out_valid; + sc_signal<int>& result; + + for_exit( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<bool>& IN_VALID, + const sc_signal<int>& IN_VALUE, + sc_signal<bool>& OUT_VALID, + sc_signal<int>& RESULT + ) + : + reset (RESET), + in_valid (IN_VALID), + in_value (IN_VALUE), + out_valid (OUT_VALID), + result (RESULT) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + void entry (); +}; diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/golden/for_exit.log b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/golden/for_exit.log new file mode 100644 index 000000000..a7037c4e5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/golden/for_exit.log @@ -0,0 +1,123 @@ +SystemC Simulation +Stimuli1 : in_valid = true in_value 0 at 6 ns +Stimuli1 : in_valid = true in_value 1 at 7 ns +Stimuli1 : in_valid = true in_value 2 at 8 ns +Display : 0 at 8 ns +Stimuli1 : in_valid = true in_value 3 at 9 ns +Display : 1 at 9 ns +Stimuli1 : in_valid = true in_value 4 at 10 ns +Display : 1 at 10 ns +Stimuli1 : in_valid = true in_value 5 at 11 ns +Display : 1 at 11 ns +Stimuli1 : in_valid = true in_value 6 at 12 ns +Display : 1 at 12 ns +Stimuli1 : in_valid = true in_value 7 at 13 ns +Display : 5 at 13 ns +Stimuli1 : in_valid = true in_value 8 at 14 ns +Display : 6 at 14 ns +Stimuli1 : in_valid = true in_value 9 at 15 ns +Display : 7 at 15 ns +Stimuli1 : in_valid = true in_value 10 at 16 ns +Display : 7 at 16 ns +Display : 9 at 17 ns +Display : 10 at 18 ns +Stimuli2 : in_valid = true in_value 0 at 21 ns +Stimuli2 : in_valid = true in_value 1 at 22 ns +Stimuli2 : in_valid = true in_value 2 at 23 ns +Stimuli2 : in_valid = true in_value 3 at 24 ns +Display : 10 at 24 ns +Stimuli2 : in_valid = true in_value 4 at 25 ns +Display : 2 at 25 ns +Stimuli2 : in_valid = true in_value 5 at 26 ns +Display : 3 at 26 ns +Stimuli2 : in_valid = true in_value 6 at 27 ns +Display : 4 at 27 ns +Stimuli2 : in_valid = true in_value 7 at 28 ns +Display : 5 at 28 ns +Stimuli2 : in_valid = true in_value 8 at 29 ns +Display : 6 at 29 ns +Stimuli2 : in_valid = true in_value 9 at 30 ns +Display : 6 at 30 ns +Stimuli2 : in_valid = true in_value 10 at 31 ns +Stimuli1 : in_valid = true in_value 0 at 42 ns +Stimuli1 : in_valid = true in_value 1 at 43 ns +Stimuli1 : in_valid = true in_value 2 at 44 ns +Display : 6 at 44 ns +Stimuli1 : in_valid = true in_value 3 at 45 ns +Display : 1 at 45 ns +Stimuli1 : in_valid = true in_value 4 at 46 ns +Display : 1 at 46 ns +Stimuli1 : in_valid = true in_value 5 at 47 ns +Display : 1 at 47 ns +Stimuli1 : in_valid = true in_value 6 at 48 ns +Display : 1 at 48 ns +Stimuli1 : in_valid = true in_value 7 at 49 ns +Display : 5 at 49 ns +Stimuli1 : in_valid = true in_value 8 at 50 ns +Display : 6 at 50 ns +Stimuli1 : in_valid = true in_value 9 at 51 ns +Display : 7 at 51 ns +Stimuli1 : in_valid = true in_value 10 at 52 ns +Display : 7 at 52 ns +Display : 9 at 53 ns +Display : 10 at 54 ns +Stimuli2 : in_valid = true in_value 0 at 57 ns +Stimuli2 : in_valid = true in_value 1 at 58 ns +Stimuli2 : in_valid = true in_value 2 at 59 ns +Stimuli2 : in_valid = true in_value 3 at 60 ns +Display : 10 at 60 ns +Stimuli2 : in_valid = true in_value 4 at 61 ns +Display : 2 at 61 ns +Stimuli2 : in_valid = true in_value 5 at 62 ns +Display : 3 at 62 ns +Stimuli2 : in_valid = true in_value 6 at 63 ns +Display : 4 at 63 ns +Stimuli2 : in_valid = true in_value 7 at 64 ns +Display : 5 at 64 ns +Stimuli2 : in_valid = true in_value 8 at 65 ns +Display : 6 at 65 ns +Stimuli2 : in_valid = true in_value 9 at 66 ns +Display : 6 at 66 ns +Stimuli2 : in_valid = true in_value 10 at 67 ns +Stimuli1 : in_valid = true in_value 0 at 78 ns +Stimuli1 : in_valid = true in_value 1 at 79 ns +Stimuli1 : in_valid = true in_value 2 at 80 ns +Display : 6 at 80 ns +Stimuli1 : in_valid = true in_value 3 at 81 ns +Display : 1 at 81 ns +Stimuli1 : in_valid = true in_value 4 at 82 ns +Display : 1 at 82 ns +Stimuli1 : in_valid = true in_value 5 at 83 ns +Display : 1 at 83 ns +Stimuli1 : in_valid = true in_value 6 at 84 ns +Display : 1 at 84 ns +Stimuli1 : in_valid = true in_value 7 at 85 ns +Display : 5 at 85 ns +Stimuli1 : in_valid = true in_value 8 at 86 ns +Display : 6 at 86 ns +Stimuli1 : in_valid = true in_value 9 at 87 ns +Display : 7 at 87 ns +Stimuli1 : in_valid = true in_value 10 at 88 ns +Display : 7 at 88 ns +Display : 9 at 89 ns +Display : 10 at 90 ns +Stimuli2 : in_valid = true in_value 0 at 93 ns +Stimuli2 : in_valid = true in_value 1 at 94 ns +Stimuli2 : in_valid = true in_value 2 at 95 ns +Stimuli2 : in_valid = true in_value 3 at 96 ns +Display : 10 at 96 ns +Stimuli2 : in_valid = true in_value 4 at 97 ns +Display : 2 at 97 ns +Stimuli2 : in_valid = true in_value 5 at 98 ns +Display : 3 at 98 ns +Stimuli2 : in_valid = true in_value 6 at 99 ns +Display : 4 at 99 ns +Stimuli2 : in_valid = true in_value 7 at 100 ns +Display : 5 at 100 ns +Stimuli2 : in_valid = true in_value 8 at 101 ns +Display : 6 at 101 ns +Stimuli2 : in_valid = true in_value 9 at 102 ns +Display : 6 at 102 ns +Stimuli2 : in_valid = true in_value 10 at 103 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/main.cpp new file mode 100644 index 000000000..b560aab5e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/main.cpp @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "for_exit.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<bool> out_valid; + sc_signal<int> in_value; + sc_signal<bool> in_valid; + sc_signal<int> result; + + + for_exit for_exit1 ( + "process_body", + clock, + reset, + in_valid, + in_value, + out_valid, + result + ); + + stimulus stimulus1 ( + "stimulus", + clock, + reset, + in_value, + in_valid + ); + + display display1 ( + "display", + clock, + result, + out_valid + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/stimulus.cpp new file mode 100644 index 000000000..d45342c41 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/stimulus.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + int i, j; + + // sending some reset values + reset.write(true); + in_valid.write(false); + in_value.write(0); + wait(); + reset.write(false); + wait(5); + for(i=0; i<3; i++){ + in_valid.write(true); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli1 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(4); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli2 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + wait(10); + }; + + wait(15); + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/stimulus.h new file mode 100644 index 000000000..d8bccb0f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_exit/stimulus.h @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& in_value; + sc_signal<bool>& in_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& IN_VALUE, + sc_signal<bool>& IN_VALID + ) + : + reset (RESET), + in_value (IN_VALUE), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/display.cpp new file mode 100644 index 000000000..05c349065 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/display.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up. + while (out_valid.read()==false) wait(); + cout << "Display : " << result.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/display.h new file mode 100644 index 000000000..b50f526c0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/display.h @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& result; // Input port + const sc_signal<bool>& out_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& RESULT, + const sc_signal<bool>& OUT_VALID + ) + : + result(RESULT), + out_valid(OUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/for_fsm.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/for_fsm.cpp new file mode 100644 index 000000000..51836042c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/for_fsm.cpp @@ -0,0 +1,113 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + for_fsm.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "for_fsm.h" + +#define max 10 + +void for_fsm::entry() +{ + + int i, inp_tmp; + + // reset_loop + if (reset.read()==true) { + result.write(0); + out_valid.write(false); + wait(); + } else wait(); + + //---------- + // main loop + //---------- + while(1) { + + // read inputs + while (in_valid.read()==false) wait(); + + // execution of for loop + out_valid.write(true); + wait(); + for (i=1; i<=max; i++) { + inp_tmp = in_value.read(); + result.write(inp_tmp); + wait(); + }; + out_valid.write(false); + wait(5); + + // execution of for loop with continues + out_valid.write(true); + wait(); + for (i=1; i<=max; i++) { + inp_tmp = in_value.read(); + if (i==8) { + wait(); + continue; + } else if (inp_tmp<5 && i!=1) { + wait(); + continue; + } else { + result.write(inp_tmp); + wait(); + }; + }; + out_valid.write(false); + wait(5); + + // for loop with break + out_valid.write(true); + wait(); + for (i=1; i<=max; i++) { + inp_tmp = in_value.read(); + if (inp_tmp==7) { + wait(); + break; + } else { + result.write(inp_tmp); + wait(); + }; + }; + out_valid.write(false); + wait(); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/for_fsm.f b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/for_fsm.f new file mode 100644 index 000000000..d1a3ca297 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/for_fsm.f @@ -0,0 +1,4 @@ +for_fsm/main.cpp +for_fsm/stimulus.cpp +for_fsm/display.cpp +for_fsm/for_fsm.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/for_fsm.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/for_fsm.h new file mode 100644 index 000000000..790e686eb --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/for_fsm.h @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + for_fsm.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( for_fsm ) +{ + SC_HAS_PROCESS( for_fsm ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<bool>& in_valid; + const sc_signal<int>& in_value; + sc_signal<bool>& out_valid; + sc_signal<int>& result; + + for_fsm( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<bool>& IN_VALID, + const sc_signal<int>& IN_VALUE, + sc_signal<bool>& OUT_VALID, + sc_signal<int>& RESULT + ) + : + reset (RESET), + in_valid (IN_VALID), + in_value (IN_VALUE), + out_valid (OUT_VALID), + result (RESULT) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + void entry (); +}; diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/golden/for_fsm.log b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/golden/for_fsm.log new file mode 100644 index 000000000..3e6064ab7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/golden/for_fsm.log @@ -0,0 +1,180 @@ +SystemC Simulation +Stimuli1 : in_valid = true in_value 1 at 6 ns +Stimuli1 : in_valid = true in_value 2 at 7 ns +Stimuli1 : in_valid = true in_value 3 at 8 ns +Display : 0 at 8 ns +Stimuli1 : in_valid = true in_value 4 at 9 ns +Display : 2 at 9 ns +Stimuli1 : in_valid = true in_value 5 at 10 ns +Display : 3 at 10 ns +Stimuli1 : in_valid = true in_value 6 at 11 ns +Display : 4 at 11 ns +Stimuli1 : in_valid = true in_value 7 at 12 ns +Display : 5 at 12 ns +Stimuli1 : in_valid = true in_value 8 at 13 ns +Display : 6 at 13 ns +Stimuli1 : in_valid = true in_value 9 at 14 ns +Display : 7 at 14 ns +Stimuli1 : in_valid = true in_value 10 at 15 ns +Display : 8 at 15 ns +Display : 9 at 16 ns +Display : 10 at 17 ns +Display : 10 at 18 ns +Stimuli2 : in_valid = true in_value 1 at 21 ns +Stimuli2 : in_valid = true in_value 2 at 22 ns +Stimuli2 : in_valid = true in_value 3 at 23 ns +Stimuli2 : in_valid = true in_value 4 at 24 ns +Display : 10 at 24 ns +Stimuli2 : in_valid = true in_value 5 at 25 ns +Display : 3 at 25 ns +Stimuli2 : in_valid = true in_value 6 at 26 ns +Display : 3 at 26 ns +Stimuli2 : in_valid = true in_value 7 at 27 ns +Display : 5 at 27 ns +Stimuli2 : in_valid = true in_value 8 at 28 ns +Display : 6 at 28 ns +Stimuli2 : in_valid = true in_value 9 at 29 ns +Display : 7 at 29 ns +Stimuli2 : in_valid = true in_value 10 at 30 ns +Display : 8 at 30 ns +Display : 9 at 31 ns +Display : 9 at 32 ns +Display : 10 at 33 ns +Display : 10 at 34 ns +Stimuli3 : in_valid = true in_value 0 at 36 ns +Stimuli3 : in_valid = true in_value 1 at 37 ns +Stimuli3 : in_valid = true in_value 2 at 38 ns +Stimuli3 : in_valid = true in_value 3 at 39 ns +Stimuli3 : in_valid = true in_value 4 at 40 ns +Display : 10 at 40 ns +Stimuli3 : in_valid = true in_value 5 at 41 ns +Display : 3 at 41 ns +Stimuli3 : in_valid = true in_value 6 at 42 ns +Display : 4 at 42 ns +Stimuli3 : in_valid = true in_value 7 at 43 ns +Display : 5 at 43 ns +Stimuli3 : in_valid = true in_value 8 at 44 ns +Display : 6 at 44 ns +Stimuli3 : in_valid = true in_value 9 at 45 ns +Display : 6 at 45 ns +Stimuli3 : in_valid = true in_value 10 at 46 ns +Stimuli1 : in_valid = true in_value 1 at 57 ns +Stimuli1 : in_valid = true in_value 2 at 58 ns +Stimuli1 : in_valid = true in_value 3 at 59 ns +Display : 6 at 59 ns +Stimuli1 : in_valid = true in_value 4 at 60 ns +Display : 2 at 60 ns +Stimuli1 : in_valid = true in_value 5 at 61 ns +Display : 3 at 61 ns +Stimuli1 : in_valid = true in_value 6 at 62 ns +Display : 4 at 62 ns +Stimuli1 : in_valid = true in_value 7 at 63 ns +Display : 5 at 63 ns +Stimuli1 : in_valid = true in_value 8 at 64 ns +Display : 6 at 64 ns +Stimuli1 : in_valid = true in_value 9 at 65 ns +Display : 7 at 65 ns +Stimuli1 : in_valid = true in_value 10 at 66 ns +Display : 8 at 66 ns +Display : 9 at 67 ns +Display : 10 at 68 ns +Display : 10 at 69 ns +Stimuli2 : in_valid = true in_value 1 at 72 ns +Stimuli2 : in_valid = true in_value 2 at 73 ns +Stimuli2 : in_valid = true in_value 3 at 74 ns +Stimuli2 : in_valid = true in_value 4 at 75 ns +Display : 10 at 75 ns +Stimuli2 : in_valid = true in_value 5 at 76 ns +Display : 3 at 76 ns +Stimuli2 : in_valid = true in_value 6 at 77 ns +Display : 3 at 77 ns +Stimuli2 : in_valid = true in_value 7 at 78 ns +Display : 5 at 78 ns +Stimuli2 : in_valid = true in_value 8 at 79 ns +Display : 6 at 79 ns +Stimuli2 : in_valid = true in_value 9 at 80 ns +Display : 7 at 80 ns +Stimuli2 : in_valid = true in_value 10 at 81 ns +Display : 8 at 81 ns +Display : 9 at 82 ns +Display : 9 at 83 ns +Display : 10 at 84 ns +Display : 10 at 85 ns +Stimuli3 : in_valid = true in_value 0 at 87 ns +Stimuli3 : in_valid = true in_value 1 at 88 ns +Stimuli3 : in_valid = true in_value 2 at 89 ns +Stimuli3 : in_valid = true in_value 3 at 90 ns +Stimuli3 : in_valid = true in_value 4 at 91 ns +Display : 10 at 91 ns +Stimuli3 : in_valid = true in_value 5 at 92 ns +Display : 3 at 92 ns +Stimuli3 : in_valid = true in_value 6 at 93 ns +Display : 4 at 93 ns +Stimuli3 : in_valid = true in_value 7 at 94 ns +Display : 5 at 94 ns +Stimuli3 : in_valid = true in_value 8 at 95 ns +Display : 6 at 95 ns +Stimuli3 : in_valid = true in_value 9 at 96 ns +Display : 6 at 96 ns +Stimuli3 : in_valid = true in_value 10 at 97 ns +Stimuli1 : in_valid = true in_value 1 at 108 ns +Stimuli1 : in_valid = true in_value 2 at 109 ns +Stimuli1 : in_valid = true in_value 3 at 110 ns +Display : 6 at 110 ns +Stimuli1 : in_valid = true in_value 4 at 111 ns +Display : 2 at 111 ns +Stimuli1 : in_valid = true in_value 5 at 112 ns +Display : 3 at 112 ns +Stimuli1 : in_valid = true in_value 6 at 113 ns +Display : 4 at 113 ns +Stimuli1 : in_valid = true in_value 7 at 114 ns +Display : 5 at 114 ns +Stimuli1 : in_valid = true in_value 8 at 115 ns +Display : 6 at 115 ns +Stimuli1 : in_valid = true in_value 9 at 116 ns +Display : 7 at 116 ns +Stimuli1 : in_valid = true in_value 10 at 117 ns +Display : 8 at 117 ns +Display : 9 at 118 ns +Display : 10 at 119 ns +Display : 10 at 120 ns +Stimuli2 : in_valid = true in_value 1 at 123 ns +Stimuli2 : in_valid = true in_value 2 at 124 ns +Stimuli2 : in_valid = true in_value 3 at 125 ns +Stimuli2 : in_valid = true in_value 4 at 126 ns +Display : 10 at 126 ns +Stimuli2 : in_valid = true in_value 5 at 127 ns +Display : 3 at 127 ns +Stimuli2 : in_valid = true in_value 6 at 128 ns +Display : 3 at 128 ns +Stimuli2 : in_valid = true in_value 7 at 129 ns +Display : 5 at 129 ns +Stimuli2 : in_valid = true in_value 8 at 130 ns +Display : 6 at 130 ns +Stimuli2 : in_valid = true in_value 9 at 131 ns +Display : 7 at 131 ns +Stimuli2 : in_valid = true in_value 10 at 132 ns +Display : 8 at 132 ns +Display : 9 at 133 ns +Display : 9 at 134 ns +Display : 10 at 135 ns +Display : 10 at 136 ns +Stimuli3 : in_valid = true in_value 0 at 138 ns +Stimuli3 : in_valid = true in_value 1 at 139 ns +Stimuli3 : in_valid = true in_value 2 at 140 ns +Stimuli3 : in_valid = true in_value 3 at 141 ns +Stimuli3 : in_valid = true in_value 4 at 142 ns +Display : 10 at 142 ns +Stimuli3 : in_valid = true in_value 5 at 143 ns +Display : 3 at 143 ns +Stimuli3 : in_valid = true in_value 6 at 144 ns +Display : 4 at 144 ns +Stimuli3 : in_valid = true in_value 7 at 145 ns +Display : 5 at 145 ns +Stimuli3 : in_valid = true in_value 8 at 146 ns +Display : 6 at 146 ns +Stimuli3 : in_valid = true in_value 9 at 147 ns +Display : 6 at 147 ns +Stimuli3 : in_valid = true in_value 10 at 148 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/main.cpp new file mode 100644 index 000000000..f9722f687 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/main.cpp @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "for_fsm.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<bool> out_valid; + sc_signal<int> in_value; + sc_signal<bool> in_valid; + sc_signal<int> result; + + + for_fsm for_fsm1 ( + "process_body", + clock, + reset, + in_valid, + in_value, + out_valid, + result + ); + + stimulus stimulus1 ( + "stimulus", + clock, + reset, + in_value, + in_valid + ); + + display display1 ( + "display", + clock, + result, + out_valid + ); + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/stimulus.cpp new file mode 100644 index 000000000..f61a6def4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/stimulus.cpp @@ -0,0 +1,83 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + int i, j; + + // sending some reset values + reset.write(true); + in_valid.write(false); + in_value.write(0); + wait(); + reset.write(false); + wait(5); + for(i=0; i<3; i++){ + in_valid.write(true); + for(j=1; j<=10; j++) { + in_value.write(j); + cout << "Stimuli1 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(5); + for(j=1; j<=10; j++) { + in_value.write(j); + cout << "Stimuli2 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(5); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli3 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + wait(10); + }; + + wait(15); + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/stimulus.h new file mode 100644 index 000000000..d8bccb0f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/for_fsm/stimulus.h @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& in_value; + sc_signal<bool>& in_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& IN_VALUE, + sc_signal<bool>& IN_VALID + ) + : + reset (RESET), + in_value (IN_VALUE), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/display.cpp new file mode 100644 index 000000000..3e8ba2ec1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/display.cpp @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (out_valid.read()==false) wait(); + cout << "Display : " << result.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/display.h new file mode 100644 index 000000000..b50f526c0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/display.h @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& result; // Input port + const sc_signal<bool>& out_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& RESULT, + const sc_signal<bool>& OUT_VALID + ) + : + result(RESULT), + out_valid(OUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/golden/while_datatypes.log b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/golden/while_datatypes.log new file mode 100644 index 000000000..ee8d4b026 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/golden/while_datatypes.log @@ -0,0 +1,186 @@ +SystemC Simulation +Stimuli1 : in_valid = true in_value 0 at 6 ns +Stimuli1 : in_valid = true in_value 1 at 7 ns +Stimuli1 : in_valid = true in_value 2 at 8 ns +Display : 0 at 8 ns +Stimuli1 : in_valid = true in_value 3 at 9 ns +Display : 1 at 9 ns +Stimuli1 : in_valid = true in_value 4 at 10 ns +Display : 2 at 10 ns +Stimuli1 : in_valid = true in_value 5 at 11 ns +Display : 3 at 11 ns +Stimuli1 : in_valid = true in_value 6 at 12 ns +Display : 4 at 12 ns +Stimuli1 : in_valid = true in_value 7 at 13 ns +Display : 5 at 13 ns +Stimuli1 : in_valid = true in_value 8 at 14 ns +Display : 6 at 14 ns +Stimuli1 : in_valid = true in_value 9 at 15 ns +Display : 7 at 15 ns +Stimuli1 : in_valid = true in_value 10 at 16 ns +Display : 8 at 16 ns +Display : 9 at 17 ns +Display : 10 at 18 ns +Stimuli2 : in_valid = true in_value 0 at 21 ns +Stimuli2 : in_valid = true in_value 1 at 22 ns +Stimuli2 : in_valid = true in_value 2 at 23 ns +Stimuli2 : in_valid = true in_value 3 at 24 ns +Display : 10 at 24 ns +Stimuli2 : in_valid = true in_value 4 at 25 ns +Display : 10 at 25 ns +Stimuli2 : in_valid = true in_value 5 at 26 ns +Display : 10 at 26 ns +Stimuli2 : in_valid = true in_value 6 at 27 ns +Display : 10 at 27 ns +Stimuli2 : in_valid = true in_value 7 at 28 ns +Display : 5 at 28 ns +Stimuli2 : in_valid = true in_value 8 at 29 ns +Display : 6 at 29 ns +Stimuli2 : in_valid = true in_value 9 at 30 ns +Display : 7 at 30 ns +Stimuli2 : in_valid = true in_value 10 at 31 ns +Display : 8 at 31 ns +Display : 8 at 32 ns +Display : 10 at 33 ns +Display : 10 at 34 ns +Display : 10 at 35 ns +Stimuli3 : in_valid = true in_value 0 at 36 ns +Stimuli3 : in_valid = true in_value 1 at 37 ns +Stimuli3 : in_valid = true in_value 2 at 38 ns +Stimuli3 : in_valid = true in_value 3 at 39 ns +Stimuli3 : in_valid = true in_value 4 at 40 ns +Stimuli3 : in_valid = true in_value 5 at 41 ns +Display : 10 at 41 ns +Stimuli3 : in_valid = true in_value 6 at 42 ns +Display : 4 at 42 ns +Stimuli3 : in_valid = true in_value 7 at 43 ns +Display : 5 at 43 ns +Stimuli3 : in_valid = true in_value 8 at 44 ns +Display : 6 at 44 ns +Stimuli3 : in_valid = true in_value 9 at 45 ns +Display : 6 at 45 ns +Stimuli3 : in_valid = true in_value 10 at 46 ns +Stimuli1 : in_valid = true in_value 0 at 57 ns +Stimuli1 : in_valid = true in_value 1 at 58 ns +Stimuli1 : in_valid = true in_value 2 at 59 ns +Display : 6 at 59 ns +Stimuli1 : in_valid = true in_value 3 at 60 ns +Display : 1 at 60 ns +Stimuli1 : in_valid = true in_value 4 at 61 ns +Display : 2 at 61 ns +Stimuli1 : in_valid = true in_value 5 at 62 ns +Display : 3 at 62 ns +Stimuli1 : in_valid = true in_value 6 at 63 ns +Display : 4 at 63 ns +Stimuli1 : in_valid = true in_value 7 at 64 ns +Display : 5 at 64 ns +Stimuli1 : in_valid = true in_value 8 at 65 ns +Display : 6 at 65 ns +Stimuli1 : in_valid = true in_value 9 at 66 ns +Display : 7 at 66 ns +Stimuli1 : in_valid = true in_value 10 at 67 ns +Display : 8 at 67 ns +Display : 9 at 68 ns +Display : 10 at 69 ns +Stimuli2 : in_valid = true in_value 0 at 72 ns +Stimuli2 : in_valid = true in_value 1 at 73 ns +Stimuli2 : in_valid = true in_value 2 at 74 ns +Stimuli2 : in_valid = true in_value 3 at 75 ns +Display : 10 at 75 ns +Stimuli2 : in_valid = true in_value 4 at 76 ns +Display : 10 at 76 ns +Stimuli2 : in_valid = true in_value 5 at 77 ns +Display : 10 at 77 ns +Stimuli2 : in_valid = true in_value 6 at 78 ns +Display : 10 at 78 ns +Stimuli2 : in_valid = true in_value 7 at 79 ns +Display : 5 at 79 ns +Stimuli2 : in_valid = true in_value 8 at 80 ns +Display : 6 at 80 ns +Stimuli2 : in_valid = true in_value 9 at 81 ns +Display : 7 at 81 ns +Stimuli2 : in_valid = true in_value 10 at 82 ns +Display : 8 at 82 ns +Display : 8 at 83 ns +Display : 10 at 84 ns +Display : 10 at 85 ns +Display : 10 at 86 ns +Stimuli3 : in_valid = true in_value 0 at 87 ns +Stimuli3 : in_valid = true in_value 1 at 88 ns +Stimuli3 : in_valid = true in_value 2 at 89 ns +Stimuli3 : in_valid = true in_value 3 at 90 ns +Stimuli3 : in_valid = true in_value 4 at 91 ns +Stimuli3 : in_valid = true in_value 5 at 92 ns +Display : 10 at 92 ns +Stimuli3 : in_valid = true in_value 6 at 93 ns +Display : 4 at 93 ns +Stimuli3 : in_valid = true in_value 7 at 94 ns +Display : 5 at 94 ns +Stimuli3 : in_valid = true in_value 8 at 95 ns +Display : 6 at 95 ns +Stimuli3 : in_valid = true in_value 9 at 96 ns +Display : 6 at 96 ns +Stimuli3 : in_valid = true in_value 10 at 97 ns +Stimuli1 : in_valid = true in_value 0 at 108 ns +Stimuli1 : in_valid = true in_value 1 at 109 ns +Stimuli1 : in_valid = true in_value 2 at 110 ns +Display : 6 at 110 ns +Stimuli1 : in_valid = true in_value 3 at 111 ns +Display : 1 at 111 ns +Stimuli1 : in_valid = true in_value 4 at 112 ns +Display : 2 at 112 ns +Stimuli1 : in_valid = true in_value 5 at 113 ns +Display : 3 at 113 ns +Stimuli1 : in_valid = true in_value 6 at 114 ns +Display : 4 at 114 ns +Stimuli1 : in_valid = true in_value 7 at 115 ns +Display : 5 at 115 ns +Stimuli1 : in_valid = true in_value 8 at 116 ns +Display : 6 at 116 ns +Stimuli1 : in_valid = true in_value 9 at 117 ns +Display : 7 at 117 ns +Stimuli1 : in_valid = true in_value 10 at 118 ns +Display : 8 at 118 ns +Display : 9 at 119 ns +Display : 10 at 120 ns +Stimuli2 : in_valid = true in_value 0 at 123 ns +Stimuli2 : in_valid = true in_value 1 at 124 ns +Stimuli2 : in_valid = true in_value 2 at 125 ns +Stimuli2 : in_valid = true in_value 3 at 126 ns +Display : 10 at 126 ns +Stimuli2 : in_valid = true in_value 4 at 127 ns +Display : 10 at 127 ns +Stimuli2 : in_valid = true in_value 5 at 128 ns +Display : 10 at 128 ns +Stimuli2 : in_valid = true in_value 6 at 129 ns +Display : 10 at 129 ns +Stimuli2 : in_valid = true in_value 7 at 130 ns +Display : 5 at 130 ns +Stimuli2 : in_valid = true in_value 8 at 131 ns +Display : 6 at 131 ns +Stimuli2 : in_valid = true in_value 9 at 132 ns +Display : 7 at 132 ns +Stimuli2 : in_valid = true in_value 10 at 133 ns +Display : 8 at 133 ns +Display : 8 at 134 ns +Display : 10 at 135 ns +Display : 10 at 136 ns +Display : 10 at 137 ns +Stimuli3 : in_valid = true in_value 0 at 138 ns +Stimuli3 : in_valid = true in_value 1 at 139 ns +Stimuli3 : in_valid = true in_value 2 at 140 ns +Stimuli3 : in_valid = true in_value 3 at 141 ns +Stimuli3 : in_valid = true in_value 4 at 142 ns +Stimuli3 : in_valid = true in_value 5 at 143 ns +Display : 10 at 143 ns +Stimuli3 : in_valid = true in_value 6 at 144 ns +Display : 4 at 144 ns +Stimuli3 : in_valid = true in_value 7 at 145 ns +Display : 5 at 145 ns +Stimuli3 : in_valid = true in_value 8 at 146 ns +Display : 6 at 146 ns +Stimuli3 : in_valid = true in_value 9 at 147 ns +Display : 6 at 147 ns +Stimuli3 : in_valid = true in_value 10 at 148 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/main.cpp new file mode 100644 index 000000000..259079b39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/main.cpp @@ -0,0 +1,82 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "while_datatypes.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<bool> out_valid; + sc_signal<bool> in_valid; + sc_signal<int> result; + sc_signal<int> in_value; + + + while_datatypes while_datatypes1 ( + "process_body", + clock, + reset, + in_valid, + in_value, + out_valid, + result + ); + + stimulus stimulus1 ( + "stimulus", + clock, + reset, + in_value, + in_valid + ); + + display display1 ( + "display", + clock, + result, + out_valid + ); + + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/stimulus.cpp new file mode 100644 index 000000000..af5159663 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/stimulus.cpp @@ -0,0 +1,83 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + int i, j; + + // sending some reset values + reset.write(true); + in_valid.write(false); + in_value.write(0); + wait(); + reset.write(false); + wait(5); + for(i=0; i<3; i++){ + in_valid.write(true); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli1 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(4); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli2 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(4); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli3 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + wait(10); + }; + + wait(15); + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/stimulus.h new file mode 100644 index 000000000..e20114c36 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/stimulus.h @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& in_value; + sc_signal<bool>& in_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& IN_VALUE, + sc_signal<bool>& IN_VALID + ) + : + reset (RESET), + in_value (IN_VALUE), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/while_datatypes.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/while_datatypes.cpp new file mode 100644 index 000000000..e0b1ae585 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/while_datatypes.cpp @@ -0,0 +1,120 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + while_datatypes.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "while_datatypes.h" + +#define max 10 + +void while_datatypes::entry() +{ + + int i, inp_tmp; + sc_signed signed_counter(8); + sc_unsigned unsigned_counter(8); + + // reset_loop + if (reset.read()==true) { + result.write(0); + out_valid.write(false); + wait(); + } else wait(); + + //---------- + // main loop + //---------- + while(1) { + + // read inputs + while (in_valid.read()==false) wait(); + + // execution of for loop + out_valid.write(true); + i=1; + wait(); + while (i<=max) { + inp_tmp = in_value.read(); + result.write(inp_tmp); + i++; + wait(); + }; + out_valid.write(false); + wait(5); + + // execution of for loop with continues + out_valid.write(true); + signed_counter=0; + wait(); + do { + signed_counter++; + inp_tmp = in_value.read(); + if (signed_counter==8) { + wait(); + continue; + } else if (in_value.read()<5) { + wait(); + continue; + } else { + result.write(inp_tmp); + wait(); + } + } while (signed_counter.to_int()<=max); + out_valid.write(false); + wait(5); + + // for loop with break + out_valid.write(true); + wait(); + unsigned_counter=0; + do { + unsigned_counter++; + inp_tmp = in_value.read(); + if (inp_tmp==7) { + wait(); + break; + } else { + result.write(inp_tmp); + wait(); + }; + } while (unsigned_counter.to_uint()<=max); + out_valid.write(false); + wait(); + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/while_datatypes.f b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/while_datatypes.f new file mode 100644 index 000000000..bdd5c8d62 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/while_datatypes.f @@ -0,0 +1,4 @@ +while_datatypes/main.cpp +while_datatypes/stimulus.cpp +while_datatypes/display.cpp +while_datatypes/while_datatypes.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/while_datatypes.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/while_datatypes.h new file mode 100644 index 000000000..40c6642b5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_datatypes/while_datatypes.h @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + while_datatypes.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( while_datatypes ) +{ + SC_HAS_PROCESS( while_datatypes ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<bool>& in_valid; + const sc_signal<int>& in_value; + sc_signal<bool>& out_valid; + sc_signal<int>& result; + + while_datatypes ( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<bool>& IN_VALID, + const sc_signal<int>& IN_VALUE, + sc_signal<bool>& OUT_VALID, + sc_signal<int>& RESULT + ) + : + reset (RESET), + in_valid (IN_VALID), + in_value (IN_VALUE), + out_valid (OUT_VALID), + result (RESULT) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + void entry (); +}; diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/display.cpp new file mode 100644 index 000000000..efa95d3cf --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/display.cpp @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up. + while (out_valid.read()==false) wait(); + cout << "Display : " << result.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/display.h new file mode 100644 index 000000000..4f696fcd3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/display.h @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& result; // Input port + const sc_signal<bool>& out_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& RESULT, + const sc_signal<bool>& OUT_VALID + ) + : + result(RESULT), + out_valid(OUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/golden/while_exit.log b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/golden/while_exit.log new file mode 100644 index 000000000..b4ad00f9a --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/golden/while_exit.log @@ -0,0 +1,183 @@ +SystemC Simulation +Stimuli1 : in_valid = true in_value 0 at 6 ns +Stimuli1 : in_valid = true in_value 1 at 7 ns +Stimuli1 : in_valid = true in_value 2 at 8 ns +Display : 0 at 8 ns +Stimuli1 : in_valid = true in_value 3 at 9 ns +Display : 1 at 9 ns +Stimuli1 : in_valid = true in_value 4 at 10 ns +Display : 2 at 10 ns +Stimuli1 : in_valid = true in_value 5 at 11 ns +Display : 3 at 11 ns +Stimuli1 : in_valid = true in_value 6 at 12 ns +Display : 4 at 12 ns +Stimuli1 : in_valid = true in_value 7 at 13 ns +Display : 5 at 13 ns +Stimuli1 : in_valid = true in_value 8 at 14 ns +Display : 6 at 14 ns +Stimuli1 : in_valid = true in_value 9 at 15 ns +Display : 7 at 15 ns +Stimuli1 : in_valid = true in_value 10 at 16 ns +Stimuli2 : in_valid = true in_value 0 at 21 ns +Stimuli2 : in_valid = true in_value 1 at 22 ns +Display : 7 at 22 ns +Stimuli2 : in_valid = true in_value 2 at 23 ns +Display : 7 at 23 ns +Stimuli2 : in_valid = true in_value 3 at 24 ns +Display : 7 at 24 ns +Stimuli2 : in_valid = true in_value 4 at 25 ns +Display : 7 at 25 ns +Stimuli2 : in_valid = true in_value 5 at 26 ns +Display : 7 at 26 ns +Stimuli2 : in_valid = true in_value 6 at 27 ns +Display : 7 at 27 ns +Stimuli2 : in_valid = true in_value 7 at 28 ns +Display : 5 at 28 ns +Stimuli2 : in_valid = true in_value 8 at 29 ns +Display : 6 at 29 ns +Stimuli2 : in_valid = true in_value 9 at 30 ns +Display : 6 at 30 ns +Stimuli2 : in_valid = true in_value 10 at 31 ns +Display : 8 at 31 ns +Display : 9 at 32 ns +Display : 10 at 33 ns +Stimuli3 : in_valid = true in_value 0 at 36 ns +Stimuli3 : in_valid = true in_value 1 at 37 ns +Stimuli3 : in_valid = true in_value 2 at 38 ns +Stimuli3 : in_valid = true in_value 3 at 39 ns +Display : 10 at 39 ns +Stimuli3 : in_valid = true in_value 4 at 40 ns +Display : 2 at 40 ns +Stimuli3 : in_valid = true in_value 5 at 41 ns +Display : 3 at 41 ns +Stimuli3 : in_valid = true in_value 6 at 42 ns +Display : 4 at 42 ns +Stimuli3 : in_valid = true in_value 7 at 43 ns +Display : 5 at 43 ns +Stimuli3 : in_valid = true in_value 8 at 44 ns +Display : 6 at 44 ns +Stimuli3 : in_valid = true in_value 9 at 45 ns +Display : 6 at 45 ns +Stimuli3 : in_valid = true in_value 10 at 46 ns +Stimuli1 : in_valid = true in_value 0 at 57 ns +Stimuli1 : in_valid = true in_value 1 at 58 ns +Stimuli1 : in_valid = true in_value 2 at 59 ns +Display : 6 at 59 ns +Stimuli1 : in_valid = true in_value 3 at 60 ns +Display : 1 at 60 ns +Stimuli1 : in_valid = true in_value 4 at 61 ns +Display : 2 at 61 ns +Stimuli1 : in_valid = true in_value 5 at 62 ns +Display : 3 at 62 ns +Stimuli1 : in_valid = true in_value 6 at 63 ns +Display : 4 at 63 ns +Stimuli1 : in_valid = true in_value 7 at 64 ns +Display : 5 at 64 ns +Stimuli1 : in_valid = true in_value 8 at 65 ns +Display : 6 at 65 ns +Stimuli1 : in_valid = true in_value 9 at 66 ns +Display : 7 at 66 ns +Stimuli1 : in_valid = true in_value 10 at 67 ns +Stimuli2 : in_valid = true in_value 0 at 72 ns +Stimuli2 : in_valid = true in_value 1 at 73 ns +Display : 7 at 73 ns +Stimuli2 : in_valid = true in_value 2 at 74 ns +Display : 7 at 74 ns +Stimuli2 : in_valid = true in_value 3 at 75 ns +Display : 7 at 75 ns +Stimuli2 : in_valid = true in_value 4 at 76 ns +Display : 7 at 76 ns +Stimuli2 : in_valid = true in_value 5 at 77 ns +Display : 7 at 77 ns +Stimuli2 : in_valid = true in_value 6 at 78 ns +Display : 7 at 78 ns +Stimuli2 : in_valid = true in_value 7 at 79 ns +Display : 5 at 79 ns +Stimuli2 : in_valid = true in_value 8 at 80 ns +Display : 6 at 80 ns +Stimuli2 : in_valid = true in_value 9 at 81 ns +Display : 6 at 81 ns +Stimuli2 : in_valid = true in_value 10 at 82 ns +Display : 8 at 82 ns +Display : 9 at 83 ns +Display : 10 at 84 ns +Stimuli3 : in_valid = true in_value 0 at 87 ns +Stimuli3 : in_valid = true in_value 1 at 88 ns +Stimuli3 : in_valid = true in_value 2 at 89 ns +Stimuli3 : in_valid = true in_value 3 at 90 ns +Display : 10 at 90 ns +Stimuli3 : in_valid = true in_value 4 at 91 ns +Display : 2 at 91 ns +Stimuli3 : in_valid = true in_value 5 at 92 ns +Display : 3 at 92 ns +Stimuli3 : in_valid = true in_value 6 at 93 ns +Display : 4 at 93 ns +Stimuli3 : in_valid = true in_value 7 at 94 ns +Display : 5 at 94 ns +Stimuli3 : in_valid = true in_value 8 at 95 ns +Display : 6 at 95 ns +Stimuli3 : in_valid = true in_value 9 at 96 ns +Display : 6 at 96 ns +Stimuli3 : in_valid = true in_value 10 at 97 ns +Stimuli1 : in_valid = true in_value 0 at 108 ns +Stimuli1 : in_valid = true in_value 1 at 109 ns +Stimuli1 : in_valid = true in_value 2 at 110 ns +Display : 6 at 110 ns +Stimuli1 : in_valid = true in_value 3 at 111 ns +Display : 1 at 111 ns +Stimuli1 : in_valid = true in_value 4 at 112 ns +Display : 2 at 112 ns +Stimuli1 : in_valid = true in_value 5 at 113 ns +Display : 3 at 113 ns +Stimuli1 : in_valid = true in_value 6 at 114 ns +Display : 4 at 114 ns +Stimuli1 : in_valid = true in_value 7 at 115 ns +Display : 5 at 115 ns +Stimuli1 : in_valid = true in_value 8 at 116 ns +Display : 6 at 116 ns +Stimuli1 : in_valid = true in_value 9 at 117 ns +Display : 7 at 117 ns +Stimuli1 : in_valid = true in_value 10 at 118 ns +Stimuli2 : in_valid = true in_value 0 at 123 ns +Stimuli2 : in_valid = true in_value 1 at 124 ns +Display : 7 at 124 ns +Stimuli2 : in_valid = true in_value 2 at 125 ns +Display : 7 at 125 ns +Stimuli2 : in_valid = true in_value 3 at 126 ns +Display : 7 at 126 ns +Stimuli2 : in_valid = true in_value 4 at 127 ns +Display : 7 at 127 ns +Stimuli2 : in_valid = true in_value 5 at 128 ns +Display : 7 at 128 ns +Stimuli2 : in_valid = true in_value 6 at 129 ns +Display : 7 at 129 ns +Stimuli2 : in_valid = true in_value 7 at 130 ns +Display : 5 at 130 ns +Stimuli2 : in_valid = true in_value 8 at 131 ns +Display : 6 at 131 ns +Stimuli2 : in_valid = true in_value 9 at 132 ns +Display : 6 at 132 ns +Stimuli2 : in_valid = true in_value 10 at 133 ns +Display : 8 at 133 ns +Display : 9 at 134 ns +Display : 10 at 135 ns +Stimuli3 : in_valid = true in_value 0 at 138 ns +Stimuli3 : in_valid = true in_value 1 at 139 ns +Stimuli3 : in_valid = true in_value 2 at 140 ns +Stimuli3 : in_valid = true in_value 3 at 141 ns +Display : 10 at 141 ns +Stimuli3 : in_valid = true in_value 4 at 142 ns +Display : 2 at 142 ns +Stimuli3 : in_valid = true in_value 5 at 143 ns +Display : 3 at 143 ns +Stimuli3 : in_valid = true in_value 6 at 144 ns +Display : 4 at 144 ns +Stimuli3 : in_valid = true in_value 7 at 145 ns +Display : 5 at 145 ns +Stimuli3 : in_valid = true in_value 8 at 146 ns +Display : 6 at 146 ns +Stimuli3 : in_valid = true in_value 9 at 147 ns +Display : 6 at 147 ns +Stimuli3 : in_valid = true in_value 10 at 148 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/main.cpp new file mode 100644 index 000000000..7d176025e --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/main.cpp @@ -0,0 +1,82 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "while_exit.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<bool> out_valid; + sc_signal<bool> in_valid; + sc_signal<int> result; + sc_signal<int> in_value; + + + while_exit while_exit1 ( + "process_body", + clock, + reset, + in_valid, + in_value, + out_valid, + result + ); + + stimulus stimulus1 ( + "stimulus", + clock, + reset, + in_value, + in_valid + ); + + display display1 ( + "display", + clock, + result, + out_valid + ); + + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/stimulus.cpp new file mode 100644 index 000000000..d86f16758 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/stimulus.cpp @@ -0,0 +1,83 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + int i, j; + + // sending some reset values + reset.write(true); + in_valid.write(false); + in_value.write(0); + wait(); + reset.write(false); + wait(5); + for(i=0; i<3; i++){ + in_valid.write(true); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli1 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(4); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli2 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(4); + for(j=0; j<=10; j++) { + in_value.write(j); + cout << "Stimuli3 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + wait(10); + }; + + wait(15); + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/stimulus.h new file mode 100644 index 000000000..5bc8313de --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/stimulus.h @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& in_value; + sc_signal<bool>& in_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& IN_VALUE, + sc_signal<bool>& IN_VALID + ) + : + reset (RESET), + in_value (IN_VALUE), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/while_exit.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/while_exit.cpp new file mode 100644 index 000000000..5cc53af40 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/while_exit.cpp @@ -0,0 +1,124 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + while_exit.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "while_exit.h" + +#define max 10 + +void while_exit::entry() +{ + + int i, inp_tmp; + + // reset_loop + if (reset.read()==true) { + result.write(0); + out_valid.write(false); + wait(); + } else wait(); + + //---------- + // main loop + //---------- + while(1) { + + // read inputs + while (in_valid.read()==false) wait(); + + // execution of while loop with exit after write statement + out_valid.write(true); + i=1; + wait(); + while (i<=max) { + inp_tmp = in_value.read(); + result.write(inp_tmp); + if (inp_tmp==7) { + wait(); + break; + } else { + i++; + wait(); + }; + }; + out_valid.write(false); + wait(6); + + // execution of do loop with continues + out_valid.write(true); + i=0; + wait(); + do { + i++; + inp_tmp = in_value.read(); + if (i==8) { + wait(); + continue; + } else if (in_value.read()<5) { + wait(); + continue; + } else { + result.write(inp_tmp); + wait(); + } + } while (i<=max); + out_valid.write(false); + wait(5); + + // execution of do loop with exit after before statement + out_valid.write(true); + i=0; + wait(); + do { + i++; + inp_tmp = in_value.read(); + if (inp_tmp==7) { + wait(); + break; + } else { + result.write(inp_tmp); + wait(); + }; + } while (i<=max); + out_valid.write(false); + wait(); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/while_exit.f b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/while_exit.f new file mode 100644 index 000000000..947eeefd1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/while_exit.f @@ -0,0 +1,4 @@ +while_exit/main.cpp +while_exit/stimulus.cpp +while_exit/display.cpp +while_exit/while_exit.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/while_exit.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/while_exit.h new file mode 100644 index 000000000..a57397dd4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_exit/while_exit.h @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + while_exit.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-30 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( while_exit ) +{ + SC_HAS_PROCESS( while_exit ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<bool>& in_valid; + const sc_signal<int>& in_value; + sc_signal<bool>& out_valid; + sc_signal<int>& result; + + while_exit( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<bool>& IN_VALID, + const sc_signal<int>& IN_VALUE, + sc_signal<bool>& OUT_VALID, + sc_signal<int>& RESULT + ) + : + reset (RESET), + in_valid (IN_VALID), + in_value (IN_VALUE), + out_valid (OUT_VALID), + result (RESULT) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + void entry (); +}; diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/display.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/display.cpp new file mode 100644 index 000000000..3e8ba2ec1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/display.cpp @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "display.h" + +void display::entry(){ + + wait(2); + while(1) { + // Reading Data, and Counter i,j is counted up.
+ while (out_valid.read()==false) wait(); + cout << "Display : " << result.read() << " " + << " at " << sc_time_stamp() << endl; + wait(); + } +} + + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/display.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/display.h new file mode 100644 index 000000000..b50f526c0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/display.h @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( display ) +{ + SC_HAS_PROCESS( display ); + + sc_in_clk clk; + + const sc_signal<int>& result; // Input port + const sc_signal<bool>& out_valid; + + display( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<int>& RESULT, + const sc_signal<bool>& OUT_VALID + ) + : + result(RESULT), + out_valid(OUT_VALID) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/golden/while_fsm.log b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/golden/while_fsm.log new file mode 100644 index 000000000..acee1098d --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/golden/while_fsm.log @@ -0,0 +1,183 @@ +SystemC Simulation +Stimuli1 : in_valid = true in_value 1 at 6 ns +Stimuli1 : in_valid = true in_value 2 at 7 ns +Stimuli1 : in_valid = true in_value 3 at 8 ns +Display : 0 at 8 ns +Stimuli1 : in_valid = true in_value 4 at 9 ns +Display : 2 at 9 ns +Stimuli1 : in_valid = true in_value 5 at 10 ns +Display : 3 at 10 ns +Stimuli1 : in_valid = true in_value 6 at 11 ns +Display : 4 at 11 ns +Stimuli1 : in_valid = true in_value 7 at 12 ns +Display : 5 at 12 ns +Stimuli1 : in_valid = true in_value 8 at 13 ns +Display : 6 at 13 ns +Stimuli1 : in_valid = true in_value 9 at 14 ns +Display : 7 at 14 ns +Stimuli1 : in_valid = true in_value 10 at 15 ns +Display : 8 at 15 ns +Display : 9 at 16 ns +Display : 10 at 17 ns +Display : 10 at 18 ns +Stimuli2 : in_valid = true in_value 1 at 20 ns +Display : 10 at 20 ns +Stimuli2 : in_valid = true in_value 2 at 21 ns +Display : 10 at 21 ns +Stimuli2 : in_valid = true in_value 3 at 22 ns +Display : 10 at 22 ns +Stimuli2 : in_valid = true in_value 4 at 23 ns +Display : 10 at 23 ns +Stimuli2 : in_valid = true in_value 5 at 24 ns +Display : 10 at 24 ns +Stimuli2 : in_valid = true in_value 6 at 25 ns +Display : 10 at 25 ns +Stimuli2 : in_valid = true in_value 7 at 26 ns +Display : 5 at 26 ns +Stimuli2 : in_valid = true in_value 8 at 27 ns +Display : 6 at 27 ns +Stimuli2 : in_valid = true in_value 9 at 28 ns +Display : 6 at 28 ns +Stimuli2 : in_valid = true in_value 10 at 29 ns +Display : 8 at 29 ns +Display : 9 at 30 ns +Display : 10 at 31 ns +Stimuli3 : in_valid = true in_value 1 at 34 ns +Stimuli3 : in_valid = true in_value 2 at 35 ns +Stimuli3 : in_valid = true in_value 3 at 36 ns +Display : 10 at 36 ns +Stimuli3 : in_valid = true in_value 4 at 37 ns +Display : 2 at 37 ns +Stimuli3 : in_valid = true in_value 5 at 38 ns +Display : 3 at 38 ns +Stimuli3 : in_valid = true in_value 6 at 39 ns +Display : 4 at 39 ns +Stimuli3 : in_valid = true in_value 7 at 40 ns +Display : 5 at 40 ns +Stimuli3 : in_valid = true in_value 8 at 41 ns +Display : 6 at 41 ns +Stimuli3 : in_valid = true in_value 9 at 42 ns +Display : 6 at 42 ns +Stimuli3 : in_valid = true in_value 10 at 43 ns +Stimuli1 : in_valid = true in_value 1 at 54 ns +Stimuli1 : in_valid = true in_value 2 at 55 ns +Stimuli1 : in_valid = true in_value 3 at 56 ns +Display : 6 at 56 ns +Stimuli1 : in_valid = true in_value 4 at 57 ns +Display : 2 at 57 ns +Stimuli1 : in_valid = true in_value 5 at 58 ns +Display : 3 at 58 ns +Stimuli1 : in_valid = true in_value 6 at 59 ns +Display : 4 at 59 ns +Stimuli1 : in_valid = true in_value 7 at 60 ns +Display : 5 at 60 ns +Stimuli1 : in_valid = true in_value 8 at 61 ns +Display : 6 at 61 ns +Stimuli1 : in_valid = true in_value 9 at 62 ns +Display : 7 at 62 ns +Stimuli1 : in_valid = true in_value 10 at 63 ns +Display : 8 at 63 ns +Display : 9 at 64 ns +Display : 10 at 65 ns +Display : 10 at 66 ns +Stimuli2 : in_valid = true in_value 1 at 68 ns +Display : 10 at 68 ns +Stimuli2 : in_valid = true in_value 2 at 69 ns +Display : 10 at 69 ns +Stimuli2 : in_valid = true in_value 3 at 70 ns +Display : 10 at 70 ns +Stimuli2 : in_valid = true in_value 4 at 71 ns +Display : 10 at 71 ns +Stimuli2 : in_valid = true in_value 5 at 72 ns +Display : 10 at 72 ns +Stimuli2 : in_valid = true in_value 6 at 73 ns +Display : 10 at 73 ns +Stimuli2 : in_valid = true in_value 7 at 74 ns +Display : 5 at 74 ns +Stimuli2 : in_valid = true in_value 8 at 75 ns +Display : 6 at 75 ns +Stimuli2 : in_valid = true in_value 9 at 76 ns +Display : 6 at 76 ns +Stimuli2 : in_valid = true in_value 10 at 77 ns +Display : 8 at 77 ns +Display : 9 at 78 ns +Display : 10 at 79 ns +Stimuli3 : in_valid = true in_value 1 at 82 ns +Stimuli3 : in_valid = true in_value 2 at 83 ns +Stimuli3 : in_valid = true in_value 3 at 84 ns +Display : 10 at 84 ns +Stimuli3 : in_valid = true in_value 4 at 85 ns +Display : 2 at 85 ns +Stimuli3 : in_valid = true in_value 5 at 86 ns +Display : 3 at 86 ns +Stimuli3 : in_valid = true in_value 6 at 87 ns +Display : 4 at 87 ns +Stimuli3 : in_valid = true in_value 7 at 88 ns +Display : 5 at 88 ns +Stimuli3 : in_valid = true in_value 8 at 89 ns +Display : 6 at 89 ns +Stimuli3 : in_valid = true in_value 9 at 90 ns +Display : 6 at 90 ns +Stimuli3 : in_valid = true in_value 10 at 91 ns +Stimuli1 : in_valid = true in_value 1 at 102 ns +Stimuli1 : in_valid = true in_value 2 at 103 ns +Stimuli1 : in_valid = true in_value 3 at 104 ns +Display : 6 at 104 ns +Stimuli1 : in_valid = true in_value 4 at 105 ns +Display : 2 at 105 ns +Stimuli1 : in_valid = true in_value 5 at 106 ns +Display : 3 at 106 ns +Stimuli1 : in_valid = true in_value 6 at 107 ns +Display : 4 at 107 ns +Stimuli1 : in_valid = true in_value 7 at 108 ns +Display : 5 at 108 ns +Stimuli1 : in_valid = true in_value 8 at 109 ns +Display : 6 at 109 ns +Stimuli1 : in_valid = true in_value 9 at 110 ns +Display : 7 at 110 ns +Stimuli1 : in_valid = true in_value 10 at 111 ns +Display : 8 at 111 ns +Display : 9 at 112 ns +Display : 10 at 113 ns +Display : 10 at 114 ns +Stimuli2 : in_valid = true in_value 1 at 116 ns +Display : 10 at 116 ns +Stimuli2 : in_valid = true in_value 2 at 117 ns +Display : 10 at 117 ns +Stimuli2 : in_valid = true in_value 3 at 118 ns +Display : 10 at 118 ns +Stimuli2 : in_valid = true in_value 4 at 119 ns +Display : 10 at 119 ns +Stimuli2 : in_valid = true in_value 5 at 120 ns +Display : 10 at 120 ns +Stimuli2 : in_valid = true in_value 6 at 121 ns +Display : 10 at 121 ns +Stimuli2 : in_valid = true in_value 7 at 122 ns +Display : 5 at 122 ns +Stimuli2 : in_valid = true in_value 8 at 123 ns +Display : 6 at 123 ns +Stimuli2 : in_valid = true in_value 9 at 124 ns +Display : 6 at 124 ns +Stimuli2 : in_valid = true in_value 10 at 125 ns +Display : 8 at 125 ns +Display : 9 at 126 ns +Display : 10 at 127 ns +Stimuli3 : in_valid = true in_value 1 at 130 ns +Stimuli3 : in_valid = true in_value 2 at 131 ns +Stimuli3 : in_valid = true in_value 3 at 132 ns +Display : 10 at 132 ns +Stimuli3 : in_valid = true in_value 4 at 133 ns +Display : 2 at 133 ns +Stimuli3 : in_valid = true in_value 5 at 134 ns +Display : 3 at 134 ns +Stimuli3 : in_valid = true in_value 6 at 135 ns +Display : 4 at 135 ns +Stimuli3 : in_valid = true in_value 7 at 136 ns +Display : 5 at 136 ns +Stimuli3 : in_valid = true in_value 8 at 137 ns +Display : 6 at 137 ns +Stimuli3 : in_valid = true in_value 9 at 138 ns +Display : 6 at 138 ns +Stimuli3 : in_valid = true in_value 10 at 139 ns + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/main.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/main.cpp new file mode 100644 index 000000000..69ab12ad6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/main.cpp @@ -0,0 +1,82 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "while_fsm.h" +#include "stimulus.h" +#include "display.h" + +int sc_main (int argc , char *argv[]) { + sc_clock clock; + sc_signal<bool> reset; + sc_signal<bool> out_valid; + sc_signal<bool> in_valid; + sc_signal<int> result; + sc_signal<int> in_value; + + + while_fsm while_fsm1 ( + "process_body", + clock, + reset, + in_valid, + in_value, + out_valid, + result + ); + + stimulus stimulus1 ( + "stimulus", + clock, + reset, + in_value, + in_valid + ); + + display display1 ( + "display", + clock, + result, + out_valid + ); + + + sc_start(); + return 0; +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/stimulus.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/stimulus.cpp new file mode 100644 index 000000000..61049e207 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/stimulus.cpp @@ -0,0 +1,82 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "stimulus.h" + +void stimulus::entry() { + + int i, j; + + // sending some reset values + reset.write(true); + in_valid.write(false); + in_value.write(0); + wait(); + reset.write(false); + wait(5); + for(i=0; i<3; i++){ + in_valid.write(true); + for(j=1; j<=10; j++) { + in_value.write(j); + cout << "Stimuli1 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + in_valid.write(false); + wait(4); + for(j=1; j<=10; j++) { + in_value.write(j); + cout << "Stimuli2 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + wait(4); + for(j=1; j<=10; j++) { + in_value.write(j); + cout << "Stimuli3 : in_valid = true in_value " << j << " at " + << sc_time_stamp() << endl; + wait(); + }; + wait(10); + }; + + wait(15); + sc_stop(); +} + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/stimulus.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/stimulus.h new file mode 100644 index 000000000..e20114c36 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/stimulus.h @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimulus.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( stimulus ) +{ + SC_HAS_PROCESS( stimulus ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<int>& in_value; + sc_signal<bool>& in_valid; + + stimulus(sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& RESET, + sc_signal<int>& IN_VALUE, + sc_signal<bool>& IN_VALID + ) + : + reset (RESET), + in_value (IN_VALUE), + in_valid (IN_VALID) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; + +// EOF diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/while_fsm.cpp b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/while_fsm.cpp new file mode 100644 index 000000000..a3f08d992 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/while_fsm.cpp @@ -0,0 +1,120 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + while_fsm.cpp -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "while_fsm.h" + +#define max 10 + +void while_fsm::entry() +{ + + int i, inp_tmp; + + // reset_loop + if (reset.read()==true) { + result.write(0); + out_valid.write(false); + wait(); + } else wait(); + + //---------- + // main loop + //---------- + while(1) { + + // read inputs + while (in_valid.read()==false) wait(); + + // execution of for loop + out_valid.write(true); + i=1; + wait(); + while (i<=max) { + inp_tmp = in_value.read(); + result.write(inp_tmp); + i++; + wait(); + }; + out_valid.write(false); + wait(); + + // execution of for loop with continues + out_valid.write(true); + i=0; + wait(); + do { + i++; + inp_tmp = in_value.read(); + if (i==8) { + wait(); + continue; + } else if (in_value.read()<5 && i!=1) { + wait(); + continue; + } else { + result.write(inp_tmp); + wait(); + } + } while (i<=max); + out_valid.write(false); + wait(); + wait(3); + + // for loop with break + out_valid.write(true); + i=0; + wait(); + do { + i++; + inp_tmp = in_value.read(); + if (inp_tmp==7) { + wait(); + break; + } else { + result.write(inp_tmp); + wait(); + }; + } while (i<=max); + out_valid.write(false); + wait(); + + } +} + +// EOF + diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/while_fsm.f b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/while_fsm.f new file mode 100644 index 000000000..e47e026a1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/while_fsm.f @@ -0,0 +1,4 @@ +while_fsm/main.cpp +while_fsm/stimulus.cpp +while_fsm/display.cpp +while_fsm/while_fsm.cpp diff --git a/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/while_fsm.h b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/while_fsm.h new file mode 100644 index 000000000..75fd0080c --- /dev/null +++ b/src/systemc/tests/systemc/misc/cae_test/general/control/loop/while_fsm/while_fsm.h @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + while_fsm.h -- + + Original Author: Rocco Jonack, Synopsys, Inc., 1999-07-27 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +#include "systemc.h" + +SC_MODULE( while_fsm ) +{ + SC_HAS_PROCESS( while_fsm ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<bool>& in_valid; + const sc_signal<int>& in_value; + sc_signal<bool>& out_valid; + sc_signal<int>& result; + + while_fsm( + sc_module_name NAME, // referense name + sc_clock& CLK, // clock + const sc_signal<bool>& RESET, + const sc_signal<bool>& IN_VALID, + const sc_signal<int>& IN_VALUE, + sc_signal<bool>& OUT_VALID, + sc_signal<int>& RESULT + ) + : + reset (RESET), + in_valid (IN_VALID), + in_value (IN_VALUE), + out_valid (OUT_VALID), + result (RESULT) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + }; + void entry (); +}; |