diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/sim_tests/srlatch')
7 files changed, 324 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/sim_tests/srlatch/golden/srlatch.log b/src/systemc/tests/systemc/misc/sim_tests/srlatch/golden/srlatch.log new file mode 100644 index 000000000..a8c1cc302 --- /dev/null +++ b/src/systemc/tests/systemc/misc/sim_tests/srlatch/golden/srlatch.log @@ -0,0 +1,7 @@ +SystemC Simulation +SR=10 QQ'=01 +SR=01 QQ'=10 +SR=00 QQ'=10 +SR=11 QQ'=00 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/sim_tests/srlatch/main.cpp b/src/systemc/tests/systemc/misc/sim_tests/srlatch/main.cpp new file mode 100644 index 000000000..4c7929dc1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/sim_tests/srlatch/main.cpp @@ -0,0 +1,63 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Main routine for nor-based SR latch */ + +#include "testbench.h" +#include "nor.h" + +int +sc_main(int ac, char *av[]) +{ + sc_signal<bool> s; + sc_signal<bool> r; + sc_signal<bool> q; + sc_signal<bool> qp; + + /* Signal initialization to make sure that we do not have an infinite loop of evaluate-update cycles */ + s = true; + r = true; + + sc_clock clk("Clock"); + + testbench T("TB", clk, q, qp, s, r); + nor G1("G1", s, qp, q); + nor G2("G2", r, q, qp); + + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/sim_tests/srlatch/nor.cpp b/src/systemc/tests/systemc/misc/sim_tests/srlatch/nor.cpp new file mode 100644 index 000000000..199e539a1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/sim_tests/srlatch/nor.cpp @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + nor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename nor.cc */ +/* This is the implementation file for asynchronous process `nor' */ + +#include "nor.h" + +void nor::entry() +{ + c.write(!(a.read() | b.read())); +} // end of entry function diff --git a/src/systemc/tests/systemc/misc/sim_tests/srlatch/nor.h b/src/systemc/tests/systemc/misc/sim_tests/srlatch/nor.h new file mode 100644 index 000000000..ab9b05c2f --- /dev/null +++ b/src/systemc/tests/systemc/misc/sim_tests/srlatch/nor.h @@ -0,0 +1,67 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + nor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename nor.h */ +/* This is the interface file for asynchronous process 'nor' */ + +#include "systemc.h" + +SC_MODULE( nor ) +{ + SC_HAS_PROCESS( nor ); + + sc_in<bool> a; + sc_in<bool> b; + sc_out<bool> c; + + // Constructor + nor( sc_module_name NAME, + sc_signal<bool>& A, + sc_signal<bool>& B, + sc_signal<bool>& C ) + { + a(A); + b(B); + c(C); + SC_METHOD( entry ); + sensitive << a << b; + } + + // Process functionality in member function below + void entry(); +}; + diff --git a/src/systemc/tests/systemc/misc/sim_tests/srlatch/srlatch.f b/src/systemc/tests/systemc/misc/sim_tests/srlatch/srlatch.f new file mode 100644 index 000000000..0935e227f --- /dev/null +++ b/src/systemc/tests/systemc/misc/sim_tests/srlatch/srlatch.f @@ -0,0 +1,3 @@ +srlatch/nor.cpp +srlatch/testbench.cpp +srlatch/main.cpp diff --git a/src/systemc/tests/systemc/misc/sim_tests/srlatch/testbench.cpp b/src/systemc/tests/systemc/misc/sim_tests/srlatch/testbench.cpp new file mode 100644 index 000000000..b5c50c778 --- /dev/null +++ b/src/systemc/tests/systemc/misc/sim_tests/srlatch/testbench.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + testbench.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename testbench.cc */ +/* This is the implementation file for synchronous process `testbench' */ + +#include "testbench.h" + +void testbench::entry() +{ + char buf[BUFSIZ]; + s.write(true); + r.write(false); + wait(); + sprintf(buf, "SR=%x%x QQ'=%x%x", true, false, q.read(), qp.read()); + cout << buf << endl; + s.write(false); + r.write(true); + wait(); + sprintf(buf, "SR=%x%x QQ'=%x%x", false, true, q.read(), qp.read()); + cout << buf << endl; + s.write(false); + r.write(false); + wait(); + sprintf(buf, "SR=%x%x QQ'=%x%x", false, false, q.read(), qp.read()); + cout << buf << endl; + s.write(true); + r.write(true); + wait(); + sprintf(buf, "SR=%x%x QQ'=%x%x", true, true, q.read(), qp.read()); + cout << buf << endl; + sc_stop(); +} // end of entry function + diff --git a/src/systemc/tests/systemc/misc/sim_tests/srlatch/testbench.h b/src/systemc/tests/systemc/misc/sim_tests/srlatch/testbench.h new file mode 100644 index 000000000..368b3d103 --- /dev/null +++ b/src/systemc/tests/systemc/misc/sim_tests/srlatch/testbench.h @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + testbench.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename testbench.h */ +/* This is the interface file for synchronous process 'testbench' */ + +#include "systemc.h" + +SC_MODULE( testbench ) +{ + SC_HAS_PROCESS( testbench ); + + sc_in_clk clk; + + sc_in<bool> q; + sc_in<bool> qp; + sc_out<bool> s; + sc_out<bool> r; + + // Constructor + testbench( sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& Q, + sc_signal<bool>& QP, + sc_signal<bool>& S, + sc_signal<bool>& R ) + { + clk(CLK); + q(Q); qp(QP); s(S); r(R); + SC_CTHREAD( entry, clk.pos() ); + } + + // Process functionality in member function below + void entry(); +}; + |