diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/synth/add_chain')
10 files changed, 1172 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.cpp b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.cpp new file mode 100644 index 000000000..56132f484 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.cpp @@ -0,0 +1,73 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + add_chain.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// $Log: add_chain.cpp,v $ +// Revision 1.2 2011/09/05 21:23:35 acg +// Philipp A. Hartmann: eliminate compiler warnings. +// +// Revision 1.1.1.1 2006/12/15 20:26:13 acg +// systemc_tests-2.3 +// +// Revision 1.4 2006/01/24 21:05:23 acg +// Andy Goodrich: replacement of deprecated features with their non-deprecated +// counterparts. +// +// Revision 1.3 2006/01/20 00:43:19 acg +// Andy Goodrich: Changed over to use putenv() instead of setenv() to accommodate old versions of Solaris. +// +// Revision 1.2 2006/01/19 00:47:26 acg +// Andy Goodrich: Changes for the fact signal write checking is enabled. +// + +#define SC_NO_WRITE_CHECK +#include "systemc.h" +#include "define.h" +#include "display.h" +#include "data_gen.h" +#include "reset_stim.h" +#include "add_chain.h" +#include "tb.h" + +int +sc_main(int ac, char *av[]) +{ + sc_clock clk( "CLOCK", 20, SC_NS, 0.5, 0, SC_NS, false); // Clock function + testbench tb1("TB1", clk ); // Testbench Instance + + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.dat b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.dat new file mode 100644 index 000000000..f6352869f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.dat @@ -0,0 +1,257 @@ +11111111 +00000000 +00000001 +00000010 +00000011 +00000100 +00000101 +00000110 +00000111 +00001000 +00001001 +00001010 +00001011 +00001100 +00001101 +00001110 +00001111 +00010000 +00010001 +00010010 +00010011 +00010100 +00010101 +00010110 +00010111 +00011000 +00011001 +00011010 +00011011 +00011100 +00011101 +00011110 +00011111 +00100000 +00100001 +00100010 +00100011 +00100100 +00100101 +00100110 +00100111 +00101000 +00101001 +00101010 +00101011 +00101100 +00101101 +00101110 +00101111 +00110000 +00110001 +00110010 +00110011 +00110100 +00110101 +00110110 +00110111 +00111000 +00111001 +00111010 +00111011 +00111100 +00111101 +00111110 +00111111 +01000000 +01000001 +01000010 +01000011 +01000100 +01000101 +01000110 +01000111 +01001000 +01001001 +01001010 +01001011 +01001100 +01001101 +01001110 +01001111 +01010000 +01010001 +01010010 +01010011 +01010100 +01010101 +01010110 +01010111 +01011000 +01011001 +01011010 +01011011 +01011100 +01011101 +01011110 +01011111 +01100000 +01100001 +01100010 +01100011 +01100100 +01100101 +01100110 +01100111 +01101000 +01101001 +01101010 +01101011 +01101100 +01101101 +01101110 +01101111 +01110000 +01110001 +01110010 +01110011 +01110100 +01110101 +01110110 +01110111 +01111000 +01111001 +01111010 +01111011 +01111100 +01111101 +01111110 +01111111 +10000000 +10000001 +10000010 +10000011 +10000100 +10000101 +10000110 +10000111 +10001000 +10001001 +10001010 +10001011 +10001100 +10001101 +10001110 +10001111 +10010000 +10010001 +10010010 +10010011 +10010100 +10010101 +10010110 +10010111 +10011000 +10011001 +10011010 +10011011 +10011100 +10011101 +10011110 +10011111 +10100000 +10100001 +10100010 +10100011 +10100100 +10100101 +10100110 +10100111 +10101000 +10101001 +10101010 +10101011 +10101100 +10101101 +10101110 +10101111 +10110000 +10110001 +10110010 +10110011 +10110100 +10110101 +10110110 +10110111 +10111000 +10111001 +10111010 +10111011 +10111100 +10111101 +10111110 +10111111 +11000000 +11000001 +11000010 +11000011 +11000100 +11000101 +11000110 +11000111 +11001000 +11001001 +11001010 +11001011 +11001100 +11001101 +11001110 +11001111 +11010000 +11010001 +11010010 +11010011 +11010100 +11010101 +11010110 +11010111 +11011000 +11011001 +11011010 +11011011 +11011100 +11011101 +11011110 +11011111 +11100000 +11100001 +11100010 +11100011 +11100100 +11100101 +11100110 +11100111 +11101000 +11101001 +11101010 +11101011 +11101100 +11101101 +11101110 +11101111 +11110000 +11110001 +11110010 +11110011 +11110100 +11110101 +11110110 +11110111 +11111000 +11111001 +11111010 +11111011 +11111100 +11111101 +11111110 +11111111 diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.h b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.h new file mode 100644 index 000000000..3162903bb --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.h @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + add_chain.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +/******************************************************************************/ +/*************************** add_chain Class Definition ********************/ +/******************************************************************************/ + +SC_MODULE( ADD_CHAIN ) +{ + SC_HAS_PROCESS( ADD_CHAIN ); + + sc_in_clk clk; + + const sc_signal<bool>& rst; + const signal_bool_vector8& a_in; + signal_bool_vector4& sum_out; + sc_signal<bool>& ready; + + ADD_CHAIN( sc_module_name NAME, + sc_clock& TICK_P, + + const sc_signal<bool>& RST, + const signal_bool_vector8& A_IN, + signal_bool_vector4& SUM_OUT, + sc_signal<bool>& READY + ) + : + rst (RST), + a_in (A_IN), + sum_out (SUM_OUT), + ready (READY) + { + clk(TICK_P); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(rst, false); + } + void entry(); +}; + +/******************************************************************************/ +/*************************** add_chain Entry Function **********************/ +/******************************************************************************/ +/** **/ +/** This function sums the number of 1's contained in a 8-bit data stream **/ +/** **/ +/******************************************************************************/ +void +ADD_CHAIN::entry() +{ + bool_vector4 sum; + bool_vector8 a; + + /***** Reset Initialization *****/ + sum_out.write(0); + ready.write(1); + wait(); + + /***** MAIN LOOP *****/ + while(true) { + + /***** Handshake *****/ + ready.write(0); + wait(); + + /***** Computation *****/ + sum = 0; + a = a_in.read(); + + for (int i=0; i<=7; i=i+1) { + sum = sum.to_uint() + a[i].to_bool(); + } + + sum_out.write(sum); + + /***** Handshake *****/ + ready.write(1); + wait(); + } +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/common.h b/src/systemc/tests/systemc/misc/synth/add_chain/common.h new file mode 100644 index 000000000..850b96ab7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/common.h @@ -0,0 +1,49 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#define SC_NO_WRITE_CHECK +#include "systemc.h" + +typedef sc_bv<4> bool_vector4; +typedef sc_bv<8> bool_vector8; +typedef sc_signal<bool_vector4> signal_bool_vector4; +typedef sc_signal<bool_vector8> signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/data_gen.h b/src/systemc/tests/systemc/misc/synth/add_chain/data_gen.h new file mode 100644 index 000000000..18df486d3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/data_gen.h @@ -0,0 +1,100 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + data_gen.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "define.h" + +/******************************************************************************/ +/*************************** data_gen Function **********************/ +/******************************************************************************/ + +SC_MODULE( DATA_GEN ) +{ + SC_HAS_PROCESS( DATA_GEN ); + + sc_in_clk clk; + + /*** Input and Output Ports ***/ + const sc_signal<bool>& ready; + signal_bool_vector8& data; + sc_signal<int>& addr; + + /*** Constructor ***/ + DATA_GEN ( sc_module_name NAME, + sc_clock& TICK_N, + const sc_signal<bool>& READY, + signal_bool_vector8& DATA, + sc_signal<int>& ADDR ) + + : + ready (READY), + data (DATA), // 8 bits + addr (ADDR) + + { + clk (TICK_N); + SC_CTHREAD( entry, clk.neg() ); + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +DATA_GEN::entry() +{ + + while(true) { + +// WAIT FOR POSEDGE OF ready + + at_posedge(ready); + +// CHECK TO SEE IF THE END OF MEMORY HAS BEEN REACHED + + if(addr.read() > LIMIT) { // if(addr > LIMIT) + break; + } + +// WRITE VALUE OF MEMORY AT CURRENT ADDRESS TO data +// INCREMENT addr BY 1 + + data.write(mem[addr.read()]); // data = mem[addr] + addr.write(addr.read() + 1); // addr = addr + 1 + } + +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/define.h b/src/systemc/tests/systemc/misc/synth/add_chain/define.h new file mode 100644 index 000000000..99f950a1a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/define.h @@ -0,0 +1,44 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +#define LIMIT 257 // Last stimulus vector memory address location +#define WIDTH 8 // Width of stimulus vector +#define LATENCY 3 // Latency of sum + +extern bool_vector8 mem[]; diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/display.h b/src/systemc/tests/systemc/misc/synth/add_chain/display.h new file mode 100644 index 000000000..bef1bf3b4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/display.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "define.h" + + +/******************************************************************************/ +/*************************** Output Display Function **********************/ +/******************************************************************************/ + +SC_MODULE( DISPLAY ) +{ + SC_HAS_PROCESS( DISPLAY ); + + /*** Input and Output Ports ***/ + const sc_signal<bool>& ready; // Input + const signal_bool_vector8& data; // Input + const signal_bool_vector4& sum; // Input + + /*** Constructor ***/ + DISPLAY ( sc_module_name NAME, + const sc_signal<bool>& READY, + const signal_bool_vector8& DATA, + const signal_bool_vector4& SUM ) + + : ready (READY), + data (DATA), // 8 bits + sum (SUM) + + { + SC_METHOD( entry ); + sensitive << ready; + sensitive << data; + sensitive << sum; + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +DISPLAY::entry() +{ +// DISPLAY NUMBER OF 1'S IN DATA AT NEGEDGE ready + + if( ready.posedge() ) { + cout << "Sum of " + << data.read() + << " is " << sum.read().to_uint() + << endl; + } +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/golden/add_chain.log b/src/systemc/tests/systemc/misc/synth/add_chain/golden/add_chain.log new file mode 100644 index 000000000..35db754ef --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/golden/add_chain.log @@ -0,0 +1,262 @@ +SystemC Simulation +Sum of 00000000 is 0 +Sum of 11111111 is 8 +Sum of 00000000 is 0 +Sum of 00000001 is 1 +Sum of 00000010 is 1 +Sum of 00000011 is 2 +Sum of 00000100 is 1 +Sum of 00000101 is 2 +Sum of 00000110 is 2 +Sum of 00000111 is 3 +Sum of 00001000 is 1 +Sum of 00001001 is 2 +Sum of 00001010 is 2 +Sum of 00001011 is 3 +Sum of 00001100 is 2 +Sum of 00001101 is 3 +Sum of 00001110 is 3 +Sum of 00001111 is 4 +Sum of 00010000 is 1 +Sum of 00010001 is 2 +Sum of 00010010 is 2 +Sum of 00010011 is 3 +Sum of 00010100 is 2 +Sum of 00010101 is 3 +Sum of 00010110 is 3 +Sum of 00010111 is 4 +Sum of 00011000 is 2 +Sum of 00011001 is 3 +Sum of 00011010 is 3 +Sum of 00011011 is 4 +Sum of 00011100 is 3 +Sum of 00011101 is 4 +Sum of 00011110 is 4 +Sum of 00011111 is 5 +Sum of 00100000 is 1 +Sum of 00100001 is 2 +Sum of 00100010 is 2 +Sum of 00100011 is 3 +Sum of 00100100 is 2 +Sum of 00100101 is 3 +Sum of 00100110 is 3 +Sum of 00100111 is 4 +Sum of 00101000 is 2 +Sum of 00101001 is 3 +Sum of 00101010 is 3 +Sum of 00101011 is 4 +Sum of 00101100 is 3 +Sum of 00101101 is 4 +Sum of 00101110 is 4 +Sum of 00101111 is 5 +Sum of 00110000 is 2 +Sum of 00110001 is 3 +Sum of 00110010 is 3 +Sum of 00110011 is 4 +Sum of 00110100 is 3 +Sum of 00110101 is 4 +Sum of 00110110 is 4 +Sum of 00110111 is 5 +Sum of 00111000 is 3 +Sum of 00111001 is 4 +Sum of 00111010 is 4 +Sum of 00111011 is 5 +Sum of 00111100 is 4 +Sum of 00111101 is 5 +Sum of 00111110 is 5 +Sum of 00111111 is 6 +Sum of 01000000 is 1 +Sum of 01000001 is 2 +Sum of 01000010 is 2 +Sum of 01000011 is 3 +Sum of 01000100 is 2 +Sum of 01000101 is 3 +Sum of 01000110 is 3 +Sum of 01000111 is 4 +Sum of 01001000 is 2 +Sum of 01001001 is 3 +Sum of 01001010 is 3 +Sum of 01001011 is 4 +Sum of 01001100 is 3 +Sum of 01001101 is 4 +Sum of 01001110 is 4 +Sum of 01001111 is 5 +Sum of 01010000 is 2 +Sum of 01010001 is 3 +Sum of 01010010 is 3 +Sum of 01010011 is 4 +Sum of 01010100 is 3 +Sum of 01010101 is 4 +Sum of 01010110 is 4 +Sum of 01010111 is 5 +Sum of 01011000 is 3 +Sum of 01011001 is 4 +Sum of 01011010 is 4 +Sum of 01011011 is 5 +Sum of 01011100 is 4 +Sum of 01011101 is 5 +Sum of 01011110 is 5 +Sum of 01011111 is 6 +Sum of 01100000 is 2 +Sum of 01100001 is 3 +Sum of 01100010 is 3 +Sum of 01100011 is 4 +Sum of 01100100 is 3 +Sum of 01100101 is 4 +Sum of 01100110 is 4 +Sum of 01100111 is 5 +Sum of 01101000 is 3 +Sum of 01101001 is 4 +Sum of 01101010 is 4 +Sum of 01101011 is 5 +Sum of 01101100 is 4 +Sum of 01101101 is 5 +Sum of 01101110 is 5 +Sum of 01101111 is 6 +Sum of 01110000 is 3 +Sum of 01110001 is 4 +Sum of 01110010 is 4 +Sum of 01110011 is 5 +Sum of 01110100 is 4 +Sum of 01110101 is 5 +Sum of 01110110 is 5 +Sum of 01110111 is 6 +Sum of 01111000 is 4 +Sum of 01111001 is 5 +Sum of 01111010 is 5 +Sum of 01111011 is 6 +Sum of 01111100 is 5 +Sum of 01111101 is 6 +Sum of 01111110 is 6 +Sum of 01111111 is 7 +Sum of 10000000 is 1 +Sum of 10000001 is 2 +Sum of 10000010 is 2 +Sum of 10000011 is 3 +Sum of 10000100 is 2 +Sum of 10000101 is 3 +Sum of 10000110 is 3 +Sum of 10000111 is 4 +Sum of 10001000 is 2 +Sum of 10001001 is 3 +Sum of 10001010 is 3 +Sum of 10001011 is 4 +Sum of 10001100 is 3 +Sum of 10001101 is 4 +Sum of 10001110 is 4 +Sum of 10001111 is 5 +Sum of 10010000 is 2 +Sum of 10010001 is 3 +Sum of 10010010 is 3 +Sum of 10010011 is 4 +Sum of 10010100 is 3 +Sum of 10010101 is 4 +Sum of 10010110 is 4 +Sum of 10010111 is 5 +Sum of 10011000 is 3 +Sum of 10011001 is 4 +Sum of 10011010 is 4 +Sum of 10011011 is 5 +Sum of 10011100 is 4 +Sum of 10011101 is 5 +Sum of 10011110 is 5 +Sum of 10011111 is 6 +Sum of 10100000 is 2 +Sum of 10100001 is 3 +Sum of 10100010 is 3 +Sum of 10100011 is 4 +Sum of 10100100 is 3 +Sum of 10100101 is 4 +Sum of 10100110 is 4 +Sum of 10100111 is 5 +Sum of 10101000 is 3 +Sum of 10101001 is 4 +Sum of 10101010 is 4 +Sum of 10101011 is 5 +Sum of 10101100 is 4 +Sum of 10101101 is 5 +Sum of 10101110 is 5 +Sum of 10101111 is 6 +Sum of 10110000 is 3 +Sum of 10110001 is 4 +Sum of 10110010 is 4 +Sum of 10110011 is 5 +Sum of 10110100 is 4 +Sum of 10110101 is 5 +Sum of 10110110 is 5 +Sum of 10110111 is 6 +Sum of 10111000 is 4 +Sum of 10111001 is 5 +Sum of 10111010 is 5 +Sum of 10111011 is 6 +Sum of 10111100 is 5 +Sum of 10111101 is 6 +Sum of 10111110 is 6 +Sum of 10111111 is 7 +Sum of 11000000 is 2 +Sum of 11000001 is 3 +Sum of 11000010 is 3 +Sum of 11000011 is 4 +Sum of 11000100 is 3 +Sum of 11000101 is 4 +Sum of 11000110 is 4 +Sum of 11000111 is 5 +Sum of 11001000 is 3 +Sum of 11001001 is 4 +Sum of 11001010 is 4 +Sum of 11001011 is 5 +Sum of 11001100 is 4 +Sum of 11001101 is 5 +Sum of 11001110 is 5 +Sum of 11001111 is 6 +Sum of 11010000 is 3 +Sum of 11010001 is 4 +Sum of 11010010 is 4 +Sum of 11010011 is 5 +Sum of 11010100 is 4 +Sum of 11010101 is 5 +Sum of 11010110 is 5 +Sum of 11010111 is 6 +Sum of 11011000 is 4 +Sum of 11011001 is 5 +Sum of 11011010 is 5 +Sum of 11011011 is 6 +Sum of 11011100 is 5 +Sum of 11011101 is 6 +Sum of 11011110 is 6 +Sum of 11011111 is 7 +Sum of 11100000 is 3 +Sum of 11100001 is 4 +Sum of 11100010 is 4 +Sum of 11100011 is 5 +Sum of 11100100 is 4 +Sum of 11100101 is 5 +Sum of 11100110 is 5 +Sum of 11100111 is 6 +Sum of 11101000 is 4 +Sum of 11101001 is 5 +Sum of 11101010 is 5 +Sum of 11101011 is 6 +Sum of 11101100 is 5 +Sum of 11101101 is 6 +Sum of 11101110 is 6 +Sum of 11101111 is 7 +Sum of 11110000 is 4 +Sum of 11110001 is 5 +Sum of 11110010 is 5 +Sum of 11110011 is 6 +Sum of 11110100 is 5 +Sum of 11110101 is 6 +Sum of 11110110 is 6 +Sum of 11110111 is 7 +Sum of 11111000 is 5 +Sum of 11111001 is 6 +Sum of 11111010 is 6 +Sum of 11111011 is 7 +Sum of 11111100 is 6 +Sum of 11111101 is 7 +Sum of 11111110 is 7 +Sum of 11111111 is 8 +Sum of 11111111 is 8 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/reset_stim.h b/src/systemc/tests/systemc/misc/synth/add_chain/reset_stim.h new file mode 100644 index 000000000..437e52b2f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/reset_stim.h @@ -0,0 +1,111 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + reset_stim.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "define.h" + +/******************************************************************************/ +/*************************** reset_stim Function **********************/ +/******************************************************************************/ +bool_vector8 mem [LIMIT + 1]; // Stimulus input memory + +SC_MODULE( RESET_STIM ) +{ + SC_HAS_PROCESS( RESET_STIM ); + + sc_in_clk clk; + + /*** Input and Output Ports ***/ + sc_signal<bool>& ready; + sc_signal<bool>& reset; + sc_signal<int>& addr; + + /*** Constructor ***/ + RESET_STIM ( sc_module_name NAME, + sc_clock& TICK_N, + sc_signal<bool>& READY, + sc_signal<bool>& RESET, + sc_signal<int>& ADDR ) + + : + ready (READY), + reset (RESET), + addr (ADDR) + + { + clk (TICK_N); + SC_CTHREAD( entry, clk.neg() ); + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +RESET_STIM::entry() +{ + +// LOAD MEMORY WITH DATA AT TIME ZERO + + ifstream stimulus ("add_chain/add_chain.dat"); + char buffer[WIDTH+1]; + + for(int i=1; i < LIMIT+1; i++) { + stimulus >> buffer; + mem[i] = buffer; + } + + stimulus.close(); + +// INITIALIZE reset AND addr, THEN REMOVE RESET AFTER 2 CLOCK CYCLES + + reset.write(0); // reset = 0 + addr.write(1); // addr = 1 + wait(2); + + reset.write(1); // reset = 1 + wait(); + +// WAIT FOR LAST MEMORY ADDRESS, THEN 3 CLOCKS, THEN STOP SIMULATION + + // do { wait(); } while (addr == LIMIT); + do { wait(); } while (!(addr == LIMIT)); + wait(LATENCY); + do { wait(); } while (ready != 1); + sc_stop(); + halt(); +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/tb.h b/src/systemc/tests/systemc/misc/synth/add_chain/tb.h new file mode 100644 index 000000000..bf96292dd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/tb.h @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** Testbench Function **********************/ +/******************************************************************************/ +/* */ +/* The testbench module has the following hierarchy: */ +/* */ +/* testbench */ +/* - RESET_STIM */ +/* - DATA_GEN */ +/* */ +/******************************************************************************/ + +struct testbench : public sc_module { + sc_signal<int> addr; // Address of input memory + sc_signal<bool> reset; + sc_signal<bool> ready; + signal_bool_vector8 data; + signal_bool_vector4 sum; + RESET_STIM rd1; + DATA_GEN dg1; + ADD_CHAIN ac1; + DISPLAY d1; + + /*** Constructor ***/ + testbench ( const sc_module_name& NAME, + sc_clock& TICK ) + + : sc_module(), + rd1 ("RD1", TICK, ready, reset, addr), + dg1 ("DG1", TICK, ready, data, addr), + ac1 ("AC1", TICK, reset, data, sum, ready), + d1 ("D1", ready, data, sum) + + { + end_module(); + } +}; |