diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/synth/circle')
5 files changed, 523 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/synth/circle/circ48.cpp b/src/systemc/tests/systemc/misc/synth/circle/circ48.cpp new file mode 100644 index 000000000..918fc5418 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/circ48.cpp @@ -0,0 +1,63 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + circ48.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "circ48.h" + +int +sc_main( int, char *[] ) +{ + sc_clock clk( "clk", 20, SC_NS, 0.5, 10, SC_NS ); + + sc_signal<bool> I_reset; + sc_signal<bool> I_x_ok; + sc_signal<bool> I_y_ok; + sc_signal<bool> O_out_wr; + sc_signal<bool> O_out_sel; + signal_bool_vector O_out_xy; + signal_bool_vector O_diffs; + + testbench tb( "TB", clk, I_reset, I_x_ok, I_y_ok, + O_out_wr, O_out_sel, O_out_xy ); + + circ48 c1( "C1", clk, I_reset, I_x_ok, I_y_ok, + O_out_wr, O_out_sel, O_out_xy, O_diffs ); + + sc_start(); + + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/circle/circ48.h b/src/systemc/tests/systemc/misc/synth/circle/circ48.h new file mode 100644 index 000000000..e26234a2e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/circ48.h @@ -0,0 +1,197 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + circ48.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( circ48 ) +{ + SC_HAS_PROCESS( circ48 ); + + sc_in_clk clk; + + sc_in<bool> reset; + sc_in<bool> x_ok; + sc_in<bool> y_ok; + sc_out<bool> out_wr; + sc_out<bool> out_sel; + sc_out<bool_vector> out_xy; + sc_out<bool_vector> diffs; + + void entry(); + + circ48( sc_module_name name_, + const sc_clock& clk_, + const sc_signal<bool>& reset_, + const sc_signal<bool>& x_ok_, + const sc_signal<bool>& y_ok_, + sc_signal<bool>& out_wr_, + sc_signal<bool>& out_sel_, + signal_bool_vector& out_xy_, + signal_bool_vector& diffs_ ) + : sc_module( name_ ) + { + clk( clk_ ); + reset( reset_ ); + x_ok( x_ok_ ); + y_ok( y_ok_ ); + out_wr( out_wr_ ); + out_sel( out_sel_ ); + out_xy( out_xy_ ); + diffs( diffs_ ); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + } +}; + + +/*****************************************************************************/ +/** **/ +/** This function is the "clean" behavior (i.e. not written with synthesis **/ +/** or implementation in mind. This is a circle generator, that uses an **/ +/** algorithmic, interpolating technique. Origin of circle is fixed to **/ +/** point (0,0) **/ +/** NOTE: Extra WAIT at end for VGB (requires waits after signal assign) **/ +/** **/ +/*****************************************************************************/ + +void +circ48::entry() +{ + sc_signed x(4); + sc_signed y(4); + sc_signed x_end(4); + sc_signed y_end(4); + sc_signed diff(8); + bool first; + + // reset initialization + + out_wr.write( 0 ); // Initialize at time zero ???? + out_sel.write( 0 ); + + // setup counter-clockwise circle generation + + while(true) { // Reset_loop + x_end = 4; + x = x_end; + diff = 0; + diffs.write(diff); + y_end = 4; + y = y_end; + first = true; + wait(); + + // perform counter-clockwise circle generation + + while(first || (x != x_end) || (y != y_end)) { // Main_loop + first = false; + diff = diff + 1; + + if (diff > 1) { + if ((x >= 0) && (y >= 0)) { + diff = diff - x - x; + x = x - 1; + } + else { // else_1_begin + if ((x < 0) && (y >= 0)) { + diff = diff - y - y; + y = y - 1; + } + else { // else_2_begin + if ((x < 0) && (y < 0)) { + diff = diff + x + x; + x = x + 1; + } + else { + diff = diff + y + y; + y = y + 1; + } + } // else_2_end + } // else_1_end + } + else { + if ((x >= 0) && (y >= 0)) { + diff = diff + y + y; + y = y + 1; + } + else { // else_3_begin + if ((x < 0) && (y >= 0)) { + diff = diff - x - x; + x = x - 1; + } + else { // else_4_begin + if ((x < 0) && (y < 0)) { + diff = diff - y - y; + y = y - 1; + } + else { + diff = x + x; + x = x + 1; + } + } // else_4_end + } // else_3_end + } + + // send the intermediate x value to port + + out_sel.write(0); // Select x + out_wr.write(1); // Output ready signal + out_xy.write(x); + diffs.write(diff); + wait(); + + // handshake x.. + + do { wait(); } while (x_ok == 0); + out_wr.write(0); + wait(); + + // send the intermediate y value to port + + out_sel.write(1); // Select y + out_wr.write(1); // Output ready signal + out_xy.write(y); + wait(); + + // handshake y.. + + do { wait(); } while (y_ok == 0); + out_wr.write(0); + wait(); + } // End of Main_loop + } // End of Reset_loop +} diff --git a/src/systemc/tests/systemc/misc/synth/circle/common.h b/src/systemc/tests/systemc/misc/synth/circle/common.h new file mode 100644 index 000000000..3ea41ad75 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_bv<8> bool_vector; +typedef sc_signal<bool_vector> signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/synth/circle/golden/circ48.log b/src/systemc/tests/systemc/misc/synth/circle/golden/circ48.log new file mode 100644 index 000000000..136e1c7c1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/golden/circ48.log @@ -0,0 +1,21 @@ +SystemC Simulation + + FINAL MEMORY VALUES +Memory Location 1 : 0000000000000000 +Memory Location 2 : 0000000111100000 +Memory Location 3 : 0000011101111000 +Memory Location 4 : 0001110001110000 +Memory Location 5 : 0001000000010000 +Memory Location 6 : 0011000000011000 +Memory Location 7 : 0010000000001000 +Memory Location 8 : 0010000000001100 +Memory Location 9 : 0011000000001100 +Memory Location 10 : 0001000000001000 +Memory Location 11 : 0001100000011000 +Memory Location 12 : 0000100000110000 +Memory Location 13 : 0000111011100000 +Memory Location 14 : 0000001110000000 +Memory Location 15 : 0000000000000000 +Memory Location 16 : 0000000000000000 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/circle/tb.h b/src/systemc/tests/systemc/misc/synth/circle/tb.h new file mode 100644 index 000000000..3004bb35c --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/tb.h @@ -0,0 +1,196 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( testbench ) +{ + SC_HAS_PROCESS( testbench ); + + sc_in_clk clk; + + sc_out<bool> reset; + sc_out<bool> x_ok; + sc_out<bool> y_ok; + sc_in<bool> data_ready; + sc_in<bool> select_xy; + sc_in<bool_vector> coord_xy; + + void entry(); + + testbench( sc_module_name name_, + const sc_clock& clk_, + sc_signal<bool>& reset_, + sc_signal<bool>& x_ok_, + sc_signal<bool>& y_ok_, + const sc_signal<bool>& data_ready_, + const sc_signal<bool>& select_xy_, + const signal_bool_vector& coord_xy_ ) + : sc_module( name_ ) + { + clk( clk_ ); + reset( reset_ ); + x_ok( x_ok_ ); + y_ok( y_ok_ ); + data_ready( data_ready_ ); + select_xy( select_xy_ ); + coord_xy( coord_xy_ ); + SC_CTHREAD( entry, clk.neg() ); + } +}; + +sc_bv<16> mem[17]; + +void +testbench::entry() +{ + bool_vector x_coord; + bool_vector y_coord; + int x_flag = 0; + int y_flag = 0; + int i; // Counter variable + int x = 0; // Memory location of x_coord + int y = 1; // Memory location of y_coord + + // reset initialization + + reset.write(1); + x_ok.write(0); + y_ok.write(0); + wait(); + reset.write(0); + wait(); + + // fill display memory with zeros + + for (i = 1; i < 17; i++) + mem[i] = 0; + + // capture of (x,y) coordinates + + while(true) { + + // wait for new x or y coordinate to be calculated + + do { wait(); } while (data_ready == 0); + + // capture x coordinate + + if(select_xy.read() == 0) { + x_coord = coord_xy.read(); + x_flag = x_flag + 1; + x_ok.write(1); + } + + // capture y coordinate + + if(select_xy.read() == 1) { + y_coord = coord_xy.read(); + y_flag = y_flag + 1; + y_ok.write(1); + } + + wait(); + x_ok.write(0); + y_ok.write(0); + + // debug display of coordinate sets + /* + if (x_flag == y_flag) { + cout << " Coordinate Set #" << x_flag + << " X = " << x_coord.to_int() + << " Y = " << y_coord.to_int() + << endl; + } + */ + + // conversion of x coordinate values to memory column locations + + if (x_coord.to_int() == -8) x = 15; + if (x_coord.to_int() == -7) x = 14; + if (x_coord.to_int() == -6) x = 13; + if (x_coord.to_int() == -5) x = 12; + if (x_coord.to_int() == -4) x = 11; + if (x_coord.to_int() == -3) x = 10; + if (x_coord.to_int() == -2) x = 9; + if (x_coord.to_int() == -1) x = 8; + if (x_coord.to_int() == 0) x = 7; + if (x_coord.to_int() == 1) x = 6; + if (x_coord.to_int() == 2) x = 5; + if (x_coord.to_int() == 3) x = 4; + if (x_coord.to_int() == 4) x = 3; + if (x_coord.to_int() == 5) x = 2; + if (x_coord.to_int() == 6) x = 1; + if (x_coord.to_int() == 7) x = 0; + + // conversion of y coordinate values to memory row locations + + if (y_coord.to_int() == -8) y = 16; + if (y_coord.to_int() == -7) y = 15; + if (y_coord.to_int() == -6) y = 14; + if (y_coord.to_int() == -5) y = 13; + if (y_coord.to_int() == -4) y = 12; + if (y_coord.to_int() == -3) y = 11; + if (y_coord.to_int() == -2) y = 10; + if (y_coord.to_int() == -1) y = 9; + if (y_coord.to_int() == 0) y = 8; + if (y_coord.to_int() == 1) y = 7; + if (y_coord.to_int() == 2) y = 6; + if (y_coord.to_int() == 3) y = 5; + if (y_coord.to_int() == 4) y = 4; + if (y_coord.to_int() == 5) y = 3; + if (y_coord.to_int() == 6) y = 2; + if (y_coord.to_int() == 7) y = 1; + + // turn bit high in memory for calculated coordinate + + mem[y][x] = 1; + + // stop simulation after 100 coordinates + + if (y_flag == 100) break; + + } // End of while loop + + cout << "\n\t FINAL MEMORY VALUES" << endl; + + for (i = 1; i < 17; i++) + cout << "Memory Location " << i + << " : \t" << mem[i] << endl; + + sc_stop(); +} |