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-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/golden/test1.log1
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/interface.h89
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/test1.cpp53
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/golden/test2.log1
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/interface.h89
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/test2.cpp62
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/golden/test3.log1
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/interface.h89
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/test3.cpp53
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/define.h55
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/golden/test.log5
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/main.cpp80
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.cpp56
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.cpp52
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.cpp58
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.h102
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/define.h55
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/golden/test.log5
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/main.cpp80
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.cpp56
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.cpp52
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.cpp62
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.h102
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/define.h55
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/golden/test.log5
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/main.cpp80
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.cpp56
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.cpp52
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.cpp61
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.h102
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/define.h55
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/golden/test.log5
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/main.cpp80
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.cpp56
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.cpp52
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.cpp61
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.h102
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/define.h55
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/golden/test.log5
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/main.cpp80
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.cpp56
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.cpp52
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.cpp62
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.h102
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/define.h55
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/golden/test.log5
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/main.cpp80
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.cpp56
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.cpp52
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.h101
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.cpp60
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.h102
69 files changed, 4138 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/golden/test1.log b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/golden/test1.log
new file mode 100644
index 000000000..6d243dcc5
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/golden/test1.log
@@ -0,0 +1 @@
+SystemC Simulation
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/interface.h b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/interface.h
new file mode 100644
index 000000000..e2c229b67
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/interface.h
@@ -0,0 +1,89 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ interface.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( t )
+{
+ SC_HAS_PROCESS( t );
+
+ sc_in_clk clk;
+
+ const sc_signal<bool>& reset_sig;
+
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ t (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4),
+ i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/test1.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/test1.cpp
new file mode 100644
index 000000000..62774b719
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/test1.cpp
@@ -0,0 +1,53 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test1.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "interface.h"
+
+void t::entry()
+{
+ int i;
+
+ o1 = i1 + i2;
+
+ wait();
+}
+
+int sc_main(int argc, char* argv[] )
+{
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/golden/test2.log b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/golden/test2.log
new file mode 100644
index 000000000..6d243dcc5
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/golden/test2.log
@@ -0,0 +1 @@
+SystemC Simulation
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/interface.h b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/interface.h
new file mode 100644
index 000000000..e2c229b67
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/interface.h
@@ -0,0 +1,89 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ interface.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( t )
+{
+ SC_HAS_PROCESS( t );
+
+ sc_in_clk clk;
+
+ const sc_signal<bool>& reset_sig;
+
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ t (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4),
+ i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/test2.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/test2.cpp
new file mode 100644
index 000000000..40824db36
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/test2.cpp
@@ -0,0 +1,62 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test2.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "interface.h"
+
+int x (int y, int z)
+{
+ return y+z;
+}
+
+void t::entry()
+{
+ o1 = i1 + i2;
+ o2 = i1 + i2;
+ o3 = x (1,2);
+ o4 = x (1,2);
+ o5 = x ( 1,2);
+ o5 = x ( x(1,2),2);
+ o5 = x ( 1, x(1,2));
+
+ wait();
+}
+
+int sc_main(int argc, char* argv[] )
+{
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/golden/test3.log b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/golden/test3.log
new file mode 100644
index 000000000..6d243dcc5
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/golden/test3.log
@@ -0,0 +1 @@
+SystemC Simulation
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/interface.h b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/interface.h
new file mode 100644
index 000000000..e2c229b67
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/interface.h
@@ -0,0 +1,89 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ interface.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( t )
+{
+ SC_HAS_PROCESS( t );
+
+ sc_in_clk clk;
+
+ const sc_signal<bool>& reset_sig;
+
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ t (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4),
+ i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/test3.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/test3.cpp
new file mode 100644
index 000000000..179ac9b46
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/test3.cpp
@@ -0,0 +1,53 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test3.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "interface.h"
+
+void t::entry()
+{
+ int i;
+
+ o1 = i1 + i2;
+ o1 = i1 + i2;
+ wait();
+}
+
+int sc_main(int argc, char* argv[] )
+{
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/define.h
new file mode 100644
index 000000000..d671993cd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/define.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ define.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#define CLOCK_PERIOD 100
+#define TB_CLOCK_PERIOD 50
+#define DUTY_CYCLE 0.5
+#define EVENT_TIME 50
+#define TEST_TIME 50
+
+#define long_wait wait(10)
+#define single_cycle wait(2)
+#define set_value(var,val) wait(); var = val; wait()
+#define test_value(actual, expected) \
+ wait (); if (expected != actual) \
+ cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl; \
+ wait ()
+#define test_value_now(actual, expected) \
+ if (expected != actual) cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl;
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/golden/test.log
new file mode 100644
index 000000000..510bd7f39
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/golden/test.log
@@ -0,0 +1,5 @@
+SystemC Simulation
+Begin Simulation
+End Simulation
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/main.cpp
new file mode 100644
index 000000000..852905b57
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/main.cpp
@@ -0,0 +1,80 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+// Main routine
+
+#include "systemc.h"
+#include "test.h"
+#include "tb.h"
+#include "monitor.h"
+#include "define.h"
+
+int sc_main(int ac, char *av[])
+{
+ sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
+
+ sc_signal<bool> reset_sig;
+
+ sc_signal<int> i1;
+ sc_signal<int> i2;
+ sc_signal<int> i3;
+ sc_signal<int> i4;
+ sc_signal<int> i5;
+
+ sc_signal<bool> cont1;
+ sc_signal<bool> cont2;
+ sc_signal<bool> cont3;
+
+ sc_signal<int> o1;
+ sc_signal<int> o2;
+ sc_signal<int> o3;
+ sc_signal<int> o4;
+ sc_signal<int> o5;
+
+ test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+
+ // Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.cpp
new file mode 100644
index 000000000..103437eee
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.cpp
@@ -0,0 +1,56 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "monitor.h"
+
+void monitor::entry()
+{
+ int cycleNo = 0;
+
+ while (true) {
+ cout << "[Cycle No: " << cycleNo << "]" <<
+ " i1 = " << i1 <<
+ " o1 = " << o1 <<
+ " o2 = " << o2 <<
+ " cont1 = " << cont1 <<
+ endl;
+ cycleNo++;
+ wait();
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.h
new file mode 100644
index 000000000..a827f7c8a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for monitor process
+ Author: PRP
+ */
+
+SC_MODULE( monitor )
+{
+ SC_HAS_PROCESS( monitor );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ monitor (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.cpp
new file mode 100644
index 000000000..dfc57d75a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "tb.h"
+#include "define.h"
+
+void tb::entry()
+{
+ cout << "Begin Simulation" << endl;
+
+
+ cout << "End Simulation" << endl;
+
+ sc_stop();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.h
new file mode 100644
index 000000000..5e76fb35d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test bench
+ Author: PRP
+ */
+
+SC_MODULE( tb )
+{
+ SC_HAS_PROCESS( tb );
+
+ sc_in_clk clk;
+
+ // Output Reset Port
+ sc_signal<bool>& reset_sig;
+
+ // Output Data Ports
+ sc_signal<int>& i1;
+ sc_signal<int>& i2;
+ sc_signal<int>& i3;
+ sc_signal<int>& i4;
+ sc_signal<int>& i5;
+
+ // Output Control Ports
+ sc_signal<bool>& cont1;
+ sc_signal<bool>& cont2;
+ sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ tb (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ sc_signal<bool>& RESET_SIG,
+
+ sc_signal<int>& I1,
+ sc_signal<int>& I2,
+ sc_signal<int>& I3,
+ sc_signal<int>& I4,
+ sc_signal<int>& I5,
+
+ sc_signal<bool>& CONT1,
+ sc_signal<bool>& CONT2,
+ sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.cpp
new file mode 100644
index 000000000..356af707a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.cpp
@@ -0,0 +1,58 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/*
+ Verifies resource directive
+ Author: PRP
+ From Test Case resource: 25.cc
+*/
+#include "systemc.h"
+#include "test.h"
+
+void test::entry()
+{
+
+ int i,j;
+
+ i = 9 + i1.read();
+ o1 = 8 + i;
+ o2 = i2;
+
+ wait();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.f
new file mode 100644
index 000000000..df637f6d7
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.f
@@ -0,0 +1,4 @@
+test1/test.cpp
+test1/tb.cpp
+test1/monitor.cpp
+test1/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.h
new file mode 100644
index 000000000..5596f1f8d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( test )
+{
+ SC_HAS_PROCESS( test );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Output Data Ports
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ test (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/define.h
new file mode 100644
index 000000000..d671993cd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/define.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ define.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#define CLOCK_PERIOD 100
+#define TB_CLOCK_PERIOD 50
+#define DUTY_CYCLE 0.5
+#define EVENT_TIME 50
+#define TEST_TIME 50
+
+#define long_wait wait(10)
+#define single_cycle wait(2)
+#define set_value(var,val) wait(); var = val; wait()
+#define test_value(actual, expected) \
+ wait (); if (expected != actual) \
+ cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl; \
+ wait ()
+#define test_value_now(actual, expected) \
+ if (expected != actual) cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl;
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/golden/test.log
new file mode 100644
index 000000000..510bd7f39
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/golden/test.log
@@ -0,0 +1,5 @@
+SystemC Simulation
+Begin Simulation
+End Simulation
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/main.cpp
new file mode 100644
index 000000000..852905b57
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/main.cpp
@@ -0,0 +1,80 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+// Main routine
+
+#include "systemc.h"
+#include "test.h"
+#include "tb.h"
+#include "monitor.h"
+#include "define.h"
+
+int sc_main(int ac, char *av[])
+{
+ sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
+
+ sc_signal<bool> reset_sig;
+
+ sc_signal<int> i1;
+ sc_signal<int> i2;
+ sc_signal<int> i3;
+ sc_signal<int> i4;
+ sc_signal<int> i5;
+
+ sc_signal<bool> cont1;
+ sc_signal<bool> cont2;
+ sc_signal<bool> cont3;
+
+ sc_signal<int> o1;
+ sc_signal<int> o2;
+ sc_signal<int> o3;
+ sc_signal<int> o4;
+ sc_signal<int> o5;
+
+ test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+
+ // Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.cpp
new file mode 100644
index 000000000..103437eee
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.cpp
@@ -0,0 +1,56 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "monitor.h"
+
+void monitor::entry()
+{
+ int cycleNo = 0;
+
+ while (true) {
+ cout << "[Cycle No: " << cycleNo << "]" <<
+ " i1 = " << i1 <<
+ " o1 = " << o1 <<
+ " o2 = " << o2 <<
+ " cont1 = " << cont1 <<
+ endl;
+ cycleNo++;
+ wait();
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.h
new file mode 100644
index 000000000..a827f7c8a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for monitor process
+ Author: PRP
+ */
+
+SC_MODULE( monitor )
+{
+ SC_HAS_PROCESS( monitor );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ monitor (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.cpp
new file mode 100644
index 000000000..dfc57d75a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "tb.h"
+#include "define.h"
+
+void tb::entry()
+{
+ cout << "Begin Simulation" << endl;
+
+
+ cout << "End Simulation" << endl;
+
+ sc_stop();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.h
new file mode 100644
index 000000000..5e76fb35d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test bench
+ Author: PRP
+ */
+
+SC_MODULE( tb )
+{
+ SC_HAS_PROCESS( tb );
+
+ sc_in_clk clk;
+
+ // Output Reset Port
+ sc_signal<bool>& reset_sig;
+
+ // Output Data Ports
+ sc_signal<int>& i1;
+ sc_signal<int>& i2;
+ sc_signal<int>& i3;
+ sc_signal<int>& i4;
+ sc_signal<int>& i5;
+
+ // Output Control Ports
+ sc_signal<bool>& cont1;
+ sc_signal<bool>& cont2;
+ sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ tb (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ sc_signal<bool>& RESET_SIG,
+
+ sc_signal<int>& I1,
+ sc_signal<int>& I2,
+ sc_signal<int>& I3,
+ sc_signal<int>& I4,
+ sc_signal<int>& I5,
+
+ sc_signal<bool>& CONT1,
+ sc_signal<bool>& CONT2,
+ sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.cpp
new file mode 100644
index 000000000..33c500faf
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.cpp
@@ -0,0 +1,62 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+
+/*
+ Verifies resource directive
+ Author: PRP
+ From Test Case resource: 26.cc
+*/
+#include "systemc.h"
+#include "test.h"
+
+void test::entry()
+{
+ int i,j,y,z;
+
+
+ YY: for (i = 0; i < 7; i++)
+ {
+ y = i - 1;
+ j = i + 2;
+ }
+
+ o1 = y + j;
+ wait();
+
+
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.f
new file mode 100644
index 000000000..0ff8be826
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.f
@@ -0,0 +1,4 @@
+test2/test.cpp
+test2/tb.cpp
+test2/monitor.cpp
+test2/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.h
new file mode 100644
index 000000000..5596f1f8d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( test )
+{
+ SC_HAS_PROCESS( test );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Output Data Ports
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ test (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/define.h
new file mode 100644
index 000000000..d671993cd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/define.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ define.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#define CLOCK_PERIOD 100
+#define TB_CLOCK_PERIOD 50
+#define DUTY_CYCLE 0.5
+#define EVENT_TIME 50
+#define TEST_TIME 50
+
+#define long_wait wait(10)
+#define single_cycle wait(2)
+#define set_value(var,val) wait(); var = val; wait()
+#define test_value(actual, expected) \
+ wait (); if (expected != actual) \
+ cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl; \
+ wait ()
+#define test_value_now(actual, expected) \
+ if (expected != actual) cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl;
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/golden/test.log
new file mode 100644
index 000000000..510bd7f39
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/golden/test.log
@@ -0,0 +1,5 @@
+SystemC Simulation
+Begin Simulation
+End Simulation
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/main.cpp
new file mode 100644
index 000000000..852905b57
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/main.cpp
@@ -0,0 +1,80 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+// Main routine
+
+#include "systemc.h"
+#include "test.h"
+#include "tb.h"
+#include "monitor.h"
+#include "define.h"
+
+int sc_main(int ac, char *av[])
+{
+ sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
+
+ sc_signal<bool> reset_sig;
+
+ sc_signal<int> i1;
+ sc_signal<int> i2;
+ sc_signal<int> i3;
+ sc_signal<int> i4;
+ sc_signal<int> i5;
+
+ sc_signal<bool> cont1;
+ sc_signal<bool> cont2;
+ sc_signal<bool> cont3;
+
+ sc_signal<int> o1;
+ sc_signal<int> o2;
+ sc_signal<int> o3;
+ sc_signal<int> o4;
+ sc_signal<int> o5;
+
+ test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+
+ // Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.cpp
new file mode 100644
index 000000000..103437eee
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.cpp
@@ -0,0 +1,56 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "monitor.h"
+
+void monitor::entry()
+{
+ int cycleNo = 0;
+
+ while (true) {
+ cout << "[Cycle No: " << cycleNo << "]" <<
+ " i1 = " << i1 <<
+ " o1 = " << o1 <<
+ " o2 = " << o2 <<
+ " cont1 = " << cont1 <<
+ endl;
+ cycleNo++;
+ wait();
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.h
new file mode 100644
index 000000000..a827f7c8a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for monitor process
+ Author: PRP
+ */
+
+SC_MODULE( monitor )
+{
+ SC_HAS_PROCESS( monitor );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ monitor (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.cpp
new file mode 100644
index 000000000..dfc57d75a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "tb.h"
+#include "define.h"
+
+void tb::entry()
+{
+ cout << "Begin Simulation" << endl;
+
+
+ cout << "End Simulation" << endl;
+
+ sc_stop();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.h
new file mode 100644
index 000000000..5e76fb35d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test bench
+ Author: PRP
+ */
+
+SC_MODULE( tb )
+{
+ SC_HAS_PROCESS( tb );
+
+ sc_in_clk clk;
+
+ // Output Reset Port
+ sc_signal<bool>& reset_sig;
+
+ // Output Data Ports
+ sc_signal<int>& i1;
+ sc_signal<int>& i2;
+ sc_signal<int>& i3;
+ sc_signal<int>& i4;
+ sc_signal<int>& i5;
+
+ // Output Control Ports
+ sc_signal<bool>& cont1;
+ sc_signal<bool>& cont2;
+ sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ tb (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ sc_signal<bool>& RESET_SIG,
+
+ sc_signal<int>& I1,
+ sc_signal<int>& I2,
+ sc_signal<int>& I3,
+ sc_signal<int>& I4,
+ sc_signal<int>& I5,
+
+ sc_signal<bool>& CONT1,
+ sc_signal<bool>& CONT2,
+ sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.cpp
new file mode 100644
index 000000000..0e7dea5fe
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.cpp
@@ -0,0 +1,61 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/*
+ Verifies resource directive
+ Author: PRP
+ From Test Case resource: 28.cc
+*/
+#include "systemc.h"
+#include "test.h"
+
+void test::entry()
+{
+ int i,j,y,z;
+
+
+ YY: for (i = 0; i < 7; i++)
+ {
+ y = i - 1;
+ j = i + 2;
+ }
+ o1 = y + j;
+
+ wait();
+
+
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.f
new file mode 100644
index 000000000..f4bc5ed9f
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.f
@@ -0,0 +1,4 @@
+test3/test.cpp
+test3/tb.cpp
+test3/monitor.cpp
+test3/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.h
new file mode 100644
index 000000000..5596f1f8d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( test )
+{
+ SC_HAS_PROCESS( test );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Output Data Ports
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ test (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/define.h
new file mode 100644
index 000000000..d671993cd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/define.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ define.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#define CLOCK_PERIOD 100
+#define TB_CLOCK_PERIOD 50
+#define DUTY_CYCLE 0.5
+#define EVENT_TIME 50
+#define TEST_TIME 50
+
+#define long_wait wait(10)
+#define single_cycle wait(2)
+#define set_value(var,val) wait(); var = val; wait()
+#define test_value(actual, expected) \
+ wait (); if (expected != actual) \
+ cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl; \
+ wait ()
+#define test_value_now(actual, expected) \
+ if (expected != actual) cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl;
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/golden/test.log
new file mode 100644
index 000000000..510bd7f39
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/golden/test.log
@@ -0,0 +1,5 @@
+SystemC Simulation
+Begin Simulation
+End Simulation
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/main.cpp
new file mode 100644
index 000000000..852905b57
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/main.cpp
@@ -0,0 +1,80 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+// Main routine
+
+#include "systemc.h"
+#include "test.h"
+#include "tb.h"
+#include "monitor.h"
+#include "define.h"
+
+int sc_main(int ac, char *av[])
+{
+ sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
+
+ sc_signal<bool> reset_sig;
+
+ sc_signal<int> i1;
+ sc_signal<int> i2;
+ sc_signal<int> i3;
+ sc_signal<int> i4;
+ sc_signal<int> i5;
+
+ sc_signal<bool> cont1;
+ sc_signal<bool> cont2;
+ sc_signal<bool> cont3;
+
+ sc_signal<int> o1;
+ sc_signal<int> o2;
+ sc_signal<int> o3;
+ sc_signal<int> o4;
+ sc_signal<int> o5;
+
+ test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+
+ // Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.cpp
new file mode 100644
index 000000000..103437eee
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.cpp
@@ -0,0 +1,56 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "monitor.h"
+
+void monitor::entry()
+{
+ int cycleNo = 0;
+
+ while (true) {
+ cout << "[Cycle No: " << cycleNo << "]" <<
+ " i1 = " << i1 <<
+ " o1 = " << o1 <<
+ " o2 = " << o2 <<
+ " cont1 = " << cont1 <<
+ endl;
+ cycleNo++;
+ wait();
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.h
new file mode 100644
index 000000000..a827f7c8a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for monitor process
+ Author: PRP
+ */
+
+SC_MODULE( monitor )
+{
+ SC_HAS_PROCESS( monitor );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ monitor (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.cpp
new file mode 100644
index 000000000..dfc57d75a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "tb.h"
+#include "define.h"
+
+void tb::entry()
+{
+ cout << "Begin Simulation" << endl;
+
+
+ cout << "End Simulation" << endl;
+
+ sc_stop();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.h
new file mode 100644
index 000000000..5e76fb35d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test bench
+ Author: PRP
+ */
+
+SC_MODULE( tb )
+{
+ SC_HAS_PROCESS( tb );
+
+ sc_in_clk clk;
+
+ // Output Reset Port
+ sc_signal<bool>& reset_sig;
+
+ // Output Data Ports
+ sc_signal<int>& i1;
+ sc_signal<int>& i2;
+ sc_signal<int>& i3;
+ sc_signal<int>& i4;
+ sc_signal<int>& i5;
+
+ // Output Control Ports
+ sc_signal<bool>& cont1;
+ sc_signal<bool>& cont2;
+ sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ tb (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ sc_signal<bool>& RESET_SIG,
+
+ sc_signal<int>& I1,
+ sc_signal<int>& I2,
+ sc_signal<int>& I3,
+ sc_signal<int>& I4,
+ sc_signal<int>& I5,
+
+ sc_signal<bool>& CONT1,
+ sc_signal<bool>& CONT2,
+ sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.cpp
new file mode 100644
index 000000000..1be7a4d86
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.cpp
@@ -0,0 +1,61 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/*
+ Verifies resource directive
+ Author: PRP
+ From Test Case resource: 29.cc
+*/
+#include "systemc.h"
+#include "test.h"
+
+void test::entry()
+{
+ int i,j,y,z;
+
+
+ YY: for (i = 0; i < 7; i++)
+ {
+ y = i - 1;
+ j = i + 2;
+ }
+ o1 = y + j;
+
+ wait();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.f
new file mode 100644
index 000000000..4ac7cda08
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.f
@@ -0,0 +1,4 @@
+test4/test.cpp
+test4/tb.cpp
+test4/monitor.cpp
+test4/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.h
new file mode 100644
index 000000000..5596f1f8d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( test )
+{
+ SC_HAS_PROCESS( test );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Output Data Ports
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ test (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/define.h
new file mode 100644
index 000000000..d671993cd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/define.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ define.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#define CLOCK_PERIOD 100
+#define TB_CLOCK_PERIOD 50
+#define DUTY_CYCLE 0.5
+#define EVENT_TIME 50
+#define TEST_TIME 50
+
+#define long_wait wait(10)
+#define single_cycle wait(2)
+#define set_value(var,val) wait(); var = val; wait()
+#define test_value(actual, expected) \
+ wait (); if (expected != actual) \
+ cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl; \
+ wait ()
+#define test_value_now(actual, expected) \
+ if (expected != actual) cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl;
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/golden/test.log
new file mode 100644
index 000000000..510bd7f39
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/golden/test.log
@@ -0,0 +1,5 @@
+SystemC Simulation
+Begin Simulation
+End Simulation
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/main.cpp
new file mode 100644
index 000000000..852905b57
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/main.cpp
@@ -0,0 +1,80 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+// Main routine
+
+#include "systemc.h"
+#include "test.h"
+#include "tb.h"
+#include "monitor.h"
+#include "define.h"
+
+int sc_main(int ac, char *av[])
+{
+ sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
+
+ sc_signal<bool> reset_sig;
+
+ sc_signal<int> i1;
+ sc_signal<int> i2;
+ sc_signal<int> i3;
+ sc_signal<int> i4;
+ sc_signal<int> i5;
+
+ sc_signal<bool> cont1;
+ sc_signal<bool> cont2;
+ sc_signal<bool> cont3;
+
+ sc_signal<int> o1;
+ sc_signal<int> o2;
+ sc_signal<int> o3;
+ sc_signal<int> o4;
+ sc_signal<int> o5;
+
+ test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+
+ // Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.cpp
new file mode 100644
index 000000000..103437eee
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.cpp
@@ -0,0 +1,56 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "monitor.h"
+
+void monitor::entry()
+{
+ int cycleNo = 0;
+
+ while (true) {
+ cout << "[Cycle No: " << cycleNo << "]" <<
+ " i1 = " << i1 <<
+ " o1 = " << o1 <<
+ " o2 = " << o2 <<
+ " cont1 = " << cont1 <<
+ endl;
+ cycleNo++;
+ wait();
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.h
new file mode 100644
index 000000000..a827f7c8a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for monitor process
+ Author: PRP
+ */
+
+SC_MODULE( monitor )
+{
+ SC_HAS_PROCESS( monitor );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ monitor (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.cpp
new file mode 100644
index 000000000..dfc57d75a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "tb.h"
+#include "define.h"
+
+void tb::entry()
+{
+ cout << "Begin Simulation" << endl;
+
+
+ cout << "End Simulation" << endl;
+
+ sc_stop();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.h
new file mode 100644
index 000000000..5e76fb35d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test bench
+ Author: PRP
+ */
+
+SC_MODULE( tb )
+{
+ SC_HAS_PROCESS( tb );
+
+ sc_in_clk clk;
+
+ // Output Reset Port
+ sc_signal<bool>& reset_sig;
+
+ // Output Data Ports
+ sc_signal<int>& i1;
+ sc_signal<int>& i2;
+ sc_signal<int>& i3;
+ sc_signal<int>& i4;
+ sc_signal<int>& i5;
+
+ // Output Control Ports
+ sc_signal<bool>& cont1;
+ sc_signal<bool>& cont2;
+ sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ tb (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ sc_signal<bool>& RESET_SIG,
+
+ sc_signal<int>& I1,
+ sc_signal<int>& I2,
+ sc_signal<int>& I3,
+ sc_signal<int>& I4,
+ sc_signal<int>& I5,
+
+ sc_signal<bool>& CONT1,
+ sc_signal<bool>& CONT2,
+ sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.cpp
new file mode 100644
index 000000000..d579684ab
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.cpp
@@ -0,0 +1,62 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/*
+ Verifies resource directive
+ Author: PRP
+ From Test Case resource: 30.cc
+*/
+#include "systemc.h"
+#include "test.h"
+
+void test::entry()
+{
+ int i,j,y,z;
+
+
+ YY: for (i = 0; i < 7; i++)
+ {
+ y = i - 1;
+ j = i + 2;
+ }
+ y = i - 1;
+ j = i + 2;
+ o1 = y + j;
+
+ wait();
+
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.f
new file mode 100644
index 000000000..48933f17e
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.f
@@ -0,0 +1,4 @@
+test5/test.cpp
+test5/tb.cpp
+test5/monitor.cpp
+test5/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.h
new file mode 100644
index 000000000..5596f1f8d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( test )
+{
+ SC_HAS_PROCESS( test );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Output Data Ports
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ test (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/define.h
new file mode 100644
index 000000000..d671993cd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/define.h
@@ -0,0 +1,55 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ define.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#define CLOCK_PERIOD 100
+#define TB_CLOCK_PERIOD 50
+#define DUTY_CYCLE 0.5
+#define EVENT_TIME 50
+#define TEST_TIME 50
+
+#define long_wait wait(10)
+#define single_cycle wait(2)
+#define set_value(var,val) wait(); var = val; wait()
+#define test_value(actual, expected) \
+ wait (); if (expected != actual) \
+ cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl; \
+ wait ()
+#define test_value_now(actual, expected) \
+ if (expected != actual) cout << "Mismatch. Expected: " << expected \
+ << ". Actual: " << actual << endl;
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/golden/test.log
new file mode 100644
index 000000000..510bd7f39
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/golden/test.log
@@ -0,0 +1,5 @@
+SystemC Simulation
+Begin Simulation
+End Simulation
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/main.cpp
new file mode 100644
index 000000000..852905b57
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/main.cpp
@@ -0,0 +1,80 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+// Main routine
+
+#include "systemc.h"
+#include "test.h"
+#include "tb.h"
+#include "monitor.h"
+#include "define.h"
+
+int sc_main(int ac, char *av[])
+{
+ sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS);
+ sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS);
+
+ sc_signal<bool> reset_sig;
+
+ sc_signal<int> i1;
+ sc_signal<int> i2;
+ sc_signal<int> i3;
+ sc_signal<int> i4;
+ sc_signal<int> i5;
+
+ sc_signal<bool> cont1;
+ sc_signal<bool> cont2;
+ sc_signal<bool> cont3;
+
+ sc_signal<int> o1;
+ sc_signal<int> o2;
+ sc_signal<int> o3;
+ sc_signal<int> o4;
+ sc_signal<int> o5;
+
+ test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+ monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5,
+ cont1, cont2, cont3, o1, o2, o3, o4, o5);
+
+ // Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.cpp
new file mode 100644
index 000000000..103437eee
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.cpp
@@ -0,0 +1,56 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "monitor.h"
+
+void monitor::entry()
+{
+ int cycleNo = 0;
+
+ while (true) {
+ cout << "[Cycle No: " << cycleNo << "]" <<
+ " i1 = " << i1 <<
+ " o1 = " << o1 <<
+ " o2 = " << o2 <<
+ " cont1 = " << cont1 <<
+ endl;
+ cycleNo++;
+ wait();
+ }
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.h
new file mode 100644
index 000000000..a827f7c8a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ monitor.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for monitor process
+ Author: PRP
+ */
+
+SC_MODULE( monitor )
+{
+ SC_HAS_PROCESS( monitor );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ monitor (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.cpp
new file mode 100644
index 000000000..dfc57d75a
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.cpp
@@ -0,0 +1,52 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "tb.h"
+#include "define.h"
+
+void tb::entry()
+{
+ cout << "Begin Simulation" << endl;
+
+
+ cout << "End Simulation" << endl;
+
+ sc_stop();
+
+}
+
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.h
new file mode 100644
index 000000000..5e76fb35d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ tb.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test bench
+ Author: PRP
+ */
+
+SC_MODULE( tb )
+{
+ SC_HAS_PROCESS( tb );
+
+ sc_in_clk clk;
+
+ // Output Reset Port
+ sc_signal<bool>& reset_sig;
+
+ // Output Data Ports
+ sc_signal<int>& i1;
+ sc_signal<int>& i2;
+ sc_signal<int>& i3;
+ sc_signal<int>& i4;
+ sc_signal<int>& i5;
+
+ // Output Control Ports
+ sc_signal<bool>& cont1;
+ sc_signal<bool>& cont2;
+ sc_signal<bool>& cont3;
+
+ // Input Data Ports
+ const sc_signal<int>& o1;
+ const sc_signal<int>& o2;
+ const sc_signal<int>& o3;
+ const sc_signal<int>& o4;
+ const sc_signal<int>& o5;
+
+ // Constructor
+ tb (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ sc_signal<bool>& RESET_SIG,
+
+ sc_signal<int>& I1,
+ sc_signal<int>& I2,
+ sc_signal<int>& I3,
+ sc_signal<int>& I4,
+ sc_signal<int>& I5,
+
+ sc_signal<bool>& CONT1,
+ sc_signal<bool>& CONT2,
+ sc_signal<bool>& CONT3,
+
+ const sc_signal<int>& O1,
+ const sc_signal<int>& O2,
+ const sc_signal<int>& O3,
+ const sc_signal<int>& O4,
+ const sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.cpp
new file mode 100644
index 000000000..485e38bcf
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.cpp
@@ -0,0 +1,60 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/*
+ Verifies resource directive
+ Author: PRP
+ From Test Case resource: 31.cc
+*/
+#include "systemc.h"
+#include "test.h"
+
+void test::entry()
+{
+ int i;
+ int a[10], b[12];
+
+ for (i = 0; i < 10; i++) {
+ a[i] = 7;
+ b[i] = 6;
+ }
+
+ wait();
+ o1 = b[i];
+ wait();
+
+}
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.f
new file mode 100644
index 000000000..208a2e652
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.f
@@ -0,0 +1,4 @@
+test6/test.cpp
+test6/tb.cpp
+test6/monitor.cpp
+test6/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.h
new file mode 100644
index 000000000..5596f1f8d
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.h
@@ -0,0 +1,102 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ test.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/* Common interface file for test cases
+ Author: PRP
+ */
+
+SC_MODULE( test )
+{
+ SC_HAS_PROCESS( test );
+
+ sc_in_clk clk;
+
+ // Input Reset Port
+ const sc_signal<bool>& reset_sig;
+
+ // Input Data Ports
+ const sc_signal<int>& i1;
+ const sc_signal<int>& i2;
+ const sc_signal<int>& i3;
+ const sc_signal<int>& i4;
+ const sc_signal<int>& i5;
+
+ // Input Control Ports
+ const sc_signal<bool>& cont1;
+ const sc_signal<bool>& cont2;
+ const sc_signal<bool>& cont3;
+
+ // Output Data Ports
+ sc_signal<int>& o1;
+ sc_signal<int>& o2;
+ sc_signal<int>& o3;
+ sc_signal<int>& o4;
+ sc_signal<int>& o5;
+
+ // Constructor
+ test (
+ sc_module_name NAME,
+ sc_clock& CLK,
+
+ const sc_signal<bool>& RESET_SIG,
+
+ const sc_signal<int>& I1,
+ const sc_signal<int>& I2,
+ const sc_signal<int>& I3,
+ const sc_signal<int>& I4,
+ const sc_signal<int>& I5,
+
+ const sc_signal<bool>& CONT1,
+ const sc_signal<bool>& CONT2,
+ const sc_signal<bool>& CONT3,
+
+ sc_signal<int>& O1,
+ sc_signal<int>& O2,
+ sc_signal<int>& O3,
+ sc_signal<int>& O4,
+ sc_signal<int>& O5)
+ : reset_sig(RESET_SIG), i1(I1), i2(I2),
+ i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2),
+ cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset_sig,true);
+ }
+
+ void entry();
+};