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-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/common.h46
-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/display.cpp60
-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/display.h70
-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/golden/prime_flag.log18
-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/main.cpp67
-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/prime_flag.f4
-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.cpp93
-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.h75
-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/reset.cpp53
-rw-r--r--src/systemc/tests/systemc/misc/synth/prime_flag/reset.h67
10 files changed, 553 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/common.h b/src/systemc/tests/systemc/misc/synth/prime_flag/common.h
new file mode 100644
index 000000000..c868bf6a6
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/common.h
@@ -0,0 +1,46 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ common.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#ifndef COMMON_H
+#define COMMON_H
+
+#include "systemc.h"
+
+typedef sc_bv<16> bool_vector;
+typedef sc_signal<bool_vector> signal_bool_vector;
+
+#endif
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/display.cpp b/src/systemc/tests/systemc/misc/synth/prime_flag/display.cpp
new file mode 100644
index 000000000..e4f8ae94e
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/display.cpp
@@ -0,0 +1,60 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ display.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+ /*****************************************/
+ /* Implementation Filename: display.cc */
+ /*****************************************/
+
+#include "display.h"
+
+void displayp::entry()
+{
+ bool_vector last_prime;
+
+ while (true) {
+
+ last_prime = prime.read();
+ wait();
+
+ do { wait(); } while (prime_ready == 0);
+ cout << prime.read().to_uint() << endl;
+
+ if (prime.read().to_uint() > 40) {
+ sc_stop();
+ }
+ }
+}
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/display.h b/src/systemc/tests/systemc/misc/synth/prime_flag/display.h
new file mode 100644
index 000000000..44b7a90dd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/display.h
@@ -0,0 +1,70 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ display.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+ /***************************************/
+ /* Interface Filename: display.h */
+ /***************************************/
+
+#include "common.h"
+
+SC_MODULE( displayp )
+{
+ SC_HAS_PROCESS( displayp );
+
+ sc_in_clk clk;
+
+ // Inputs
+ const sc_signal<bool>& prime_ready;
+ const signal_bool_vector& prime;
+
+ // Constructor
+ displayp (sc_module_name NAME,
+ sc_clock& TICK,
+ const sc_signal<bool>& PRIME_READY,
+ const signal_bool_vector& PRIME )
+
+ :
+ prime_ready (PRIME_READY),
+ prime (PRIME)
+
+ {
+ clk (TICK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/golden/prime_flag.log b/src/systemc/tests/systemc/misc/synth/prime_flag/golden/prime_flag.log
new file mode 100644
index 000000000..147abf5fd
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/golden/prime_flag.log
@@ -0,0 +1,18 @@
+SystemC Simulation
+1
+Terminating process T1.entry
+2
+3
+5
+7
+11
+13
+17
+19
+23
+29
+31
+37
+41
+
+Info: /OSCI/SystemC: Simulation stopped by user.
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/main.cpp b/src/systemc/tests/systemc/misc/synth/prime_flag/main.cpp
new file mode 100644
index 000000000..cf63b5e05
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/main.cpp
@@ -0,0 +1,67 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ main.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+ /***************************************/
+ /* Main Filename: main.cc */
+ /***************************************/
+
+#include "reset.h"
+#include "display.h"
+#include "prime_numgen.h"
+
+int sc_main(int ac, char *av[])
+{
+
+// Signal Instantiation
+ sc_signal<bool> reset ("reset");
+ sc_signal<bool> prime_ready ("prime_ready");
+ signal_bool_vector prime ("prime");
+
+// Clock Instantiation
+ sc_clock clk ("CLK", 6, SC_NS, 0.5, 10, SC_NS, false); // 167 Mhz
+
+// Process Instantiation
+ prime_numgen D1 ("D1", clk, reset, prime_ready, prime);
+
+ resetp T1 ("T1", clk, reset);
+
+ displayp T2 ("T2", clk, prime_ready, prime);
+
+// Simulation Run Control
+ sc_start();
+ return 0;
+}
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/prime_flag.f b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_flag.f
new file mode 100644
index 000000000..baf7285c1
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_flag.f
@@ -0,0 +1,4 @@
+prime_flag/reset.cpp
+prime_flag/display.cpp
+prime_flag/prime_numgen.cpp
+prime_flag/main.cpp
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.cpp b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.cpp
new file mode 100644
index 000000000..07c937abe
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.cpp
@@ -0,0 +1,93 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ prime_numgen.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+/******************************************************************************/
+/*** Prime Number Generator ***/
+/*** Implementation Filename: prime_numgen.cc ***/
+/******************************************************************************/
+
+#include "prime_numgen.h"
+
+void prime_numgen::entry()
+{
+
+ static unsigned int p2 = 1,
+ p3 = 0,
+ p5 = 0,
+ p7 = 0,
+ p11 = 0,
+ p13 = 0,
+ p17 = 0,
+ p19 = 0,
+ p23 = 0,
+ p29 = 0;
+
+ // HANDSHAKING
+ prime_ready.write(0);
+ wait();
+
+ // COMPUTE LOOP
+ while (true) {
+
+ // PRINT prime IF ALL OTHER VALUES ARE ZERO AND p2 IS NONZERO
+ if (p2 && !p3 && !p5 && !p7 && !p11 && !p13 && !p17 && !p19 && !p23 && !p29)
+ {
+ prime_ready.write(1);
+ prime.write(p2); // Printing prime value p2
+ wait();
+
+ prime_ready.write(0);
+ }
+ wait();
+
+ // DETERMINE NEW PRIME NUMBER
+ if (p7 && p13) { p7--, p13--, p17++; }
+ else if (p5 && p17) { p5--, p17--, p2++, p3++, p13++; }
+ else if (p3 && p17) { p3--, p17--, p19++; }
+ else if (p2 && p19) { p2--, p19--, p23++; }
+ else if (p3 && p11) { p3--, p11--, p29++; }
+ else if (p29) { p29--, p7++, p11++; }
+ else if (p23) { p23--, p5++, p19++; }
+ else if (p19) { p19--, p7++, p11++; }
+ else if (p17) { p17 = 0; }
+ else if (p13) { p13--, p11++; }
+ else if (p11) { p11--, p13++; }
+ else if (p2 && p7) { p2--, p7--, p3++, p5++; }
+ else if (p2) { p2--, p3++, p5++; }
+ else { p5++, p11++; }
+ }
+}
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.h b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.h
new file mode 100644
index 000000000..f01ea57bf
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.h
@@ -0,0 +1,75 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ prime_numgen.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+ /***************************************/
+ /* Interface Filename: prime_numgen.h */
+ /***************************************/
+
+#include "common.h"
+
+SC_MODULE( prime_numgen )
+{
+ SC_HAS_PROCESS( prime_numgen );
+
+ sc_in_clk clk;
+
+ // Inputs
+ const sc_signal<bool>& reset;
+ // Outputs
+ sc_signal<bool>& prime_ready;
+ signal_bool_vector& prime;
+
+ // Constructor
+ prime_numgen (sc_module_name NAME,
+ sc_clock& TICK,
+ const sc_signal<bool>& RESET,
+ sc_signal<bool>& PRIME_READY,
+ signal_bool_vector& PRIME )
+
+ :
+ reset (RESET),
+ prime_ready (PRIME_READY),
+ prime (PRIME)
+
+ {
+ clk (TICK);
+ SC_CTHREAD( entry, clk.pos() );
+ reset_signal_is(reset,false);
+ }
+
+ void entry();
+};
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/reset.cpp b/src/systemc/tests/systemc/misc/synth/prime_flag/reset.cpp
new file mode 100644
index 000000000..43e3ce8d8
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/reset.cpp
@@ -0,0 +1,53 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ reset.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+ /***************************************/
+ /* Implementation Filename: reset.cc */
+ /***************************************/
+
+#include "reset.h"
+
+void resetp::entry()
+{
+ reset.write(0);
+ wait(3);
+
+ reset.write(1);
+ wait();
+
+ halt();
+}
diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/reset.h b/src/systemc/tests/systemc/misc/synth/prime_flag/reset.h
new file mode 100644
index 000000000..c918604e5
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/synth/prime_flag/reset.h
@@ -0,0 +1,67 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ reset.h --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+ /***************************************/
+ /* Interface Filename: reset.h */
+ /***************************************/
+
+#include "common.h"
+
+SC_MODULE( resetp )
+{
+ SC_HAS_PROCESS( resetp );
+
+ sc_in_clk clk;
+
+ // Outputs
+ sc_signal<bool>& reset;
+
+ // Constructor
+ resetp (sc_module_name NAME,
+ sc_clock& TICK,
+ sc_signal<bool>& RESET )
+
+ :
+ reset (RESET)
+
+ {
+ clk (TICK);
+ SC_CTHREAD( entry, clk.neg() );
+ }
+
+ void entry();
+};