diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/synth/wait_until/misc')
18 files changed, 1089 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/golden/test1.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/golden/test1.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/golden/test1.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test.h new file mode 100644 index 000000000..4a591ce30 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test1.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test1.cpp new file mode 100644 index 000000000..4ff400163 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test1.cpp @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test1.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + wait (); + + do { wait(); } while (cont1 == 0); + + + +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/golden/test2.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/golden/test2.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/golden/test2.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test.h new file mode 100644 index 000000000..4a591ce30 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test2.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test2.cpp new file mode 100644 index 000000000..e128e0372 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test2.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test2.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + while (1) { + do { wait(); } while (cont1 == 0); + if (i2 == 1) + break; + /* error: wait needs to be inserted between do { wait(); } while + and break */ + } + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/golden/test3.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/golden/test3.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/golden/test3.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test.h new file mode 100644 index 000000000..5bd25d99e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test3.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test3.cpp new file mode 100644 index 000000000..411e2f4e7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test3.cpp @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test3.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + while (1) { + if (i2 == 1) + continue; + /* error: do { wait(); } while transformation does not allow continue stmt + before it if no wait follows the do { wait(); } while */ + do { wait(); } while (cont1 == 0); + if (i2 == 1) + break; + } + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/golden/test4.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/golden/test4.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/golden/test4.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test.h new file mode 100644 index 000000000..5bd25d99e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test4.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test4.cpp new file mode 100644 index 000000000..d8c42acd3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test4.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test4.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + if (i1 == 1) { + while (i1 == 1) { + do { wait(); } while (cont1 == 1); + } + } else { + wait(); + } + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/golden/test5.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/golden/test5.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/golden/test5.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test.h new file mode 100644 index 000000000..5bd25d99e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test5.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test5.cpp new file mode 100644 index 000000000..74a0f56e2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test5.cpp @@ -0,0 +1,179 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test5.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + /* error: control nesting too deep - error reported in siu_do { wait(); } while .c */ + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) +#if !defined( _MSC_VER ) + // running into limitations of VC6 here + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) +#endif + wait(); + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/golden/test6.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/golden/test6.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/golden/test6.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test1.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test1.h new file mode 100644 index 000000000..570465d8e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test1.h @@ -0,0 +1,105 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test1.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); + void a(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test6.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test6.cpp new file mode 100644 index 000000000..3f1f002d4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test6.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test6.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test1.h" + +void t::a() +{ + do { wait(); } while (cont1 == 1); + +} + +void t::entry() +{ + a(); + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} |