diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/synth/wait_until/test09')
10 files changed, 619 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test09/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.cpp new file mode 100644 index 000000000..2a4edae69 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 53.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + + wait(); + while (i1 < 4) { + o1 = 0; + wait (); + do { wait(); } while (cont2 != 1); + o1 = 1; + wait (); + } + wait(); + + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.f new file mode 100644 index 000000000..1dd8094ef --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.f @@ -0,0 +1,4 @@ +test09/test.cpp +test09/tb.cpp +test09/monitor.cpp +test09/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; |