diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/synth/wait_until')
186 files changed, 11670 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/golden/test1.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/golden/test1.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/golden/test1.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test.h new file mode 100644 index 000000000..4a591ce30 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test1.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test1.cpp new file mode 100644 index 000000000..4ff400163 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test1.cpp @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test1.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + wait (); + + do { wait(); } while (cont1 == 0); + + + +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/golden/test2.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/golden/test2.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/golden/test2.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test.h new file mode 100644 index 000000000..4a591ce30 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test2.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test2.cpp new file mode 100644 index 000000000..e128e0372 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test2.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test2.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + while (1) { + do { wait(); } while (cont1 == 0); + if (i2 == 1) + break; + /* error: wait needs to be inserted between do { wait(); } while + and break */ + } + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/golden/test3.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/golden/test3.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/golden/test3.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test.h new file mode 100644 index 000000000..5bd25d99e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test3.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test3.cpp new file mode 100644 index 000000000..411e2f4e7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test3.cpp @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test3.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + while (1) { + if (i2 == 1) + continue; + /* error: do { wait(); } while transformation does not allow continue stmt + before it if no wait follows the do { wait(); } while */ + do { wait(); } while (cont1 == 0); + if (i2 == 1) + break; + } + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/golden/test4.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/golden/test4.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/golden/test4.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test.h new file mode 100644 index 000000000..5bd25d99e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test4.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test4.cpp new file mode 100644 index 000000000..d8c42acd3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test4.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test4.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + if (i1 == 1) { + while (i1 == 1) { + do { wait(); } while (cont1 == 1); + } + } else { + wait(); + } + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/golden/test5.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/golden/test5.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/golden/test5.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test.h new file mode 100644 index 000000000..5bd25d99e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test5.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test5.cpp new file mode 100644 index 000000000..74a0f56e2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test5.cpp @@ -0,0 +1,179 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test5.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + /* error: control nesting too deep - error reported in siu_do { wait(); } while .c */ + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) +#if !defined( _MSC_VER ) + // running into limitations of VC6 here + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) +#endif + wait(); + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/golden/test6.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/golden/test6.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/golden/test6.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test1.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test1.h new file mode 100644 index 000000000..570465d8e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test1.h @@ -0,0 +1,105 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test1.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); + void a(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test6.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test6.cpp new file mode 100644 index 000000000..3f1f002d4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test6.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test6.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test1.h" + +void t::a() +{ + do { wait(); } while (cont1 == 1); + +} + +void t::entry() +{ + a(); + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test01/define.h new file mode 100644 index 000000000..9b4c36e61 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/define.h @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(5*CLOCK_PERIOD) +#define single_cycle wait() +#define set_value(var,val) wait(EVENT_TIME); var = val; wait(CLOCK_PERIOD - EVENT_TIME) +#define test_value(actual, expected) \ + wait (TEST_TIME); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait (CLOCK_PERIOD - TEST_TIME) +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test01/golden/test.log new file mode 100644 index 000000000..d75ef208f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/golden/test.log @@ -0,0 +1,4 @@ +SystemC Simulation +Begin Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test01/main.cpp new file mode 100644 index 000000000..b754b436b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/main.cpp @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.cpp new file mode 100644 index 000000000..7c819fbf9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + reset_sig = 1; + cont1 = 0; + single_cycle; + single_cycle; + reset_sig = 0; + + long_wait; + + set_value(cont1,1); + single_cycle; + test_value(o1.read(),4); + long_wait; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.cpp new file mode 100644 index 000000000..ca94c1583 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + wait(); + wait (); + do { wait(); } while (cont1 == 1); + wait (); + o1 = 4; + wait (); + wait (); + wait (); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.f new file mode 100644 index 000000000..18d0009a8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.f @@ -0,0 +1,3 @@ +test01/test.cpp +test01/tb.cpp +test01/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.h new file mode 100644 index 000000000..56820dca5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test02/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test02/golden/test.log new file mode 100644 index 000000000..ae1be6e37 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/golden/test.log @@ -0,0 +1,30 @@ +SystemC Simulation +Begin Simulation +[Cycle No: 0] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 1] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 2] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 3] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 4] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 5] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 6] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 7] i1 = 5 o1 = 0 o2 = 0 cont1 = 1 +[Cycle No: 8] i1 = 5 o1 = 0 o2 = 0 cont1 = 1 +[Cycle No: 9] i1 = 5 o1 = 0 o2 = 0 cont1 = 1 +[Cycle No: 10] i1 = 5 o1 = 2 o2 = 0 cont1 = 1 +[Cycle No: 11] i1 = 5 o1 = 2 o2 = 3 cont1 = 1 +[Cycle No: 12] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 13] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 14] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 15] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +Mismatch. Expected: 2. Actual: 0 +[Cycle No: 16] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +Mismatch. Expected: 3. Actual: 0 +[Cycle No: 17] i1 = 0 o1 = 2 o2 = 0 cont1 = 0 +[Cycle No: 18] i1 = 0 o1 = 2 o2 = 3 cont1 = 0 +[Cycle No: 19] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 20] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 21] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 22] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test02/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.cpp new file mode 100644 index 000000000..97bb148ec --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + reset_sig = 1; + cont1 = 0; + i1 = 0; + i2 = 0; + single_cycle; + reset_sig = 0; + + i1 = 5; + single_cycle; + single_cycle; + single_cycle; + single_cycle; + single_cycle; + single_cycle; + + set_value(cont1,1); + single_cycle; + single_cycle; + + test_value(o1,2); + test_value(o2,3); + + // 2nd iteration. Test 'else' clause. + i1 = 0; + i2 = 0; + cont1 = 0; + single_cycle; + single_cycle; + single_cycle; + single_cycle; + + test_value(o1,2); + test_value(o2,3); + + long_wait; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.cpp new file mode 100644 index 000000000..bbd1a5933 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + while (true) { + o1 = 0; o2 = 0; + wait(); + wait(); + wait (); + if (i1 == 5) { + do { wait(); } while (cont1 == 0); + wait (); + } else { + wait (); + } + wait (); + o1 = 2; + wait (); + o2 = 3; + wait (); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.f new file mode 100644 index 000000000..030dc67dd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.f @@ -0,0 +1,4 @@ +test02/test.cpp +test02/tb.cpp +test02/monitor.cpp +test02/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test03/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test03/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test03/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.cpp new file mode 100644 index 000000000..92b753daa --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.cpp @@ -0,0 +1,65 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + while (true) { + o1 = 0; + do { wait(); } while (cont1 == 1); + wait(); + wait (); + if (i1 == 5) { + if (i2 == 5) { + do { wait(); } while (cont2 == 1); + wait (); + o1 = 1; + } else { + wait(); + o1 = 2; + } + } else { + wait(); + o1 = 3; + } + wait (); + wait (); + wait (); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.f new file mode 100644 index 000000000..44bca3f91 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.f @@ -0,0 +1,4 @@ +test03/test.cpp +test03/tb.cpp +test03/monitor.cpp +test03/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test04/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test04/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test04/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.cpp new file mode 100644 index 000000000..b10e4c6a7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 1); + wait(); + o1 = 0; + wait (); + if (i1 == 5) { + do { wait(); } while (cont2 == 1); + } else { + wait (); + } + o1 = 6; + wait (); + wait (); + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.f new file mode 100644 index 000000000..2a530a6e3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.f @@ -0,0 +1,4 @@ +test04/test.cpp +test04/tb.cpp +test04/monitor.cpp +test04/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test05/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test05/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test05/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.cpp new file mode 100644 index 000000000..b6a5cc9b0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 1); + wait(); + o1 = 0; + o2 = 0; + o3 = 0; + o4 = 0; + o5 = 0; + wait (); + if (i1 == 5) { + if (i2 == 5) { + if (i3 == 5) { + do { wait(); } while (cont2 == 1); + } else { + wait (); + } + o1 = 9; + o2 = 10; + wait(); + } else { + wait (); + } + o3 = 5; + o4 = 10; + wait(); + wait(); + } else { + wait (); + } + o5 = 6; + wait (); + wait (); + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.f new file mode 100644 index 000000000..a2d56602a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.f @@ -0,0 +1,4 @@ +test05/test.cpp +test05/tb.cpp +test05/monitor.cpp +test05/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test06/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test06/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test06/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.cpp new file mode 100644 index 000000000..8e0b65f6c --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 50.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 0); + wait(); + o1 = 0; + o2 = 0; + o3 = 0; + o4 = 0; + o5 = 0; + wait (); + if (i1 == 5) { + if (i2 == 5) { + if (i3 == 5) { + do { wait(); } while (cont2 == 0); + } else { + wait (); + } + o1 = 9; + o2 = 10; + } else { + wait (); + } + o3 = 5; + o4 = 10; + wait(); + wait(); + } else { + wait (); + } + o5 = 6; + wait (); + wait (); + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.f new file mode 100644 index 000000000..687c574e6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.f @@ -0,0 +1,4 @@ +test06/test.cpp +test06/tb.cpp +test06/monitor.cpp +test06/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test07/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test07/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test07/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.cpp new file mode 100644 index 000000000..5c3f91119 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.cpp @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 51.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 0); + wait(); + o1 = 0; + o2 = 0; + o3 = 0; + o4 = 0; + o5 = 0; + wait (); + if (i1 == 25) { + if (i2 == 15) { + if (i3 == 5) { + wait (); + } else { + if (i4 == 1) { + wait (); + o5 = 2; + } else { + do { wait(); } while (cont2 != 8); + } + } + o1 = 9; + o2 = 10; + } else { + wait(); + wait(); + } + o3 = 5; + o4 = 20; + wait(); + wait(); + } else { + wait(); + } + o5 = 6; + wait (); + wait (); + wait (); + + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.f new file mode 100644 index 000000000..06081cb35 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.f @@ -0,0 +1,4 @@ +test07/test.cpp +test07/tb.cpp +test07/monitor.cpp +test07/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test08/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test08/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test08/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.cpp new file mode 100644 index 000000000..d59304852 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 52.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 0); + wait(); + o1 = 0; + o2 = 0; + o3 = 0; + o4 = 0; + o5 = 0; + wait (); + if (i1 == 25) { + if (i2 == 15) { + if (i3 == 5) { + wait (); + } else { + if (i4 == 1) { + wait (); + o5 = 2; + } else { + do { wait(); } while (cont2 != 8); + wait (); + } + } + o1 = 9; + o2 = 10; + } else { + wait(); + wait(); + } + o3 = 5; + o4 = 20; + wait(); + wait(); + } else { + wait(); + } + o5 = 6; + wait (); + wait (); + wait (); + + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.f new file mode 100644 index 000000000..97efb0322 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.f @@ -0,0 +1,4 @@ +test08/test.cpp +test08/tb.cpp +test08/monitor.cpp +test08/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test09/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.cpp new file mode 100644 index 000000000..2a4edae69 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 53.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + + wait(); + while (i1 < 4) { + o1 = 0; + wait (); + do { wait(); } while (cont2 != 1); + o1 = 1; + wait (); + } + wait(); + + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.f new file mode 100644 index 000000000..1dd8094ef --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.f @@ -0,0 +1,4 @@ +test09/test.cpp +test09/tb.cpp +test09/monitor.cpp +test09/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test10/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test10/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test10/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.cpp new file mode 100644 index 000000000..d6cdb4529 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.cpp @@ -0,0 +1,57 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 54.sc */ +void test::entry() +{ + while (true) { + + wait(); + o1 = 2; + do { wait(); } while (cont1 != 1); + wait(); + while (1) { + wait (); + o1 = i2 + 1; + do { wait(); } while (cont1 != 1); + } + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.f new file mode 100644 index 000000000..328dc35a0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.f @@ -0,0 +1,4 @@ +test10/test.cpp +test10/tb.cpp +test10/monitor.cpp +test10/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test11/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test11/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test11/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.cpp new file mode 100644 index 000000000..4eca67444 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.cpp @@ -0,0 +1,64 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 55.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait(); + if (i2 == 1) + o1 = 9; + else + o1 = 10; + wait (); + switch (i3) { + case 1: o2 = 8; do { wait(); } while (cont2 != 1); break; + case 2: o2 = 9; wait(); break; + case 3: o2 = 10; wait(); break; + default: o2 = 11; wait(); break; + } + wait(); + o1 = 5; + wait(); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.f new file mode 100644 index 000000000..715ba8512 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.f @@ -0,0 +1,4 @@ +test11/test.cpp +test11/tb.cpp +test11/monitor.cpp +test11/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test12/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test12/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test12/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.cpp new file mode 100644 index 000000000..c517882da --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.cpp @@ -0,0 +1,65 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 56.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait(); + o1 = 9; + switch (i3) { + case 1: o2 = 8; + if (i2 > 4) + do { wait(); } while (cont1 != 1); + else + wait(); + break; + case 2: o2 = 9; wait(); break; + case 3: o2 = 10; wait(); break; + default: o2 = 11; wait(); break; + } + wait(); + o1 = 5; + wait(); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.f new file mode 100644 index 000000000..e193e228f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.f @@ -0,0 +1,4 @@ +test12/test.cpp +test12/tb.cpp +test12/monitor.cpp +test12/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test13/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test13/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test13/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.cpp new file mode 100644 index 000000000..26c93fdcf --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.cpp @@ -0,0 +1,90 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 57.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait (); + o1 = 9; + + switch (i5) { + case 1: + if (i2 > 4) { + o2 = 80; + do { wait(); } while (cont2 != 1); + } else { + o2 = 81; + wait(); + } + break; + case 2: + o2 = 9; + if (i4 == 5) { + wait(); wait(); break; + } + else + wait(); + break; + case 3: + o2 = 10; + wait(); + while (i3 < 5) { + wait(); + o3 = i4 + 1; + if (i4 > 7) break; + wait(); + } + wait (); + break; + default: o2 = 11; wait(); break; + } + if (i3 == 3) { + o1 = 4; + wait(); + } else { + o1 = 5; + wait(); + } + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.f new file mode 100644 index 000000000..b12d0f35b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.f @@ -0,0 +1,4 @@ +test13/test.cpp +test13/tb.cpp +test13/monitor.cpp +test13/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test14/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test14/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test14/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.cpp new file mode 100644 index 000000000..5c82a908d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.cpp @@ -0,0 +1,76 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 58.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait(); + o1 = 0; + wait (); + if (i1 > 5) { + if (i2 > 3) { + do { wait(); } while (cont2 != 1); + o1 = 9; + if (i2 > 6) + o2 = 6; + else + o2 = 7; + wait (); + if (i2 > 9) + o2 = 8; + else + o2 = 9; + } else { + o2 = 10; + wait(); + } + } else { + o2 = 11; + wait(); + } + wait (); + o1 = 1; + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.f new file mode 100644 index 000000000..5db160f14 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.f @@ -0,0 +1,4 @@ +test14/test.cpp +test14/tb.cpp +test14/monitor.cpp +test14/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test15/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test15/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test15/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.cpp new file mode 100644 index 000000000..faf5894a1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.cpp @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 59.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait(); + o1 = 5; + do { wait(); } while (cont2 != 1); + o1 = 1; + do { wait(); } while (cont1 != 1); + o1 = 2; + wait (); + o1 = 3; + if (i2 == 5) { + do { wait(); } while (cont2 != 1); + do { wait(); } while (cont1 != 1); + o1 = 4; + wait (); + wait (); + do { wait(); } while (cont2 != 1); + do { wait(); } while (cont1 != 1); + } else { + wait(); + } + o1 = 0; + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.f new file mode 100644 index 000000000..418eb1dff --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.f @@ -0,0 +1,4 @@ +test15/test.cpp +test15/tb.cpp +test15/monitor.cpp +test15/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test16/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test16/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test16/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.cpp new file mode 100644 index 000000000..c85de0a63 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 62.sc */ +void test::entry() +{ + while (true) { + + wait(); + do { wait(); } while (cont1 != 1); + wait(); + o2 = 8; + wait(); + while (i2 < 6) { + wait(); + o1 = 7; + do { wait(); } while (cont2 != 1); + } + wait(); + o2 = 0; + wait(); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.f new file mode 100644 index 000000000..6593d828f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.f @@ -0,0 +1,4 @@ +test16/test.cpp +test16/tb.cpp +test16/monitor.cpp +test16/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test17/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test17/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test17/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.cpp new file mode 100644 index 000000000..ec4680efb --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 61.sc */ +void test::entry() +{ + while (true) { + + wait(); + o1 = 2; + do { wait(); } while (cont1 != 1); + wait(); + if (i3 == 4) { + wait(); + while (1) { + wait (); + o1 = i2 + 1; + do { wait(); } while (cont2 != 2); + } + } else { + wait(); + } + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.f new file mode 100644 index 000000000..b2695ac54 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.f @@ -0,0 +1,4 @@ +test17/test.cpp +test17/tb.cpp +test17/monitor.cpp +test17/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; |