diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/synth')
629 files changed, 41174 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.cpp b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.cpp new file mode 100644 index 000000000..56132f484 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.cpp @@ -0,0 +1,73 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + add_chain.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// $Log: add_chain.cpp,v $ +// Revision 1.2 2011/09/05 21:23:35 acg +// Philipp A. Hartmann: eliminate compiler warnings. +// +// Revision 1.1.1.1 2006/12/15 20:26:13 acg +// systemc_tests-2.3 +// +// Revision 1.4 2006/01/24 21:05:23 acg +// Andy Goodrich: replacement of deprecated features with their non-deprecated +// counterparts. +// +// Revision 1.3 2006/01/20 00:43:19 acg +// Andy Goodrich: Changed over to use putenv() instead of setenv() to accommodate old versions of Solaris. +// +// Revision 1.2 2006/01/19 00:47:26 acg +// Andy Goodrich: Changes for the fact signal write checking is enabled. +// + +#define SC_NO_WRITE_CHECK +#include "systemc.h" +#include "define.h" +#include "display.h" +#include "data_gen.h" +#include "reset_stim.h" +#include "add_chain.h" +#include "tb.h" + +int +sc_main(int ac, char *av[]) +{ + sc_clock clk( "CLOCK", 20, SC_NS, 0.5, 0, SC_NS, false); // Clock function + testbench tb1("TB1", clk ); // Testbench Instance + + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.dat b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.dat new file mode 100644 index 000000000..f6352869f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.dat @@ -0,0 +1,257 @@ +11111111 +00000000 +00000001 +00000010 +00000011 +00000100 +00000101 +00000110 +00000111 +00001000 +00001001 +00001010 +00001011 +00001100 +00001101 +00001110 +00001111 +00010000 +00010001 +00010010 +00010011 +00010100 +00010101 +00010110 +00010111 +00011000 +00011001 +00011010 +00011011 +00011100 +00011101 +00011110 +00011111 +00100000 +00100001 +00100010 +00100011 +00100100 +00100101 +00100110 +00100111 +00101000 +00101001 +00101010 +00101011 +00101100 +00101101 +00101110 +00101111 +00110000 +00110001 +00110010 +00110011 +00110100 +00110101 +00110110 +00110111 +00111000 +00111001 +00111010 +00111011 +00111100 +00111101 +00111110 +00111111 +01000000 +01000001 +01000010 +01000011 +01000100 +01000101 +01000110 +01000111 +01001000 +01001001 +01001010 +01001011 +01001100 +01001101 +01001110 +01001111 +01010000 +01010001 +01010010 +01010011 +01010100 +01010101 +01010110 +01010111 +01011000 +01011001 +01011010 +01011011 +01011100 +01011101 +01011110 +01011111 +01100000 +01100001 +01100010 +01100011 +01100100 +01100101 +01100110 +01100111 +01101000 +01101001 +01101010 +01101011 +01101100 +01101101 +01101110 +01101111 +01110000 +01110001 +01110010 +01110011 +01110100 +01110101 +01110110 +01110111 +01111000 +01111001 +01111010 +01111011 +01111100 +01111101 +01111110 +01111111 +10000000 +10000001 +10000010 +10000011 +10000100 +10000101 +10000110 +10000111 +10001000 +10001001 +10001010 +10001011 +10001100 +10001101 +10001110 +10001111 +10010000 +10010001 +10010010 +10010011 +10010100 +10010101 +10010110 +10010111 +10011000 +10011001 +10011010 +10011011 +10011100 +10011101 +10011110 +10011111 +10100000 +10100001 +10100010 +10100011 +10100100 +10100101 +10100110 +10100111 +10101000 +10101001 +10101010 +10101011 +10101100 +10101101 +10101110 +10101111 +10110000 +10110001 +10110010 +10110011 +10110100 +10110101 +10110110 +10110111 +10111000 +10111001 +10111010 +10111011 +10111100 +10111101 +10111110 +10111111 +11000000 +11000001 +11000010 +11000011 +11000100 +11000101 +11000110 +11000111 +11001000 +11001001 +11001010 +11001011 +11001100 +11001101 +11001110 +11001111 +11010000 +11010001 +11010010 +11010011 +11010100 +11010101 +11010110 +11010111 +11011000 +11011001 +11011010 +11011011 +11011100 +11011101 +11011110 +11011111 +11100000 +11100001 +11100010 +11100011 +11100100 +11100101 +11100110 +11100111 +11101000 +11101001 +11101010 +11101011 +11101100 +11101101 +11101110 +11101111 +11110000 +11110001 +11110010 +11110011 +11110100 +11110101 +11110110 +11110111 +11111000 +11111001 +11111010 +11111011 +11111100 +11111101 +11111110 +11111111 diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.h b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.h new file mode 100644 index 000000000..3162903bb --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/add_chain.h @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + add_chain.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +/******************************************************************************/ +/*************************** add_chain Class Definition ********************/ +/******************************************************************************/ + +SC_MODULE( ADD_CHAIN ) +{ + SC_HAS_PROCESS( ADD_CHAIN ); + + sc_in_clk clk; + + const sc_signal<bool>& rst; + const signal_bool_vector8& a_in; + signal_bool_vector4& sum_out; + sc_signal<bool>& ready; + + ADD_CHAIN( sc_module_name NAME, + sc_clock& TICK_P, + + const sc_signal<bool>& RST, + const signal_bool_vector8& A_IN, + signal_bool_vector4& SUM_OUT, + sc_signal<bool>& READY + ) + : + rst (RST), + a_in (A_IN), + sum_out (SUM_OUT), + ready (READY) + { + clk(TICK_P); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(rst, false); + } + void entry(); +}; + +/******************************************************************************/ +/*************************** add_chain Entry Function **********************/ +/******************************************************************************/ +/** **/ +/** This function sums the number of 1's contained in a 8-bit data stream **/ +/** **/ +/******************************************************************************/ +void +ADD_CHAIN::entry() +{ + bool_vector4 sum; + bool_vector8 a; + + /***** Reset Initialization *****/ + sum_out.write(0); + ready.write(1); + wait(); + + /***** MAIN LOOP *****/ + while(true) { + + /***** Handshake *****/ + ready.write(0); + wait(); + + /***** Computation *****/ + sum = 0; + a = a_in.read(); + + for (int i=0; i<=7; i=i+1) { + sum = sum.to_uint() + a[i].to_bool(); + } + + sum_out.write(sum); + + /***** Handshake *****/ + ready.write(1); + wait(); + } +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/common.h b/src/systemc/tests/systemc/misc/synth/add_chain/common.h new file mode 100644 index 000000000..850b96ab7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/common.h @@ -0,0 +1,49 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#define SC_NO_WRITE_CHECK +#include "systemc.h" + +typedef sc_bv<4> bool_vector4; +typedef sc_bv<8> bool_vector8; +typedef sc_signal<bool_vector4> signal_bool_vector4; +typedef sc_signal<bool_vector8> signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/data_gen.h b/src/systemc/tests/systemc/misc/synth/add_chain/data_gen.h new file mode 100644 index 000000000..18df486d3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/data_gen.h @@ -0,0 +1,100 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + data_gen.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "define.h" + +/******************************************************************************/ +/*************************** data_gen Function **********************/ +/******************************************************************************/ + +SC_MODULE( DATA_GEN ) +{ + SC_HAS_PROCESS( DATA_GEN ); + + sc_in_clk clk; + + /*** Input and Output Ports ***/ + const sc_signal<bool>& ready; + signal_bool_vector8& data; + sc_signal<int>& addr; + + /*** Constructor ***/ + DATA_GEN ( sc_module_name NAME, + sc_clock& TICK_N, + const sc_signal<bool>& READY, + signal_bool_vector8& DATA, + sc_signal<int>& ADDR ) + + : + ready (READY), + data (DATA), // 8 bits + addr (ADDR) + + { + clk (TICK_N); + SC_CTHREAD( entry, clk.neg() ); + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +DATA_GEN::entry() +{ + + while(true) { + +// WAIT FOR POSEDGE OF ready + + at_posedge(ready); + +// CHECK TO SEE IF THE END OF MEMORY HAS BEEN REACHED + + if(addr.read() > LIMIT) { // if(addr > LIMIT) + break; + } + +// WRITE VALUE OF MEMORY AT CURRENT ADDRESS TO data +// INCREMENT addr BY 1 + + data.write(mem[addr.read()]); // data = mem[addr] + addr.write(addr.read() + 1); // addr = addr + 1 + } + +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/define.h b/src/systemc/tests/systemc/misc/synth/add_chain/define.h new file mode 100644 index 000000000..99f950a1a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/define.h @@ -0,0 +1,44 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +#define LIMIT 257 // Last stimulus vector memory address location +#define WIDTH 8 // Width of stimulus vector +#define LATENCY 3 // Latency of sum + +extern bool_vector8 mem[]; diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/display.h b/src/systemc/tests/systemc/misc/synth/add_chain/display.h new file mode 100644 index 000000000..bef1bf3b4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/display.h @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "define.h" + + +/******************************************************************************/ +/*************************** Output Display Function **********************/ +/******************************************************************************/ + +SC_MODULE( DISPLAY ) +{ + SC_HAS_PROCESS( DISPLAY ); + + /*** Input and Output Ports ***/ + const sc_signal<bool>& ready; // Input + const signal_bool_vector8& data; // Input + const signal_bool_vector4& sum; // Input + + /*** Constructor ***/ + DISPLAY ( sc_module_name NAME, + const sc_signal<bool>& READY, + const signal_bool_vector8& DATA, + const signal_bool_vector4& SUM ) + + : ready (READY), + data (DATA), // 8 bits + sum (SUM) + + { + SC_METHOD( entry ); + sensitive << ready; + sensitive << data; + sensitive << sum; + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +DISPLAY::entry() +{ +// DISPLAY NUMBER OF 1'S IN DATA AT NEGEDGE ready + + if( ready.posedge() ) { + cout << "Sum of " + << data.read() + << " is " << sum.read().to_uint() + << endl; + } +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/golden/add_chain.log b/src/systemc/tests/systemc/misc/synth/add_chain/golden/add_chain.log new file mode 100644 index 000000000..35db754ef --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/golden/add_chain.log @@ -0,0 +1,262 @@ +SystemC Simulation +Sum of 00000000 is 0 +Sum of 11111111 is 8 +Sum of 00000000 is 0 +Sum of 00000001 is 1 +Sum of 00000010 is 1 +Sum of 00000011 is 2 +Sum of 00000100 is 1 +Sum of 00000101 is 2 +Sum of 00000110 is 2 +Sum of 00000111 is 3 +Sum of 00001000 is 1 +Sum of 00001001 is 2 +Sum of 00001010 is 2 +Sum of 00001011 is 3 +Sum of 00001100 is 2 +Sum of 00001101 is 3 +Sum of 00001110 is 3 +Sum of 00001111 is 4 +Sum of 00010000 is 1 +Sum of 00010001 is 2 +Sum of 00010010 is 2 +Sum of 00010011 is 3 +Sum of 00010100 is 2 +Sum of 00010101 is 3 +Sum of 00010110 is 3 +Sum of 00010111 is 4 +Sum of 00011000 is 2 +Sum of 00011001 is 3 +Sum of 00011010 is 3 +Sum of 00011011 is 4 +Sum of 00011100 is 3 +Sum of 00011101 is 4 +Sum of 00011110 is 4 +Sum of 00011111 is 5 +Sum of 00100000 is 1 +Sum of 00100001 is 2 +Sum of 00100010 is 2 +Sum of 00100011 is 3 +Sum of 00100100 is 2 +Sum of 00100101 is 3 +Sum of 00100110 is 3 +Sum of 00100111 is 4 +Sum of 00101000 is 2 +Sum of 00101001 is 3 +Sum of 00101010 is 3 +Sum of 00101011 is 4 +Sum of 00101100 is 3 +Sum of 00101101 is 4 +Sum of 00101110 is 4 +Sum of 00101111 is 5 +Sum of 00110000 is 2 +Sum of 00110001 is 3 +Sum of 00110010 is 3 +Sum of 00110011 is 4 +Sum of 00110100 is 3 +Sum of 00110101 is 4 +Sum of 00110110 is 4 +Sum of 00110111 is 5 +Sum of 00111000 is 3 +Sum of 00111001 is 4 +Sum of 00111010 is 4 +Sum of 00111011 is 5 +Sum of 00111100 is 4 +Sum of 00111101 is 5 +Sum of 00111110 is 5 +Sum of 00111111 is 6 +Sum of 01000000 is 1 +Sum of 01000001 is 2 +Sum of 01000010 is 2 +Sum of 01000011 is 3 +Sum of 01000100 is 2 +Sum of 01000101 is 3 +Sum of 01000110 is 3 +Sum of 01000111 is 4 +Sum of 01001000 is 2 +Sum of 01001001 is 3 +Sum of 01001010 is 3 +Sum of 01001011 is 4 +Sum of 01001100 is 3 +Sum of 01001101 is 4 +Sum of 01001110 is 4 +Sum of 01001111 is 5 +Sum of 01010000 is 2 +Sum of 01010001 is 3 +Sum of 01010010 is 3 +Sum of 01010011 is 4 +Sum of 01010100 is 3 +Sum of 01010101 is 4 +Sum of 01010110 is 4 +Sum of 01010111 is 5 +Sum of 01011000 is 3 +Sum of 01011001 is 4 +Sum of 01011010 is 4 +Sum of 01011011 is 5 +Sum of 01011100 is 4 +Sum of 01011101 is 5 +Sum of 01011110 is 5 +Sum of 01011111 is 6 +Sum of 01100000 is 2 +Sum of 01100001 is 3 +Sum of 01100010 is 3 +Sum of 01100011 is 4 +Sum of 01100100 is 3 +Sum of 01100101 is 4 +Sum of 01100110 is 4 +Sum of 01100111 is 5 +Sum of 01101000 is 3 +Sum of 01101001 is 4 +Sum of 01101010 is 4 +Sum of 01101011 is 5 +Sum of 01101100 is 4 +Sum of 01101101 is 5 +Sum of 01101110 is 5 +Sum of 01101111 is 6 +Sum of 01110000 is 3 +Sum of 01110001 is 4 +Sum of 01110010 is 4 +Sum of 01110011 is 5 +Sum of 01110100 is 4 +Sum of 01110101 is 5 +Sum of 01110110 is 5 +Sum of 01110111 is 6 +Sum of 01111000 is 4 +Sum of 01111001 is 5 +Sum of 01111010 is 5 +Sum of 01111011 is 6 +Sum of 01111100 is 5 +Sum of 01111101 is 6 +Sum of 01111110 is 6 +Sum of 01111111 is 7 +Sum of 10000000 is 1 +Sum of 10000001 is 2 +Sum of 10000010 is 2 +Sum of 10000011 is 3 +Sum of 10000100 is 2 +Sum of 10000101 is 3 +Sum of 10000110 is 3 +Sum of 10000111 is 4 +Sum of 10001000 is 2 +Sum of 10001001 is 3 +Sum of 10001010 is 3 +Sum of 10001011 is 4 +Sum of 10001100 is 3 +Sum of 10001101 is 4 +Sum of 10001110 is 4 +Sum of 10001111 is 5 +Sum of 10010000 is 2 +Sum of 10010001 is 3 +Sum of 10010010 is 3 +Sum of 10010011 is 4 +Sum of 10010100 is 3 +Sum of 10010101 is 4 +Sum of 10010110 is 4 +Sum of 10010111 is 5 +Sum of 10011000 is 3 +Sum of 10011001 is 4 +Sum of 10011010 is 4 +Sum of 10011011 is 5 +Sum of 10011100 is 4 +Sum of 10011101 is 5 +Sum of 10011110 is 5 +Sum of 10011111 is 6 +Sum of 10100000 is 2 +Sum of 10100001 is 3 +Sum of 10100010 is 3 +Sum of 10100011 is 4 +Sum of 10100100 is 3 +Sum of 10100101 is 4 +Sum of 10100110 is 4 +Sum of 10100111 is 5 +Sum of 10101000 is 3 +Sum of 10101001 is 4 +Sum of 10101010 is 4 +Sum of 10101011 is 5 +Sum of 10101100 is 4 +Sum of 10101101 is 5 +Sum of 10101110 is 5 +Sum of 10101111 is 6 +Sum of 10110000 is 3 +Sum of 10110001 is 4 +Sum of 10110010 is 4 +Sum of 10110011 is 5 +Sum of 10110100 is 4 +Sum of 10110101 is 5 +Sum of 10110110 is 5 +Sum of 10110111 is 6 +Sum of 10111000 is 4 +Sum of 10111001 is 5 +Sum of 10111010 is 5 +Sum of 10111011 is 6 +Sum of 10111100 is 5 +Sum of 10111101 is 6 +Sum of 10111110 is 6 +Sum of 10111111 is 7 +Sum of 11000000 is 2 +Sum of 11000001 is 3 +Sum of 11000010 is 3 +Sum of 11000011 is 4 +Sum of 11000100 is 3 +Sum of 11000101 is 4 +Sum of 11000110 is 4 +Sum of 11000111 is 5 +Sum of 11001000 is 3 +Sum of 11001001 is 4 +Sum of 11001010 is 4 +Sum of 11001011 is 5 +Sum of 11001100 is 4 +Sum of 11001101 is 5 +Sum of 11001110 is 5 +Sum of 11001111 is 6 +Sum of 11010000 is 3 +Sum of 11010001 is 4 +Sum of 11010010 is 4 +Sum of 11010011 is 5 +Sum of 11010100 is 4 +Sum of 11010101 is 5 +Sum of 11010110 is 5 +Sum of 11010111 is 6 +Sum of 11011000 is 4 +Sum of 11011001 is 5 +Sum of 11011010 is 5 +Sum of 11011011 is 6 +Sum of 11011100 is 5 +Sum of 11011101 is 6 +Sum of 11011110 is 6 +Sum of 11011111 is 7 +Sum of 11100000 is 3 +Sum of 11100001 is 4 +Sum of 11100010 is 4 +Sum of 11100011 is 5 +Sum of 11100100 is 4 +Sum of 11100101 is 5 +Sum of 11100110 is 5 +Sum of 11100111 is 6 +Sum of 11101000 is 4 +Sum of 11101001 is 5 +Sum of 11101010 is 5 +Sum of 11101011 is 6 +Sum of 11101100 is 5 +Sum of 11101101 is 6 +Sum of 11101110 is 6 +Sum of 11101111 is 7 +Sum of 11110000 is 4 +Sum of 11110001 is 5 +Sum of 11110010 is 5 +Sum of 11110011 is 6 +Sum of 11110100 is 5 +Sum of 11110101 is 6 +Sum of 11110110 is 6 +Sum of 11110111 is 7 +Sum of 11111000 is 5 +Sum of 11111001 is 6 +Sum of 11111010 is 6 +Sum of 11111011 is 7 +Sum of 11111100 is 6 +Sum of 11111101 is 7 +Sum of 11111110 is 7 +Sum of 11111111 is 8 +Sum of 11111111 is 8 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/reset_stim.h b/src/systemc/tests/systemc/misc/synth/add_chain/reset_stim.h new file mode 100644 index 000000000..437e52b2f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/reset_stim.h @@ -0,0 +1,111 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + reset_stim.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "define.h" + +/******************************************************************************/ +/*************************** reset_stim Function **********************/ +/******************************************************************************/ +bool_vector8 mem [LIMIT + 1]; // Stimulus input memory + +SC_MODULE( RESET_STIM ) +{ + SC_HAS_PROCESS( RESET_STIM ); + + sc_in_clk clk; + + /*** Input and Output Ports ***/ + sc_signal<bool>& ready; + sc_signal<bool>& reset; + sc_signal<int>& addr; + + /*** Constructor ***/ + RESET_STIM ( sc_module_name NAME, + sc_clock& TICK_N, + sc_signal<bool>& READY, + sc_signal<bool>& RESET, + sc_signal<int>& ADDR ) + + : + ready (READY), + reset (RESET), + addr (ADDR) + + { + clk (TICK_N); + SC_CTHREAD( entry, clk.neg() ); + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +RESET_STIM::entry() +{ + +// LOAD MEMORY WITH DATA AT TIME ZERO + + ifstream stimulus ("add_chain/add_chain.dat"); + char buffer[WIDTH+1]; + + for(int i=1; i < LIMIT+1; i++) { + stimulus >> buffer; + mem[i] = buffer; + } + + stimulus.close(); + +// INITIALIZE reset AND addr, THEN REMOVE RESET AFTER 2 CLOCK CYCLES + + reset.write(0); // reset = 0 + addr.write(1); // addr = 1 + wait(2); + + reset.write(1); // reset = 1 + wait(); + +// WAIT FOR LAST MEMORY ADDRESS, THEN 3 CLOCKS, THEN STOP SIMULATION + + // do { wait(); } while (addr == LIMIT); + do { wait(); } while (!(addr == LIMIT)); + wait(LATENCY); + do { wait(); } while (ready != 1); + sc_stop(); + halt(); +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain/tb.h b/src/systemc/tests/systemc/misc/synth/add_chain/tb.h new file mode 100644 index 000000000..bf96292dd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain/tb.h @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** Testbench Function **********************/ +/******************************************************************************/ +/* */ +/* The testbench module has the following hierarchy: */ +/* */ +/* testbench */ +/* - RESET_STIM */ +/* - DATA_GEN */ +/* */ +/******************************************************************************/ + +struct testbench : public sc_module { + sc_signal<int> addr; // Address of input memory + sc_signal<bool> reset; + sc_signal<bool> ready; + signal_bool_vector8 data; + signal_bool_vector4 sum; + RESET_STIM rd1; + DATA_GEN dg1; + ADD_CHAIN ac1; + DISPLAY d1; + + /*** Constructor ***/ + testbench ( const sc_module_name& NAME, + sc_clock& TICK ) + + : sc_module(), + rd1 ("RD1", TICK, ready, reset, addr), + dg1 ("DG1", TICK, ready, data, addr), + ac1 ("AC1", TICK, reset, data, sum, ready), + d1 ("D1", ready, data, sum) + + { + end_module(); + } +}; diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain.cpp b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain.cpp new file mode 100644 index 000000000..143d1aa67 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain.cpp @@ -0,0 +1,128 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + add_chain.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +/******************************************************************************/ +/*************************** add_chain Class Definition ********************/ +/******************************************************************************/ + +SC_MODULE( add_chain ) +{ + SC_HAS_PROCESS( add_chain ); + + sc_in_clk clk; + + const sc_signal<bool>& rst; + const signal_bool_vector8& a_in; + signal_bool_vector4& sum_out; + sc_signal<bool>& ready; + + add_chain( sc_module_name NAME, + sc_clock& TICK_P, + + const sc_signal<bool>& RST, + const signal_bool_vector8& A_IN, + signal_bool_vector4& SUM_OUT, + sc_signal<bool>& READY + ) + : + rst (RST), + a_in (A_IN), + sum_out (SUM_OUT), + ready (READY) + { + clk(TICK_P); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(rst,0); + } + void entry(); +}; + +/******************************************************************************/ +/*************************** add_chain Entry Function **********************/ +/******************************************************************************/ +/** **/ +/** This function sums the number of 1's contained in a 8-bit data stream **/ +/** **/ +/******************************************************************************/ +void +add_chain::entry() +{ + bool_vector4 sum; + bool_vector8 a; + + /***** Reset Initialization *****/ + sum_out.write(0); + ready.write(1); + wait(); + + /***** MAIN LOOP *****/ + while(true) { + a = a_in; + + /***** Handshake *****/ + ready.write(0); + wait(); + + /***** Computation *****/ + sum = 0; + + for (int i=0; i<=7; i=i+1) { + sum = sum.to_uint() + a[i].to_bool(); + } + + sum_out.write(sum); + + /***** Handshake *****/ + ready.write(1); + wait(); + } +} + +void +f_add_chain( const char* NAME, + sc_clock& TICK, + const sc_signal<bool>& RST, + const signal_bool_vector8& A_IN, + signal_bool_vector4& SUM_OUT, + sc_signal<bool>& READY ) + +{ + new add_chain(NAME, TICK, RST, A_IN, SUM_OUT, READY); +} + diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain.dat b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain.dat new file mode 100644 index 000000000..f6352869f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain.dat @@ -0,0 +1,257 @@ +11111111 +00000000 +00000001 +00000010 +00000011 +00000100 +00000101 +00000110 +00000111 +00001000 +00001001 +00001010 +00001011 +00001100 +00001101 +00001110 +00001111 +00010000 +00010001 +00010010 +00010011 +00010100 +00010101 +00010110 +00010111 +00011000 +00011001 +00011010 +00011011 +00011100 +00011101 +00011110 +00011111 +00100000 +00100001 +00100010 +00100011 +00100100 +00100101 +00100110 +00100111 +00101000 +00101001 +00101010 +00101011 +00101100 +00101101 +00101110 +00101111 +00110000 +00110001 +00110010 +00110011 +00110100 +00110101 +00110110 +00110111 +00111000 +00111001 +00111010 +00111011 +00111100 +00111101 +00111110 +00111111 +01000000 +01000001 +01000010 +01000011 +01000100 +01000101 +01000110 +01000111 +01001000 +01001001 +01001010 +01001011 +01001100 +01001101 +01001110 +01001111 +01010000 +01010001 +01010010 +01010011 +01010100 +01010101 +01010110 +01010111 +01011000 +01011001 +01011010 +01011011 +01011100 +01011101 +01011110 +01011111 +01100000 +01100001 +01100010 +01100011 +01100100 +01100101 +01100110 +01100111 +01101000 +01101001 +01101010 +01101011 +01101100 +01101101 +01101110 +01101111 +01110000 +01110001 +01110010 +01110011 +01110100 +01110101 +01110110 +01110111 +01111000 +01111001 +01111010 +01111011 +01111100 +01111101 +01111110 +01111111 +10000000 +10000001 +10000010 +10000011 +10000100 +10000101 +10000110 +10000111 +10001000 +10001001 +10001010 +10001011 +10001100 +10001101 +10001110 +10001111 +10010000 +10010001 +10010010 +10010011 +10010100 +10010101 +10010110 +10010111 +10011000 +10011001 +10011010 +10011011 +10011100 +10011101 +10011110 +10011111 +10100000 +10100001 +10100010 +10100011 +10100100 +10100101 +10100110 +10100111 +10101000 +10101001 +10101010 +10101011 +10101100 +10101101 +10101110 +10101111 +10110000 +10110001 +10110010 +10110011 +10110100 +10110101 +10110110 +10110111 +10111000 +10111001 +10111010 +10111011 +10111100 +10111101 +10111110 +10111111 +11000000 +11000001 +11000010 +11000011 +11000100 +11000101 +11000110 +11000111 +11001000 +11001001 +11001010 +11001011 +11001100 +11001101 +11001110 +11001111 +11010000 +11010001 +11010010 +11010011 +11010100 +11010101 +11010110 +11010111 +11011000 +11011001 +11011010 +11011011 +11011100 +11011101 +11011110 +11011111 +11100000 +11100001 +11100010 +11100011 +11100100 +11100101 +11100110 +11100111 +11101000 +11101001 +11101010 +11101011 +11101100 +11101101 +11101110 +11101111 +11110000 +11110001 +11110010 +11110011 +11110100 +11110101 +11110110 +11110111 +11111000 +11111001 +11111010 +11111011 +11111100 +11111101 +11111110 +11111111 diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain.h b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain.h new file mode 100644 index 000000000..61214c3bc --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain.h @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + add_chain.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define LIMIT 257 // Last stimulus vector memory address location +#define WIDTH 8 // Width of stimulus vector +#define LATENCY 3 // Latency of sum + + + +extern bool_vector8 mem[]; + +extern void f_RESET_STIM (const char*, + sc_clock&, + sc_signal<bool>&, + sc_signal<bool>&, + sc_signal<int>& ); + +extern void f_DATA_GEN (const char*, + sc_clock&, + const sc_signal<bool>&, + signal_bool_vector8&, + sc_signal<int>& ); + +extern void f_add_chain (const char*, + sc_clock&, + const sc_signal<bool>&, + const signal_bool_vector8&, + signal_bool_vector4&, + sc_signal<bool>& ); + +extern void f_DISPLAY (const char*, + const sc_signal<bool>&, + const signal_bool_vector8&, + const signal_bool_vector4&); + diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain_FUNC.f b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain_FUNC.f new file mode 100644 index 000000000..e7ac3f3b0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain_FUNC.f @@ -0,0 +1,5 @@ +add_chain_FUNC/add_chain.cpp +add_chain_FUNC/reset_stim.cpp +add_chain_FUNC/data_gen.cpp +add_chain_FUNC/display.cpp +add_chain_FUNC/add_chain_main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain_main.cpp b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain_main.cpp new file mode 100644 index 000000000..5bb91b5d9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain_main.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + add_chain_main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// $Log: add_chain_main.cpp,v $ +// Revision 1.2 2011/09/05 21:23:35 acg +// Philipp A. Hartmann: eliminate compiler warnings. +// +// Revision 1.1.1.1 2006/12/15 20:26:13 acg +// systemc_tests-2.3 +// +// Revision 1.4 2006/01/24 21:05:23 acg +// Andy Goodrich: replacement of deprecated features with their non-deprecated +// counterparts. +// +// Revision 1.3 2006/01/20 00:43:23 acg +// Andy Goodrich: Changed over to use putenv() instead of setenv() to accommodate old versions of Solaris. +// +// Revision 1.2 2006/01/19 00:47:31 acg +// Andy Goodrich: Changes for the fact signal write checking is enabled. +// + +#include "common.h" +#include "add_chain.h" +#include "add_chain_tb.h" /** Definition of testbench Structure **/ + +int +sc_main(int ac, char *av[]) +{ + sc_clock clk( "CLOCK", 20, SC_NS, 0.5, 10, SC_NS); // Clock function + testbench tb1("TB1", clk ); // Testbench Instance + sc_start(); // Simulation runs forever + // due to negative value + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain_tb.h b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain_tb.h new file mode 100644 index 000000000..6900f7fc0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/add_chain_tb.h @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + add_chain_tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** Testbench Function **********************/ +/******************************************************************************/ +/* */ +/* The testbench module has the following hierarchy: */ +/* */ +/* testbench */ +/* - RESET_STIM */ +/* - DATA_GEN */ +/* */ +/******************************************************************************/ + +#include "common.h" + +struct testbench : public sc_module { + sc_signal<int> addr; // Address of input memory + sc_signal<bool> reset; + sc_signal<bool> ready; + signal_bool_vector8 data; + signal_bool_vector4 sum; + + /*** Constructor ***/ + testbench ( const sc_module_name& NAME, + sc_clock& TICK ) + + : sc_module() + { + f_RESET_STIM ("RD1", TICK, ready, reset, addr); + f_DATA_GEN ("DG1", TICK, ready, data, addr); + f_add_chain ("AC1", TICK, reset, data, sum, ready); + f_DISPLAY ("D1", ready, data, sum); + } +}; diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/common.h b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/common.h new file mode 100644 index 000000000..850b96ab7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/common.h @@ -0,0 +1,49 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#define SC_NO_WRITE_CHECK +#include "systemc.h" + +typedef sc_bv<4> bool_vector4; +typedef sc_bv<8> bool_vector8; +typedef sc_signal<bool_vector4> signal_bool_vector4; +typedef sc_signal<bool_vector8> signal_bool_vector8; + +#endif diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/data_gen.cpp b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/data_gen.cpp new file mode 100644 index 000000000..6b0ea3306 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/data_gen.cpp @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + data_gen.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" +#include "add_chain.h" + +/******************************************************************************/ +/*************************** data_gen Function **********************/ +/******************************************************************************/ + +SC_MODULE( DATA_GEN ) +{ + SC_HAS_PROCESS( DATA_GEN ); + + sc_in_clk clk; + + /*** Input and Output Ports ***/ + const sc_signal<bool>& ready; + signal_bool_vector8& data; + sc_signal<int>& addr; + + /*** Constructor ***/ + DATA_GEN ( sc_module_name NAME, + sc_clock& TICK_N, + const sc_signal<bool>& READY, + signal_bool_vector8& DATA, + sc_signal<int>& ADDR ) + + : + ready (READY), + data (DATA), // 8 bits + addr (ADDR) + + { + clk (TICK_N); + SC_CTHREAD( entry, clk.neg() ); + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +DATA_GEN::entry() +{ + while(true) { + +/** WAIT FOR POSEDGE OF ready **/ + + do { wait(); } while (ready == 1); // Posedge ready + do { wait(); } while (ready == 0); + +/** CHECK TO SEE IF THE END OF MEMORY HAS BEEN REACHED **/ + + if(addr.read() > LIMIT) { // if(addr > LIMIT) + break; + } + +/** WRITE VALUE OF MEMORY AT CURRENT ADDRESS TO data **/ + + data.write(mem[addr.read()]); // data = mem[addr] + +/** INCREMENT addr BY 1 **/ + + addr.write(addr.read() + 1); // addr = addr + 1 + } + +} + +void +f_DATA_GEN ( const char* NAME, + sc_clock& TICK, + const sc_signal<bool>& READY, + signal_bool_vector8& DATA, + sc_signal<int>& ADDR ) + +{ + new DATA_GEN(NAME, TICK, READY, DATA, ADDR); +} + diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/display.cpp b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/display.cpp new file mode 100644 index 000000000..ebda9e56e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/display.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" +#include "add_chain.h" + +/******************************************************************************/ +/*************************** Output Display Function **********************/ +/******************************************************************************/ + +SC_MODULE( DISPLAY ) +{ + SC_HAS_PROCESS( DISPLAY ); + + /*** Input and Output Ports ***/ + const sc_signal<bool>& ready; // Input + const signal_bool_vector8& data; // Input + const signal_bool_vector4& sum; // Input + + /*** Constructor ***/ + DISPLAY ( sc_module_name NAME, + const sc_signal<bool>& READY, + const signal_bool_vector8& DATA, + const signal_bool_vector4& SUM ) + + : ready (READY), + data (DATA), // 8 bits + sum (SUM) + + { + SC_METHOD( entry ); + sensitive << ready; + sensitive << data; + sensitive << sum; + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +DISPLAY::entry() +{ +// DISPLAY NUMBER OF 1'S IN DATA AT NEGEDGE ready + + if( ready.posedge() ) { + cout << "Sum of " + << data.read() + << " is " << sum.read().to_uint() + << endl; + } +} + +void +f_DISPLAY ( const char* NAME, + const sc_signal<bool>& READY, + const signal_bool_vector8& DATA, + const signal_bool_vector4& SUM ) + +{ + new DISPLAY(NAME, READY, DATA, SUM); +} + diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/golden/add_chain_FUNC.log b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/golden/add_chain_FUNC.log new file mode 100644 index 000000000..0b991ff63 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/golden/add_chain_FUNC.log @@ -0,0 +1,263 @@ +SystemC Simulation +Sum of 00000000 is 0 +Sum of 00000000 is 0 +Sum of 11111111 is 8 +Sum of 00000000 is 0 +Sum of 00000001 is 1 +Sum of 00000010 is 1 +Sum of 00000011 is 2 +Sum of 00000100 is 1 +Sum of 00000101 is 2 +Sum of 00000110 is 2 +Sum of 00000111 is 3 +Sum of 00001000 is 1 +Sum of 00001001 is 2 +Sum of 00001010 is 2 +Sum of 00001011 is 3 +Sum of 00001100 is 2 +Sum of 00001101 is 3 +Sum of 00001110 is 3 +Sum of 00001111 is 4 +Sum of 00010000 is 1 +Sum of 00010001 is 2 +Sum of 00010010 is 2 +Sum of 00010011 is 3 +Sum of 00010100 is 2 +Sum of 00010101 is 3 +Sum of 00010110 is 3 +Sum of 00010111 is 4 +Sum of 00011000 is 2 +Sum of 00011001 is 3 +Sum of 00011010 is 3 +Sum of 00011011 is 4 +Sum of 00011100 is 3 +Sum of 00011101 is 4 +Sum of 00011110 is 4 +Sum of 00011111 is 5 +Sum of 00100000 is 1 +Sum of 00100001 is 2 +Sum of 00100010 is 2 +Sum of 00100011 is 3 +Sum of 00100100 is 2 +Sum of 00100101 is 3 +Sum of 00100110 is 3 +Sum of 00100111 is 4 +Sum of 00101000 is 2 +Sum of 00101001 is 3 +Sum of 00101010 is 3 +Sum of 00101011 is 4 +Sum of 00101100 is 3 +Sum of 00101101 is 4 +Sum of 00101110 is 4 +Sum of 00101111 is 5 +Sum of 00110000 is 2 +Sum of 00110001 is 3 +Sum of 00110010 is 3 +Sum of 00110011 is 4 +Sum of 00110100 is 3 +Sum of 00110101 is 4 +Sum of 00110110 is 4 +Sum of 00110111 is 5 +Sum of 00111000 is 3 +Sum of 00111001 is 4 +Sum of 00111010 is 4 +Sum of 00111011 is 5 +Sum of 00111100 is 4 +Sum of 00111101 is 5 +Sum of 00111110 is 5 +Sum of 00111111 is 6 +Sum of 01000000 is 1 +Sum of 01000001 is 2 +Sum of 01000010 is 2 +Sum of 01000011 is 3 +Sum of 01000100 is 2 +Sum of 01000101 is 3 +Sum of 01000110 is 3 +Sum of 01000111 is 4 +Sum of 01001000 is 2 +Sum of 01001001 is 3 +Sum of 01001010 is 3 +Sum of 01001011 is 4 +Sum of 01001100 is 3 +Sum of 01001101 is 4 +Sum of 01001110 is 4 +Sum of 01001111 is 5 +Sum of 01010000 is 2 +Sum of 01010001 is 3 +Sum of 01010010 is 3 +Sum of 01010011 is 4 +Sum of 01010100 is 3 +Sum of 01010101 is 4 +Sum of 01010110 is 4 +Sum of 01010111 is 5 +Sum of 01011000 is 3 +Sum of 01011001 is 4 +Sum of 01011010 is 4 +Sum of 01011011 is 5 +Sum of 01011100 is 4 +Sum of 01011101 is 5 +Sum of 01011110 is 5 +Sum of 01011111 is 6 +Sum of 01100000 is 2 +Sum of 01100001 is 3 +Sum of 01100010 is 3 +Sum of 01100011 is 4 +Sum of 01100100 is 3 +Sum of 01100101 is 4 +Sum of 01100110 is 4 +Sum of 01100111 is 5 +Sum of 01101000 is 3 +Sum of 01101001 is 4 +Sum of 01101010 is 4 +Sum of 01101011 is 5 +Sum of 01101100 is 4 +Sum of 01101101 is 5 +Sum of 01101110 is 5 +Sum of 01101111 is 6 +Sum of 01110000 is 3 +Sum of 01110001 is 4 +Sum of 01110010 is 4 +Sum of 01110011 is 5 +Sum of 01110100 is 4 +Sum of 01110101 is 5 +Sum of 01110110 is 5 +Sum of 01110111 is 6 +Sum of 01111000 is 4 +Sum of 01111001 is 5 +Sum of 01111010 is 5 +Sum of 01111011 is 6 +Sum of 01111100 is 5 +Sum of 01111101 is 6 +Sum of 01111110 is 6 +Sum of 01111111 is 7 +Sum of 10000000 is 1 +Sum of 10000001 is 2 +Sum of 10000010 is 2 +Sum of 10000011 is 3 +Sum of 10000100 is 2 +Sum of 10000101 is 3 +Sum of 10000110 is 3 +Sum of 10000111 is 4 +Sum of 10001000 is 2 +Sum of 10001001 is 3 +Sum of 10001010 is 3 +Sum of 10001011 is 4 +Sum of 10001100 is 3 +Sum of 10001101 is 4 +Sum of 10001110 is 4 +Sum of 10001111 is 5 +Sum of 10010000 is 2 +Sum of 10010001 is 3 +Sum of 10010010 is 3 +Sum of 10010011 is 4 +Sum of 10010100 is 3 +Sum of 10010101 is 4 +Sum of 10010110 is 4 +Sum of 10010111 is 5 +Sum of 10011000 is 3 +Sum of 10011001 is 4 +Sum of 10011010 is 4 +Sum of 10011011 is 5 +Sum of 10011100 is 4 +Sum of 10011101 is 5 +Sum of 10011110 is 5 +Sum of 10011111 is 6 +Sum of 10100000 is 2 +Sum of 10100001 is 3 +Sum of 10100010 is 3 +Sum of 10100011 is 4 +Sum of 10100100 is 3 +Sum of 10100101 is 4 +Sum of 10100110 is 4 +Sum of 10100111 is 5 +Sum of 10101000 is 3 +Sum of 10101001 is 4 +Sum of 10101010 is 4 +Sum of 10101011 is 5 +Sum of 10101100 is 4 +Sum of 10101101 is 5 +Sum of 10101110 is 5 +Sum of 10101111 is 6 +Sum of 10110000 is 3 +Sum of 10110001 is 4 +Sum of 10110010 is 4 +Sum of 10110011 is 5 +Sum of 10110100 is 4 +Sum of 10110101 is 5 +Sum of 10110110 is 5 +Sum of 10110111 is 6 +Sum of 10111000 is 4 +Sum of 10111001 is 5 +Sum of 10111010 is 5 +Sum of 10111011 is 6 +Sum of 10111100 is 5 +Sum of 10111101 is 6 +Sum of 10111110 is 6 +Sum of 10111111 is 7 +Sum of 11000000 is 2 +Sum of 11000001 is 3 +Sum of 11000010 is 3 +Sum of 11000011 is 4 +Sum of 11000100 is 3 +Sum of 11000101 is 4 +Sum of 11000110 is 4 +Sum of 11000111 is 5 +Sum of 11001000 is 3 +Sum of 11001001 is 4 +Sum of 11001010 is 4 +Sum of 11001011 is 5 +Sum of 11001100 is 4 +Sum of 11001101 is 5 +Sum of 11001110 is 5 +Sum of 11001111 is 6 +Sum of 11010000 is 3 +Sum of 11010001 is 4 +Sum of 11010010 is 4 +Sum of 11010011 is 5 +Sum of 11010100 is 4 +Sum of 11010101 is 5 +Sum of 11010110 is 5 +Sum of 11010111 is 6 +Sum of 11011000 is 4 +Sum of 11011001 is 5 +Sum of 11011010 is 5 +Sum of 11011011 is 6 +Sum of 11011100 is 5 +Sum of 11011101 is 6 +Sum of 11011110 is 6 +Sum of 11011111 is 7 +Sum of 11100000 is 3 +Sum of 11100001 is 4 +Sum of 11100010 is 4 +Sum of 11100011 is 5 +Sum of 11100100 is 4 +Sum of 11100101 is 5 +Sum of 11100110 is 5 +Sum of 11100111 is 6 +Sum of 11101000 is 4 +Sum of 11101001 is 5 +Sum of 11101010 is 5 +Sum of 11101011 is 6 +Sum of 11101100 is 5 +Sum of 11101101 is 6 +Sum of 11101110 is 6 +Sum of 11101111 is 7 +Sum of 11110000 is 4 +Sum of 11110001 is 5 +Sum of 11110010 is 5 +Sum of 11110011 is 6 +Sum of 11110100 is 5 +Sum of 11110101 is 6 +Sum of 11110110 is 6 +Sum of 11110111 is 7 +Sum of 11111000 is 5 +Sum of 11111001 is 6 +Sum of 11111010 is 6 +Sum of 11111011 is 7 +Sum of 11111100 is 6 +Sum of 11111101 is 7 +Sum of 11111110 is 7 +Sum of 11111111 is 8 +Sum of 11111111 is 8 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/reset_stim.cpp b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/reset_stim.cpp new file mode 100644 index 000000000..7ce054971 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/add_chain_FUNC/reset_stim.cpp @@ -0,0 +1,122 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + reset_stim.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" +#include "add_chain.h" + +/******************************************************************************/ +/*************************** reset_stim Function **********************/ +/******************************************************************************/ +bool_vector8 mem[LIMIT + 1]; // Stimulus input memory + +SC_MODULE( RESET_STIM ) +{ + SC_HAS_PROCESS( RESET_STIM ); + + sc_in_clk clk; + + /*** Input and Output Ports ***/ + sc_signal<bool>& ready; + sc_signal<bool>& reset; + sc_signal<int>& addr; + + /*** Constructor ***/ + RESET_STIM ( sc_module_name NAME, + sc_clock& TICK_N, + sc_signal<bool>& READY, + sc_signal<bool>& RESET, + sc_signal<int>& ADDR ) + + : + ready (READY), + reset (RESET), + addr (ADDR) + + { + clk (TICK_N); + SC_CTHREAD( entry, clk.neg() ); + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +RESET_STIM::entry() +{ + +/** LOAD MEMORY WITH DATA AT TIME ZERO **/ + + ifstream stimulus ("add_chain_FUNC/add_chain.dat"); + char buffer[WIDTH+1]; + + for(int i=1; i < LIMIT+1; i++) { + stimulus >> buffer; + mem[i] = buffer; + } + + stimulus.close(); + +/** INITIALIZE reset AND addr, THEN REMOVE RESET AFTER 2 CLOCK CYCLES **/ + + reset.write(0); // reset = 0 + addr.write(1); // addr = 1 + wait(2); + + reset.write(1); // reset = 1 + +/** WAIT FOR LAST MEMORY ADDRESS, THEN 3 CLOCKS, THEN STOP SIMULATION **/ + +// do { wait(); } while (addr == LIMIT); + do { wait(); } while (!(addr == LIMIT)); + wait(LATENCY); + do { wait(); } while (ready != 1); + sc_stop(); + halt(); +} + +void +f_RESET_STIM ( const char* NAME, + sc_clock& TICK, + sc_signal<bool>& READY, + sc_signal<bool>& RESET, + sc_signal<int>& ADDR ) + +{ + new RESET_STIM(NAME, TICK, READY,RESET, ADDR); +} diff --git a/src/systemc/tests/systemc/misc/synth/blast/blast1/blast1.cpp b/src/systemc/tests/systemc/misc/synth/blast/blast1/blast1.cpp new file mode 100644 index 000000000..7e422a0ad --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/blast/blast1/blast1.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + blast1.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( array ) +{ + SC_HAS_PROCESS( array ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<char>& a; + const sc_signal<char>& b; + sc_signal<short>& c; + + char mem[4]; + sc_unsigned i, j; + + array( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<bool>& RESET, + const sc_signal<char>& A, + const sc_signal<char>& B, + sc_signal<short>& C ) + : + reset(RESET), a(A), b(B), c(C), + i(2), j(2) + { + clk(CLK); + SC_CTHREAD( entry, clk ); + reset_signal_is(reset,true); + } + void entry(); +}; + +void +array::entry() +{ + i = 1; + j = 2; + mem[i.to_uint()] = a.read(); + mem[j.to_uint()] = b.read(); + c = mem[i.to_uint()] * mem[j.to_uint()]; + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/blast/blast1/golden/blast1.log b/src/systemc/tests/systemc/misc/synth/blast/blast1/golden/blast1.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/blast/blast1/golden/blast1.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/blast/blast2/blast2.cpp b/src/systemc/tests/systemc/misc/synth/blast/blast2/blast2.cpp new file mode 100644 index 000000000..51035fea1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/blast/blast2/blast2.cpp @@ -0,0 +1,89 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + blast2.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( array ) +{ + SC_HAS_PROCESS( array ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<char>& a; + const sc_signal<char>& b; + sc_signal<short>& c; + + char mem[9]; + sc_unsigned i, j; + + array( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<bool>& RESET, + const sc_signal<char>& A, + const sc_signal<char>& B, + sc_signal<short>& C ) + : + reset(RESET), a(A), b(B), c(C), + i(2), j(2) + { + clk(CLK); + SC_CTHREAD( entry, clk ); + reset_signal_is(reset,true); + } + void entry(); +}; + +void +array::entry() +{ + i = 2; + j = 1; + mem[i.to_uint()] = a.read(); + mem[j.to_uint()] = b.read(); + mem[7] = i.to_uint(); + mem[8] = j.to_uint(); + mem[mem[7]] = a + 1; + mem[mem[8]] = b - 2; + c = mem[i.to_uint()] * mem[j.to_uint()]; + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/blast/blast2/golden/blast2.log b/src/systemc/tests/systemc/misc/synth/blast/blast2/golden/blast2.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/blast/blast2/golden/blast2.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/blast/blast3/blast3.cpp b/src/systemc/tests/systemc/misc/synth/blast/blast3/blast3.cpp new file mode 100644 index 000000000..73d831d56 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/blast/blast3/blast3.cpp @@ -0,0 +1,96 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + blast3.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( array ) +{ + SC_HAS_PROCESS( array ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + sc_signal<bool>& ready; + const sc_signal<char>& a; + const sc_signal<char>& b; + sc_signal<short>& c; + + char mem[17]; + sc_unsigned i, j; + + array( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<bool>& RESET, + sc_signal<bool>& READY, + const sc_signal<char>& A, + const sc_signal<char>& B, + sc_signal<short>& C ) + : + reset(RESET), ready(READY), + a(A), b(B), c(C), + i(2), j(2) + { + clk(CLK); + SC_CTHREAD( entry, clk ); + reset_signal_is(reset,true); + } + void entry(); +}; + +void +array::entry() +{ + i = 2; + j = 1; + ready = 0; + mem[i.to_uint()] = a.read(); + mem[j.to_uint()] = b.read(); + mem[14] = i.to_uint(); + mem[12] = j.to_uint(); + wait(); + mem[mem[14]] = a + 1; + mem[mem[12]] = b - 2; + c = mem[i.to_uint()] * mem[j.to_uint()]; + ready = 1; + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} + diff --git a/src/systemc/tests/systemc/misc/synth/blast/blast3/golden/blast3.log b/src/systemc/tests/systemc/misc/synth/blast/blast3/golden/blast3.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/blast/blast3/golden/blast3.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/bubble/bubble.cpp b/src/systemc/tests/systemc/misc/synth/bubble/bubble.cpp new file mode 100644 index 000000000..5c4e0bc58 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/bubble/bubble.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bubble.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "display.h" +#include "stim.h" +#include "bubble.h" +#include "tb.h" + +int +sc_main(int ac, char *av[]) +{ + sc_clock clk( "clk", 20, SC_NS, 0.5, 0, SC_NS, false); // Clock function + + TESTBENCH tb("TB", clk ); + + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/bubble/bubble.h b/src/systemc/tests/systemc/misc/synth/bubble/bubble.h new file mode 100644 index 000000000..0ac59374c --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/bubble/bubble.h @@ -0,0 +1,216 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + bubble.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** bubble Class Definition ********************/ +/******************************************************************************/ + +#include "common.h" + +SC_MODULE( BUBBLE ) +{ + SC_HAS_PROCESS( BUBBLE ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<bool>& in_ok; + const sc_signal<bool>& out_ok; + sc_signal<bool>& instrb; + sc_signal<bool>& outstrb; + const signal_bool_vector &a1,&a2,&a3,&a4,&a5,&a6,&a7,&a8;// -128 to 127 + signal_bool_vector &d1,&d2,&d3,&d4,&d5,&d6,&d7,&d8;// -128 to 127 + + BUBBLE( sc_module_name NAME, + sc_clock& TICK_P, + const sc_signal<bool>& RESET, + const sc_signal<bool>& IN_OK, + const sc_signal<bool>& OUT_OK, + sc_signal<bool>& INSTRB, + sc_signal<bool>& OUTSTRB, + const signal_bool_vector& A1, + const signal_bool_vector& A2, + const signal_bool_vector& A3, + const signal_bool_vector& A4, + const signal_bool_vector& A5, + const signal_bool_vector& A6, + const signal_bool_vector& A7, + const signal_bool_vector& A8, + signal_bool_vector& D1, + signal_bool_vector& D2, + signal_bool_vector& D3, + signal_bool_vector& D4, + signal_bool_vector& D5, + signal_bool_vector& D6, + signal_bool_vector& D7, + signal_bool_vector& D8 + ) + : + reset (RESET), + in_ok (IN_OK), + out_ok (OUT_OK), + instrb (INSTRB), + outstrb (OUTSTRB), + a1 (A1), a2(A2), a3(A3), a4(A4), + a5 (A5), a6(A6), a7(A7), a8(A8), + d1 (D1), d2(D2), d3(D3), d4(D4), + d5 (D5), d6(D6), d7(D7), d8(D8) + { + clk(TICK_P); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + } + void entry(); +}; + +/******************************************************************************/ +/*************************** bubble Entry Function **********************/ +/******************************************************************************/ +/** **/ +/** This function is most likely a bubble sort algorithm ??? **/ +/** **/ +/******************************************************************************/ +void +BUBBLE::entry() +{ + bool_vector B[9]; + bool_vector C[9]; + int minel; + int x; + int i; + int j; + +// RESET INITIALIZATION + + while(true) { + + instrb.write(false); + outstrb.write(false); + minel = -500; + x = 0; + d1.write(0); + d2.write(0); + d3.write(0); + d4.write(0); + d5.write(0); + d6.write(0); + d7.write(0); + d8.write(0); + for (i = 1; i <= 8; i++) { + B[i] = 0; + } + for (i = 1; i <= 8; i++) { + C[i] = 0; + } + wait(); + +// READY SIGNAL FOR INPUT DATA + + wait(); + instrb.write(true); + wait(); + +// INPUT HANDSHAKE & INPUT READ + + do { wait(); } while (!in_ok); + + instrb.write(false); + wait(); + + B[1] = a1.read(); B[2] = a2.read(); B[3] = a3.read(); B[4] = a4.read(); + B[5] = a5.read(); B[6] = a6.read(); B[7] = a7.read(); B[8] = a8.read(); + wait(); + +lout << "STARTING BUBBLE SORT" << endl; +// BUBBLE SORT ALGORITHM + + // EVERY ELEMENT + for (i = 1; i <= 7; i++) { + + if (B[i].to_int() > B[i+1].to_int()) { // if #1 + for (j = 1; j <= 8; j++) { + C[j] = B[j]; // COPY + } + + B[i] = B[i+1]; + B[i+1] = C[i]; + minel = C[i].to_int(); // MOVE + + for (j = 1; j <= 8; j++) { + C[j] = B[j]; // COPY + } + + if (i >= 2) { // if #2 + x = i; + while (x > 1) { + if (B[x].to_int() > B[x-1].to_int()) { + break; + } + else { + for (j = 1; j <= 8; j++) { + C[j] = B[j]; + } + + B[x] = B[x-1]; + B[x-1] = C[x]; // MOVE + + for (j = 1; j <= 8; j++) { + C[j] = B[j]; // COPY + } + } // end else + x = x-1; + } // end WHL Loop + } // end if #2 + } // end if #1; + } // end FL3 Loop + wait(); + +// WRITE OUTPUT & OUTPUT HANDSHAKE + + d1.write(C[1]); d2.write(C[2]); d3.write(C[3]); d4.write(C[4]); + d5.write(C[5]); d6.write(C[6]); d7.write(C[7]); d8.write(C[8]); + outstrb.write(true); // Ready to give output data + wait(); + + do { wait(); } while (!out_ok); + + outstrb.write(false); + wait(); + + } // end Reset Loop + +} diff --git a/src/systemc/tests/systemc/misc/synth/bubble/common.h b/src/systemc/tests/systemc/misc/synth/bubble/common.h new file mode 100644 index 000000000..3ea41ad75 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/bubble/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_bv<8> bool_vector; +typedef sc_signal<bool_vector> signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/synth/bubble/display.h b/src/systemc/tests/systemc/misc/synth/bubble/display.h new file mode 100644 index 000000000..b66c02626 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/bubble/display.h @@ -0,0 +1,163 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +/****************************************************************/ +/** Display to standard out and to logfile "systemc.log" **/ +/****************************************************************/ + +ofstream lout ("systemc.log"); // Output log file + +/******************************************************************************/ +/*************************** Output Display Function **********************/ +/******************************************************************************/ + +SC_MODULE( DISPLAY ) +{ + SC_HAS_PROCESS( DISPLAY ); + +// INPUTS & OUTPUTS TO DISPLAY + + const sc_signal<bool>& reset; + const sc_signal<bool>& in_ok; + const sc_signal<bool>& out_ok; + const sc_signal<bool>& instrb; + const sc_signal<bool>& outstrb; + const signal_bool_vector &a1,&a2,&a3,&a4,&a5,&a6,&a7,&a8; + const signal_bool_vector &d1,&d2,&d3,&d4,&d5,&d6,&d7,&d8; + +// CONSTRUCTOR DEFINITION + + DISPLAY( sc_module_name NAME, + const sc_signal<bool>& RESET, + const sc_signal<bool>& IN_OK, + const sc_signal<bool>& OUT_OK, + const sc_signal<bool>& INSTRB, + const sc_signal<bool>& OUTSTRB, + const signal_bool_vector& A1, + const signal_bool_vector& A2, + const signal_bool_vector& A3, + const signal_bool_vector& A4, + const signal_bool_vector& A5, + const signal_bool_vector& A6, + const signal_bool_vector& A7, + const signal_bool_vector& A8, + const signal_bool_vector& D1, + const signal_bool_vector& D2, + const signal_bool_vector& D3, + const signal_bool_vector& D4, + const signal_bool_vector& D5, + const signal_bool_vector& D6, + const signal_bool_vector& D7, + const signal_bool_vector& D8 + ) + + : + reset (RESET), + in_ok (IN_OK), + out_ok (OUT_OK), + instrb (INSTRB), + outstrb (OUTSTRB), + a1 (A1), a2(A2), a3(A3), a4(A4), + a5 (A5), a6(A6), a7(A7), a8(A8), + d1 (D1), d2(D2), d3(D3), d4(D4), + d5 (D5), d6(D6), d7(D7), d8(D8) + + { + SC_METHOD( entry ); + sensitive << reset; + sensitive << in_ok; + sensitive << out_ok; + sensitive << instrb; + sensitive << outstrb; + sensitive << a1; + sensitive << a2; + sensitive << a3; + sensitive << a4; + sensitive << a5; + sensitive << a6; + sensitive << a7; + sensitive << a8; + sensitive << d1; + sensitive << d2; + sensitive << d3; + sensitive << d4; + sensitive << d5; + sensitive << d6; + sensitive << d7; + sensitive << d8; + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +DISPLAY::entry() +{ +// DISPLAYS ALL SIGNALS USED TO DEBUG DESIGN + + lout << " reset = " << reset + << " in_ok = " << in_ok + << " out_ok = " << out_ok + << " instrb = " << instrb + << " outstrb = " << outstrb + << "\n" + << " a1 = " << a1 + << " a2 = " << a2 + << " a3 = " << a3 + << " a4 = " << a4 + << "\n" + << " a5 = " << a5 + << " a6 = " << a6 + << " a7 = " << a7 + << " a8 = " << a8 + << "\n" + << " d1 = " << d1 + << " d2 = " << d2 + << " d3 = " << d3 + << " d4 = " << d4 + << "\n" + << " d5 = " << d5 + << " d6 = " << d6 + << " d7 = " << d7 + << " d8 = " << d8 + << endl; + +} diff --git a/src/systemc/tests/systemc/misc/synth/bubble/golden/bubble.log b/src/systemc/tests/systemc/misc/synth/bubble/golden/bubble.log new file mode 100644 index 000000000..4c745ae88 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/bubble/golden/bubble.log @@ -0,0 +1,16 @@ +SystemC Simulation + + + INPUT DATA SORTED DATA + -76 -76 + 1 -2 + 12 1 + 85 3 + 15 12 + 103 15 + -2 85 + 3 103 + + + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/bubble/stim.h b/src/systemc/tests/systemc/misc/synth/bubble/stim.h new file mode 100644 index 000000000..50a02a06d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/bubble/stim.h @@ -0,0 +1,178 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stim.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** stimulus Class Definition ********************/ +/******************************************************************************/ + +#include "common.h" + +SC_MODULE( STIM ) +{ + SC_HAS_PROCESS( STIM ); + + sc_in_clk clk; + + sc_signal<bool>& reset; + sc_signal<bool>& in_ok; + sc_signal<bool>& out_ok; + const sc_signal<bool>& instrb; + const sc_signal<bool>& outstrb; + signal_bool_vector &a1,&a2,&a3,&a4,&a5,&a6,&a7,&a8;// -128 to 127 + const signal_bool_vector &d1,&d2,&d3,&d4,&d5,&d6,&d7,&d8; + + + STIM( sc_module_name NAME, + sc_clock& TICK_P, + sc_signal<bool>& RESET, + sc_signal<bool>& IN_OK, + sc_signal<bool>& OUT_OK, + const sc_signal<bool>& INSTRB, + const sc_signal<bool>& OUTSTRB, + signal_bool_vector& A1, + signal_bool_vector& A2, + signal_bool_vector& A3, + signal_bool_vector& A4, + signal_bool_vector& A5, + signal_bool_vector& A6, + signal_bool_vector& A7, + signal_bool_vector& A8, + signal_bool_vector& D1, + signal_bool_vector& D2, + signal_bool_vector& D3, + signal_bool_vector& D4, + signal_bool_vector& D5, + signal_bool_vector& D6, + signal_bool_vector& D7, + signal_bool_vector& D8 + ) + : + reset (RESET), + in_ok (IN_OK), + out_ok (OUT_OK), + instrb (INSTRB), + outstrb (OUTSTRB), + a1 (A1), a2(A2), a3(A3), a4(A4), + a5 (A5), a6(A6), a7(A7), a8(A8), + d1 (D1), d2(D2), d3(D3), d4(D4), + d5 (D5), d6(D6), d7(D7), d8(D8) + { + clk(TICK_P); + SC_CTHREAD( entry, clk.neg() ); + } + void entry(); +}; + +/******************************************************************************/ +/*************************** testbench Entry Function **********************/ +/******************************************************************************/ +void +STIM::entry() +{ + +// INITIAL INPUT VALUES + + a1.write(0); // Are quotes necessary ??? + a2.write(0); + a3.write(0); + a4.write(0); + a5.write(0); + a6.write(0); + a7.write(0); + a8.write(0); + in_ok.write(0); + out_ok.write(0); + reset.write(1); + wait(2); + +// REMOVE RESET + + reset.write(0); + wait(); + +// WAIT FOR REQUEST FOR INPUT + + do { wait(); } while (instrb == 0); + +// SEND INPUT DATA TO BE SORTED + a1.write(-76); + a2.write( 1); + a3.write( 12); + a4.write( 85); + a5.write( 15); + a6.write(103); + a7.write( -2); + a8.write( 3); + in_ok.write(1); + wait(); + +// WAIT FOR OUTPUT READY + + do { wait(); } while (outstrb == 0); + +// READ OUTPUT & DISPLAY RESULTS + + cout << "\n" << endl; + cout << "\t\t INPUT DATA \t\t SORTED DATA" << endl; + cout << "\t\t " << a1.read().to_int() << " \t\t " + << d1.read().to_int() << endl; + cout << "\t\t " << a2.read().to_int() << " \t\t " + << d2.read().to_int() << endl; + cout << "\t\t " << a3.read().to_int() << " \t\t " + << d3.read().to_int() << endl; + cout << "\t\t " << a4.read().to_int() << " \t\t " + << d4.read().to_int() << endl; + cout << "\t\t " << a5.read().to_int() << " \t\t " + << d5.read().to_int() << endl; + cout << "\t\t " << a6.read().to_int() << " \t\t " + << d6.read().to_int() << endl; + cout << "\t\t " << a7.read().to_int() << " \t\t " + << d7.read().to_int() << endl; + cout << "\t\t " << a8.read().to_int() << " \t\t " + << d8.read().to_int() << endl; + cout << "\n" << endl; + +// SEND FINISHED READING OUTPUT FLAG + + in_ok.write(0); + out_ok.write(1); + wait(); + +// STOP SIMULATION + + sc_stop(); +} diff --git a/src/systemc/tests/systemc/misc/synth/bubble/tb.h b/src/systemc/tests/systemc/misc/synth/bubble/tb.h new file mode 100644 index 000000000..136accc25 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/bubble/tb.h @@ -0,0 +1,72 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** testbench Class Definition ********************/ +/******************************************************************************/ + +#include "common.h" + +SC_MODULE( TESTBENCH ) +{ + sc_signal<bool> reset; + sc_signal<bool> in_ok; + sc_signal<bool> out_ok; + sc_signal<bool> instrb; + sc_signal<bool> outstrb; + signal_bool_vector a1,a2,a3,a4,a5,a6,a7,a8; // -128 to 127 + signal_bool_vector d1,d2,d3,d4,d5,d6,d7,d8; // -128 to 127 + STIM st1; + BUBBLE bubble; + DISPLAY disp1; + + TESTBENCH( sc_module_name NAME, + sc_clock& TICK ) + + : st1 ("ST1", TICK, reset, in_ok, out_ok, instrb, outstrb, + a1, a2, a3, a4, a5, a6, a7, a8, + d1, d2, d3, d4, d5, d6, d7, d8) , + + bubble ("B1", TICK, reset, in_ok, out_ok, instrb, outstrb, + a1, a2, a3, a4, a5, a6, a7, a8, + d1, d2, d3, d4, d5, d6, d7, d8) , + + disp1 ("D1", reset, in_ok, out_ok, instrb, outstrb, + a1, a2, a3, a4, a5, a6, a7, a8, + d1, d2, d3, d4, d5, d6, d7, d8) + {} +}; diff --git a/src/systemc/tests/systemc/misc/synth/circle/circ48.cpp b/src/systemc/tests/systemc/misc/synth/circle/circ48.cpp new file mode 100644 index 000000000..918fc5418 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/circ48.cpp @@ -0,0 +1,63 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + circ48.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "circ48.h" + +int +sc_main( int, char *[] ) +{ + sc_clock clk( "clk", 20, SC_NS, 0.5, 10, SC_NS ); + + sc_signal<bool> I_reset; + sc_signal<bool> I_x_ok; + sc_signal<bool> I_y_ok; + sc_signal<bool> O_out_wr; + sc_signal<bool> O_out_sel; + signal_bool_vector O_out_xy; + signal_bool_vector O_diffs; + + testbench tb( "TB", clk, I_reset, I_x_ok, I_y_ok, + O_out_wr, O_out_sel, O_out_xy ); + + circ48 c1( "C1", clk, I_reset, I_x_ok, I_y_ok, + O_out_wr, O_out_sel, O_out_xy, O_diffs ); + + sc_start(); + + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/circle/circ48.h b/src/systemc/tests/systemc/misc/synth/circle/circ48.h new file mode 100644 index 000000000..e26234a2e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/circ48.h @@ -0,0 +1,197 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + circ48.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( circ48 ) +{ + SC_HAS_PROCESS( circ48 ); + + sc_in_clk clk; + + sc_in<bool> reset; + sc_in<bool> x_ok; + sc_in<bool> y_ok; + sc_out<bool> out_wr; + sc_out<bool> out_sel; + sc_out<bool_vector> out_xy; + sc_out<bool_vector> diffs; + + void entry(); + + circ48( sc_module_name name_, + const sc_clock& clk_, + const sc_signal<bool>& reset_, + const sc_signal<bool>& x_ok_, + const sc_signal<bool>& y_ok_, + sc_signal<bool>& out_wr_, + sc_signal<bool>& out_sel_, + signal_bool_vector& out_xy_, + signal_bool_vector& diffs_ ) + : sc_module( name_ ) + { + clk( clk_ ); + reset( reset_ ); + x_ok( x_ok_ ); + y_ok( y_ok_ ); + out_wr( out_wr_ ); + out_sel( out_sel_ ); + out_xy( out_xy_ ); + diffs( diffs_ ); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + } +}; + + +/*****************************************************************************/ +/** **/ +/** This function is the "clean" behavior (i.e. not written with synthesis **/ +/** or implementation in mind. This is a circle generator, that uses an **/ +/** algorithmic, interpolating technique. Origin of circle is fixed to **/ +/** point (0,0) **/ +/** NOTE: Extra WAIT at end for VGB (requires waits after signal assign) **/ +/** **/ +/*****************************************************************************/ + +void +circ48::entry() +{ + sc_signed x(4); + sc_signed y(4); + sc_signed x_end(4); + sc_signed y_end(4); + sc_signed diff(8); + bool first; + + // reset initialization + + out_wr.write( 0 ); // Initialize at time zero ???? + out_sel.write( 0 ); + + // setup counter-clockwise circle generation + + while(true) { // Reset_loop + x_end = 4; + x = x_end; + diff = 0; + diffs.write(diff); + y_end = 4; + y = y_end; + first = true; + wait(); + + // perform counter-clockwise circle generation + + while(first || (x != x_end) || (y != y_end)) { // Main_loop + first = false; + diff = diff + 1; + + if (diff > 1) { + if ((x >= 0) && (y >= 0)) { + diff = diff - x - x; + x = x - 1; + } + else { // else_1_begin + if ((x < 0) && (y >= 0)) { + diff = diff - y - y; + y = y - 1; + } + else { // else_2_begin + if ((x < 0) && (y < 0)) { + diff = diff + x + x; + x = x + 1; + } + else { + diff = diff + y + y; + y = y + 1; + } + } // else_2_end + } // else_1_end + } + else { + if ((x >= 0) && (y >= 0)) { + diff = diff + y + y; + y = y + 1; + } + else { // else_3_begin + if ((x < 0) && (y >= 0)) { + diff = diff - x - x; + x = x - 1; + } + else { // else_4_begin + if ((x < 0) && (y < 0)) { + diff = diff - y - y; + y = y - 1; + } + else { + diff = x + x; + x = x + 1; + } + } // else_4_end + } // else_3_end + } + + // send the intermediate x value to port + + out_sel.write(0); // Select x + out_wr.write(1); // Output ready signal + out_xy.write(x); + diffs.write(diff); + wait(); + + // handshake x.. + + do { wait(); } while (x_ok == 0); + out_wr.write(0); + wait(); + + // send the intermediate y value to port + + out_sel.write(1); // Select y + out_wr.write(1); // Output ready signal + out_xy.write(y); + wait(); + + // handshake y.. + + do { wait(); } while (y_ok == 0); + out_wr.write(0); + wait(); + } // End of Main_loop + } // End of Reset_loop +} diff --git a/src/systemc/tests/systemc/misc/synth/circle/common.h b/src/systemc/tests/systemc/misc/synth/circle/common.h new file mode 100644 index 000000000..3ea41ad75 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_bv<8> bool_vector; +typedef sc_signal<bool_vector> signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/synth/circle/golden/circ48.log b/src/systemc/tests/systemc/misc/synth/circle/golden/circ48.log new file mode 100644 index 000000000..136e1c7c1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/golden/circ48.log @@ -0,0 +1,21 @@ +SystemC Simulation + + FINAL MEMORY VALUES +Memory Location 1 : 0000000000000000 +Memory Location 2 : 0000000111100000 +Memory Location 3 : 0000011101111000 +Memory Location 4 : 0001110001110000 +Memory Location 5 : 0001000000010000 +Memory Location 6 : 0011000000011000 +Memory Location 7 : 0010000000001000 +Memory Location 8 : 0010000000001100 +Memory Location 9 : 0011000000001100 +Memory Location 10 : 0001000000001000 +Memory Location 11 : 0001100000011000 +Memory Location 12 : 0000100000110000 +Memory Location 13 : 0000111011100000 +Memory Location 14 : 0000001110000000 +Memory Location 15 : 0000000000000000 +Memory Location 16 : 0000000000000000 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/circle/tb.h b/src/systemc/tests/systemc/misc/synth/circle/tb.h new file mode 100644 index 000000000..3004bb35c --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/circle/tb.h @@ -0,0 +1,196 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "common.h" + +SC_MODULE( testbench ) +{ + SC_HAS_PROCESS( testbench ); + + sc_in_clk clk; + + sc_out<bool> reset; + sc_out<bool> x_ok; + sc_out<bool> y_ok; + sc_in<bool> data_ready; + sc_in<bool> select_xy; + sc_in<bool_vector> coord_xy; + + void entry(); + + testbench( sc_module_name name_, + const sc_clock& clk_, + sc_signal<bool>& reset_, + sc_signal<bool>& x_ok_, + sc_signal<bool>& y_ok_, + const sc_signal<bool>& data_ready_, + const sc_signal<bool>& select_xy_, + const signal_bool_vector& coord_xy_ ) + : sc_module( name_ ) + { + clk( clk_ ); + reset( reset_ ); + x_ok( x_ok_ ); + y_ok( y_ok_ ); + data_ready( data_ready_ ); + select_xy( select_xy_ ); + coord_xy( coord_xy_ ); + SC_CTHREAD( entry, clk.neg() ); + } +}; + +sc_bv<16> mem[17]; + +void +testbench::entry() +{ + bool_vector x_coord; + bool_vector y_coord; + int x_flag = 0; + int y_flag = 0; + int i; // Counter variable + int x = 0; // Memory location of x_coord + int y = 1; // Memory location of y_coord + + // reset initialization + + reset.write(1); + x_ok.write(0); + y_ok.write(0); + wait(); + reset.write(0); + wait(); + + // fill display memory with zeros + + for (i = 1; i < 17; i++) + mem[i] = 0; + + // capture of (x,y) coordinates + + while(true) { + + // wait for new x or y coordinate to be calculated + + do { wait(); } while (data_ready == 0); + + // capture x coordinate + + if(select_xy.read() == 0) { + x_coord = coord_xy.read(); + x_flag = x_flag + 1; + x_ok.write(1); + } + + // capture y coordinate + + if(select_xy.read() == 1) { + y_coord = coord_xy.read(); + y_flag = y_flag + 1; + y_ok.write(1); + } + + wait(); + x_ok.write(0); + y_ok.write(0); + + // debug display of coordinate sets + /* + if (x_flag == y_flag) { + cout << " Coordinate Set #" << x_flag + << " X = " << x_coord.to_int() + << " Y = " << y_coord.to_int() + << endl; + } + */ + + // conversion of x coordinate values to memory column locations + + if (x_coord.to_int() == -8) x = 15; + if (x_coord.to_int() == -7) x = 14; + if (x_coord.to_int() == -6) x = 13; + if (x_coord.to_int() == -5) x = 12; + if (x_coord.to_int() == -4) x = 11; + if (x_coord.to_int() == -3) x = 10; + if (x_coord.to_int() == -2) x = 9; + if (x_coord.to_int() == -1) x = 8; + if (x_coord.to_int() == 0) x = 7; + if (x_coord.to_int() == 1) x = 6; + if (x_coord.to_int() == 2) x = 5; + if (x_coord.to_int() == 3) x = 4; + if (x_coord.to_int() == 4) x = 3; + if (x_coord.to_int() == 5) x = 2; + if (x_coord.to_int() == 6) x = 1; + if (x_coord.to_int() == 7) x = 0; + + // conversion of y coordinate values to memory row locations + + if (y_coord.to_int() == -8) y = 16; + if (y_coord.to_int() == -7) y = 15; + if (y_coord.to_int() == -6) y = 14; + if (y_coord.to_int() == -5) y = 13; + if (y_coord.to_int() == -4) y = 12; + if (y_coord.to_int() == -3) y = 11; + if (y_coord.to_int() == -2) y = 10; + if (y_coord.to_int() == -1) y = 9; + if (y_coord.to_int() == 0) y = 8; + if (y_coord.to_int() == 1) y = 7; + if (y_coord.to_int() == 2) y = 6; + if (y_coord.to_int() == 3) y = 5; + if (y_coord.to_int() == 4) y = 4; + if (y_coord.to_int() == 5) y = 3; + if (y_coord.to_int() == 6) y = 2; + if (y_coord.to_int() == 7) y = 1; + + // turn bit high in memory for calculated coordinate + + mem[y][x] = 1; + + // stop simulation after 100 coordinates + + if (y_flag == 100) break; + + } // End of while loop + + cout << "\n\t FINAL MEMORY VALUES" << endl; + + for (i = 1; i < 17; i++) + cout << "Memory Location " << i + << " : \t" << mem[i] << endl; + + sc_stop(); +} diff --git a/src/systemc/tests/systemc/misc/synth/combo/share/golden/share.log b/src/systemc/tests/systemc/misc/synth/combo/share/golden/share.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/share/golden/share.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/combo/share/share.cpp b/src/systemc/tests/systemc/misc/synth/combo/share/share.cpp new file mode 100644 index 000000000..44cd9fb59 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/share/share.cpp @@ -0,0 +1,50 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + share.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +sc_signed +share( const sc_unsigned& u, + const sc_unsigned& v ) +{ + return (u - v) * (v + u); +} + +int +sc_main( int, char** argv ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/combo/switch3/golden/switch3.log b/src/systemc/tests/systemc/misc/synth/combo/switch3/golden/switch3.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/switch3/golden/switch3.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/combo/switch3/switch3.cpp b/src/systemc/tests/systemc/misc/synth/combo/switch3/switch3.cpp new file mode 100644 index 000000000..f464142ae --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/switch3/switch3.cpp @@ -0,0 +1,65 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + switch3.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +short +select( int a, int b, int c ) +{ + sc_signed x(7); + + switch ((c >> 2) & 3) { + default: + case 0: + x = a + b; + return x.to_int(); + case 1: + x = a - b; + return x.to_int(); + case 2: + x = (a >> 16) + (b << 16); + return x.to_int(); + case 3: + x = (a << 16) - (b >> 16); + return x.to_int(); + } +} + +int +sc_main( int, char** argv ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/combo/switch4/golden/switch4.log b/src/systemc/tests/systemc/misc/synth/combo/switch4/golden/switch4.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/switch4/golden/switch4.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/combo/switch4/switch4.cpp b/src/systemc/tests/systemc/misc/synth/combo/switch4/switch4.cpp new file mode 100644 index 000000000..f467aebc0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/switch4/switch4.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + switch4.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +short +select( int a, int b, int c ) +{ + sc_signed x(7); + sc_signed y(9); + + switch ((c >> 2) & 3) { + case 0: + x = a + b; + return x.to_int(); + case 1: + x = a - b; + break; + case 2: + x = (a >> 16) + (b << 16); + return x.to_int(); + case 3: + x = (a << 16) - (b >> 16); + break; + } + + y = 2 * x; + return y.to_int(); +} + +int +sc_main( int, char** argv ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/combo/switch5/golden/switch5.log b/src/systemc/tests/systemc/misc/synth/combo/switch5/golden/switch5.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/switch5/golden/switch5.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/combo/switch5/switch5.cpp b/src/systemc/tests/systemc/misc/synth/combo/switch5/switch5.cpp new file mode 100644 index 000000000..36685e487 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/switch5/switch5.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + switch5.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +unsigned short +select( unsigned a, unsigned b, unsigned c ) +{ + sc_unsigned x(7); + sc_unsigned y(9); + + switch ((c >> 2) & 3) { + case 0: + x = a + b; + return x.to_uint(); + case 1: + x = a - b; + break; + case 2: + x = (a >> 16) + (b << 16); + return x.to_uint(); + case 3: + x = (a << 16) - (b >> 16); + break; + } + + y = 2 * x; + return y.to_uint(); +} + +int +sc_main( int, char** argv ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/combo/switch6/golden/switch6.log b/src/systemc/tests/systemc/misc/synth/combo/switch6/golden/switch6.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/switch6/golden/switch6.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/combo/switch6/switch6.cpp b/src/systemc/tests/systemc/misc/synth/combo/switch6/switch6.cpp new file mode 100644 index 000000000..84e489e76 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/combo/switch6/switch6.cpp @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + switch6.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +unsigned short +select( unsigned a, unsigned b, unsigned c ) +{ + sc_unsigned x(7); + sc_unsigned y(9); + + switch ((c >> 2) & 3) { + case 0: + x = a + b; + if (a > 23349212) { + x = x + 1; + break; + } else { + x = x - 1; + } + return x.to_uint(); + case 1: + x = a - b; + break; + case 2: + x = (a >> 16) + (b << 16); + return x.to_uint(); + case 3: + x = (a << 16) - (b >> 16); + if (b < 234328112) { + x = x - 1; + break; + } else { + x = x + 1; + return x.to_uint(); + } + break; + } + + y = 2 * x; + return y.to_uint(); +} + +int +sc_main( int, char** argv ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/define.h b/src/systemc/tests/systemc/misc/synth/concat/fncall/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/golden/test.log b/src/systemc/tests/systemc/misc/synth/concat/fncall/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/main.cpp b/src/systemc/tests/systemc/misc/synth/concat/fncall/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.cpp b/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.h b/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.cpp b/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.h b/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/test.cpp b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.cpp new file mode 100644 index 000000000..1cb0672fc --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.cpp @@ -0,0 +1,134 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// +// Verifies the functionality of concanetation operation. +// Operands are arguments to a function +// +// Author: PRP +// Date Created: 19 Feb 99 +// + + +#include "systemc.h" +#include "test.h" + +sc_lv_base AND_fn (const sc_lv_base &a, const sc_lv_base &b) +{ + return a | b; +} + +sc_lv_base OR_fn (const sc_lv_base &a, const sc_lv_base &b) +{ + return a & b; +} + +void test::entry() +{ + sc_lv<8> a; + sc_lv<8> b; + sc_lv<8> c; + sc_lv<8> d; + sc_lv<24> e; + sc_lv<24> f; + + sc_logic k; + sc_logic n; + sc_logic m, o, p, q, r, s, t, u; + + sc_lv<32> x; + sc_lv<32> y; + sc_lv<32> z; + sc_lv<32> z1; + + + while (true) { + + wait (); + + a = "00000000"; // 0 + b = "00000001"; // 1 + c = "00000011"; // 3 + d = "00001111"; // 15 + e = "000000000000000000000001"; // 1 + f = "000000000000000000001010"; // 10 + + // =============== Array + Array ==================================== + // variable + variable, cascading + x = OR_fn ((a, b, c, d), (d, c, b, a)); + // x = 00001111 00000011 00000011 00001111 + + // variable + constant, cascading, composition + y = AND_fn (((a, b, c), "00000000"), (d, "00000000", b, a)); + // y = 00000000 00000000 00000001 00000000 + + // constant + constant + z = OR_fn (( sc_lv_base( "0000000000000000" ), "1000000000000000"), x); + // z = 00001111 00000011 10000011 00001111 + + z = z & (~y); + // z = 00001111 00000011 10000010 00001111 + + // =============== Array (variable) + Scalar ============================== + + n = '1'; + o = '0'; + z = OR_fn (z, ( sc_lv_base( n ), "000000000000000", "0000000000000000")); + // z = 10001111 00000011 10000010 00001111 + + z = OR_fn (z, ( sc_lv_base( "00000000" ), o, n, d, "00000000000000")); + // z = 10001111 01000011 11000010 00001111 + + k = '1'; + z = OR_fn (z, ( sc_lv_base( "00000000" ), "00", k, "00000", "0000000000000000")); + // z = 10001111 01100011 11000010 00001111 + + // =============== Null Vector ==================================== + + z = AND_fn (z, (( sc_lv_base( o ), sc_lv_base( k ), "111111"), "111111111111111111111111")); + // z = 00001111 01100011 11000010 00001111 + + // =============== LHS/RHS of different widths ============================== + + z1 = OR_fn (z, sc_lv_base( "00000000000000000000000000000000" )); // length of string = 32 + + o1 = z.to_int(); // o1 = 00001111 01100011 11000010 00001111 + wait(); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/test.f b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.f new file mode 100644 index 000000000..050983dc0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.f @@ -0,0 +1,4 @@ +fncall/test.cpp +fncall/tb.cpp +fncall/monitor.cpp +fncall/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/concat/fncall/test.h b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/fncall/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/define.h b/src/systemc/tests/systemc/misc/synth/concat/lvalue/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/golden/test.log b/src/systemc/tests/systemc/misc/synth/concat/lvalue/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/main.cpp b/src/systemc/tests/systemc/misc/synth/concat/lvalue/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.cpp b/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.h b/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.cpp b/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.h b/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.cpp b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.cpp new file mode 100644 index 000000000..e20874af6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.cpp @@ -0,0 +1,131 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// +// Verifies the functionality of concanetation operation. +// Operands form the rvalue of an assignment +// +// Author: PRP +// Date Created: 19 Feb 99 +// + + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + sc_lv<8> a; + sc_lv<8> b; + sc_lv<8> c; + sc_lv<8> d; + sc_lv<24> e; + sc_lv<24> f; + + // sc_logic k; + // sc_logic n; + // sc_logic m, o, p, q, r, s, t, u; + sc_lv<1> k, n, m, o, p, q, r, s, t, u; + + sc_lv<32> x; + sc_lv<32> y; + sc_lv<32> z; + + int i,j; + + while (true) { + + wait (); + + + b = "00000001"; // 1 + c = "00000011"; // 3 + d = "00001111"; // 15 + + // =============== Array + Array ==================================== + + (a, f) = "00000000000000000000000000000011"; // a = 0, f = 3 + + // =============== Cascading ==================================== + // cascading array variables + (a, f) = (b, c, d, a); + // a = 00000001 f = "00000011 00001111 00000000" + z = (a, f); + + // composing cascaded array variables + x = ( sc_lv_base( "00000011" ), "00000011", "00000011", "00000101"); + (a, (b, c, d)) = x; + z = z | x; // z = 00000011 00000011 00001111 00000101 + + // =============== Array (variable) + Scalar ============================== + + (b, c, d, a.range (7, 2), k, n) = (a, b, c, d); + // b = 00000011 c = 00000011 d = 00000011 a = 00000111 + // k = 0 n = 1 + z = z | (a, b, c, d); // z = 00000111 00000011 00001111 00000111 + + ( k, m, a.range (5, 0)) = z.range (15, 8); + // k = 0 m = 0 a = 00001111 + z = z | ( sc_lv_base( n ), m, k, n, "0000", a, "0000000000000000"); + // z = 10010111 00001111 00001111 00000111 + + // =============== Null Vector ==================================== + + ( m, n, o, p, q, r, s, t ) = "11011010"; + a = ( sc_lv_base( s ), t, q, r, o, m, n, p); // a = "10100111" + z = (z.range (31, 8), a); // z = 10010111 00001111 00001111 10100111 + + b = "00000000"; + + z = z | (b, b, b, z.range (7, 0)); + + // =============== LHS/RHS of different widths ============================== + + (x.range (15, 0), x.range (31, 16)) = ("1001011100001111000011111010011101"); + // RHS is (z, "01") + // x = 00111110 10011101 01011100 00111100 + + (z.range (31, 16), z.range (15, 0)) = (x.range (7, 0), x.range (23, 16), + x.range (15, 8), x.range (31, 24)); + // z = 00111100 10011101 01011100 00111110 + + o1 = z.to_int(); + wait(); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.f b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.f new file mode 100644 index 000000000..5fccdcdd7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.f @@ -0,0 +1,4 @@ +lvalue/test.cpp +lvalue/tb.cpp +lvalue/monitor.cpp +lvalue/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.h b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/lvalue/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/define.h b/src/systemc/tests/systemc/misc/synth/concat/rvalue/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/golden/test.log b/src/systemc/tests/systemc/misc/synth/concat/rvalue/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/main.cpp b/src/systemc/tests/systemc/misc/synth/concat/rvalue/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.cpp b/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.h b/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.cpp b/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.h b/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.cpp b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.cpp new file mode 100644 index 000000000..3a1c86093 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.cpp @@ -0,0 +1,160 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// +// Verifies the functionality of concanetation operation. +// Operands form the rvalue of an assignment +// +// Author: PRP +// Date Created: 19 Feb 99 +// + + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + sc_lv<8> a; + sc_lv<8> b; + sc_lv<8> c; + sc_lv<8> d; + sc_lv<24> e; + sc_lv<24> f; + + sc_logic k; + sc_logic n; + sc_logic m; + + sc_lv<32> x; + sc_lv<32> y; + sc_lv<32> z; + + sc_lv<2> kk; + + int i,j; + + while (true) { + + wait (); + + // ------- rvalue --------------------------------------------- + + a = "00000000"; // 0 + b = "00000001"; // 1 + c = "00000011"; // 3 + d = "00001111"; // 15 + e = "000000000000000000000001"; // 1 + f = "000000000000000000001010"; // 10 + + // =============== Array + Array ==================================== + // array constant + array constant + x = ( sc_lv_base( "000000000000000000000000" ), "00010000"); // x = 32 + + // array constant + array variable + y = ("000000000000000000000000", b); // y = 1 + z = x | y; // z = 00000000 00000000 00000000 00010001 + + // array variable + array constant + x = (a, "000000000000000000000011"); // x = 3 + z = z & x; // z = 00000000 00000000 00000000 00000001 + + // array variable + array variable + x = (a, f); // x = 10 + z = z | x; // z = 00000000 00000000 00000000 00001011 + + // =============== Cascading ==================================== + // cascading array variables + x = (a, b, c, d); // x = 00000000 00000001 00000011 00001111 + z = z & x; // z = 00000000 00000000 00000000 00001011 + + // cascading array constants + x = ( sc_lv_base( "00000011" ), "00000011", "00000011", "00000011"); + // x = 00000011 00000011 00000011 00000011 + z = z | x; // z = 00000011 00000011 00000011 00001011 + + // composing array concats + x = ( sc_lv_base( "00000011" ), ( sc_lv_base( "11111111" ), "00000011", "00000011")); + // x = 00000011 11111111 00000011 00000011 + z = z | x; // z = 00000011 11111111 00000011 00001011 + + // =============== Array (variable) + Scalar ============================== + // array variable + scalar constant + m = '0'; + n = '1'; + x = (a, b, c, d.range (6, 0), m); + // x = 00000000 00000001 00000011 00011110 + z = z | x; // z = 00000011 11111111 00000011 00011111 + + k = '1'; + // array variable + scalar variable + x = (a, b, k, c.range (6, 0), x.range (7, 0)); + // x = 00000000 00000001 10000001 00011110 + z = z & x; // z = 00000000 00000001 00000001 00011110 + + // =============== Null Vector ==================================== + // null vector - variable + kk = ~( sc_lv_base( k ), k); // "00" + z = (z.range (31, 2), kk); // z = 00000000 00000001 00000001 00011100 + + // null vector - constant + kk = ( sc_lv_base( n ), n); // "11" + z = (kk, z.range (29, 0)); // z = 11000000 00000001 00000001 00011100 + + // =============== Array (constant) + Scalar ============================== + // scalar constant + array constant + x = ( sc_lv_base( n ), "1111111000000000000000000000011"); + // x = 01111111 00000000 00000000 00000011 + z = z | x; // z = 11111111 00000001 00000001 00011111 + + // array constant + scalar variable + x = ( sc_lv_base( "1111111000000000000000000000011" ), k); + // x = 11111110 00000000 00000000 00000111 + z = z & x; // z = 11111110 00000000 00000000 00000111 + + // =============== LHS/RHS of different widths ============================== + // lhs and rhs of different widths + x = "100001111000000000000000000001111"; // warning should be issued + z = z & x; + // z = 00001110 00000000 00000000 00000111 + + o1 = z.to_int(); + wait(); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.f b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.f new file mode 100644 index 000000000..2399ece43 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.f @@ -0,0 +1,4 @@ +rvalue/test.cpp +rvalue/tb.cpp +rvalue/monitor.cpp +rvalue/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.h b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/concat/rvalue/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/golden/test1.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/golden/test1.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/golden/test1.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/interface.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/interface.h new file mode 100644 index 000000000..e2c229b67 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/interface.h @@ -0,0 +1,89 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + interface.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + const sc_signal<bool>& reset_sig; + + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4), + i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/test1.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/test1.cpp new file mode 100644 index 000000000..62a92a2db --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/test1.cpp @@ -0,0 +1,53 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test1.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "interface.h" + +void t::entry() +{ + int i; + + o1 = 1; + + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/golden/test2.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/golden/test2.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/golden/test2.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/interface.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/interface.h new file mode 100644 index 000000000..e2c229b67 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/interface.h @@ -0,0 +1,89 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + interface.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + const sc_signal<bool>& reset_sig; + + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4), + i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/test2.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/test2.cpp new file mode 100644 index 000000000..985092b65 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/test2.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test2.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "interface.h" + +void t::entry() +{ + int i; + + o3 = i1 + i2; + o3 = i1 + i2; + o3 = i1 + i2; + + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test3/golden/test3.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test3/golden/test3.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test3/golden/test3.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test3/interface.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test3/interface.h new file mode 100644 index 000000000..e2c229b67 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test3/interface.h @@ -0,0 +1,89 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + interface.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + const sc_signal<bool>& reset_sig; + + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4), + i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test3/test3.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test3/test3.cpp new file mode 100644 index 000000000..22ad8972f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test3/test3.cpp @@ -0,0 +1,59 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test3.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "interface.h" + +void t::entry() +{ + int i; + + if (i1 == 1) + { + o1 = 1; + } + o2 = i1 + i2; + o2 = i1 + i2; + + wait(); +} + + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/define.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/tb.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/test.cpp new file mode 100644 index 000000000..9beae954a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/test.cpp @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case line_label: 7.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j; + + { + int i; + + a:i = 2; + if (i == 2) + i = 4; + else + i = 7; + } + b:i = 3; + j = 5; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/test.f b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/test.f new file mode 100644 index 000000000..df637f6d7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/test.f @@ -0,0 +1,4 @@ +test1/test.cpp +test1/tb.cpp +test1/monitor.cpp +test1/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/test.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test1/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/define.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/tb.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/test.cpp new file mode 100644 index 000000000..323500d36 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/test.cpp @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case line_label: 8.cc +*/ + +#include "systemc.h" +#include "test.h" + + +void test::entry() +{ + int i,j; + + { + int i; + + a:i = 2; + if (i == 2) { + i = 5; + i = 4; + i = 5; + } + else + i = 7; + } + b:i = 3; + j = 5; + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/test.f b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/test.f new file mode 100644 index 000000000..0ff8be826 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/test.f @@ -0,0 +1,4 @@ +test2/test.cpp +test2/tb.cpp +test2/monitor.cpp +test2/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/test.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test2/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/define.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/tb.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/test.cpp new file mode 100644 index 000000000..b9a651cd6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/test.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case line_label: 9.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j; + + { + int i; + + a:i = 2; + if (i == 2) { + i = 7; + i = 4; + i = 5; + } + else + i = 7; + } + b:i = 3; + j = 5; + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/test.f b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/test.f new file mode 100644 index 000000000..f4bc5ed9f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/test.f @@ -0,0 +1,4 @@ +test3/test.cpp +test3/tb.cpp +test3/monitor.cpp +test3/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/test.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test3/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/define.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/tb.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/test.cpp new file mode 100644 index 000000000..965ab956f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/test.cpp @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case line_label: 10.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j; + + { + int i; + + a:i = 2; + if (i == 2) { + j = 0; + i = 7; + i = 4; + i = 5; + } + else + i = 7; + } + b:i = 3; + j = 5; + + wait(); + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/test.f b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/test.f new file mode 100644 index 000000000..4ac7cda08 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/test.f @@ -0,0 +1,4 @@ +test4/test.cpp +test4/tb.cpp +test4/monitor.cpp +test4/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/test.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test4/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/define.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/tb.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/test.cpp new file mode 100644 index 000000000..91cc0eb22 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/test.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case line_label: 11.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j; + + { + int i; + + a:i = 2; + if (i == 2) { + foobart: i = 7; + i = 4; + i = 5; + } + else + i = 7; + } + b:i = 3; + j = 5; + + wait(); + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/test.f b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/test.f new file mode 100644 index 000000000..48933f17e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/test.f @@ -0,0 +1,4 @@ +test5/test.cpp +test5/tb.cpp +test5/monitor.cpp +test5/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/test.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test5/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/define.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/tb.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/test.cpp new file mode 100644 index 000000000..29e13b1d4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/test.cpp @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case line_label: 7.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j; + + { + int i; + + a:i = 2; + if (i == 2) + { + foobart: i = 7; + i = 4; + i = 5; + } + else + i = 7; + } + b:i = 3; + j = 5; + + wait(); + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/test.f b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/test.f new file mode 100644 index 000000000..208a2e652 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/test.f @@ -0,0 +1,4 @@ +test6/test.cpp +test6/tb.cpp +test6/monitor.cpp +test6/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/test.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test6/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/define.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/tb.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/test.cpp new file mode 100644 index 000000000..c057884c3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/test.cpp @@ -0,0 +1,76 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case line_label: 13.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + { + int i; + + a:i = 2; + if (i == 2) + { + foobart: i = 7; + i = 4; + i = 5; + } + else + i = 7; + + y = 2; + if (y == 3) { + z = 1; + } else { + z = 2; + } + } + b:i = 3; + j = 5; + + wait(); + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/test.f b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/test.f new file mode 100644 index 000000000..772c5048e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/test.f @@ -0,0 +1,4 @@ +test7/test.cpp +test7/tb.cpp +test7/monitor.cpp +test7/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/test.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test7/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/1 b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/1 new file mode 100644 index 000000000..73e4da4d8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/1 @@ -0,0 +1,62 @@ +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + const char* NAME, + sc_clock_edge& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : sc_sync (NAME, CLK), reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/define.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/main.cpp new file mode 100644 index 000000000..134947889 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS , DUTY_CYCLE, 0, SC_NS ); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS , DUTY_CYCLE, 0, SC_NS ); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS , DUTY_CYCLE, 75, SC_NS ); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/tb.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/test.cpp new file mode 100644 index 000000000..e120e54b9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/test.cpp @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case line_label: 7.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + { + int i; + int x = 0; + + a:i = 2; + if (i == 2) + { + foobart: i = 7; + i = 4; + i = 5; + } + else + i = 7; + + y = 2; + if (y == 3) { + z = 1; + } else { + z = 2; + } + + switch (x) { + case 1: break; + case 3: break; + default: ; + } + } + b:i = 3; + j = 5; + + while (i == 4) { + j = 7; + y = 4; + i++; + + wait(); + } + do + { + j = 7; + y = 4; + i++; + + wait(); + } while (i < 4); + if (i == 4) { + i = 5; + } else { + i = 9; + } + + wait(); + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/test.f b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/test.f new file mode 100644 index 000000000..3607d345c --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/test.f @@ -0,0 +1,4 @@ +test8/test.cpp +test8/tb.cpp +test8/monitor.cpp +test8/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/test.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test8/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/define.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/tb.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/test.cpp new file mode 100644 index 000000000..abe2967d7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/test.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From PR 358 - Check that directive is accepted when followed + by a labelled statement +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int y,j,i; + + y = 3; + + i = 3; + + switch (i) { + case 0: + y = 1; + j = 2; + case 1: + y = y + 1; + break; + case 2: + y = y + 1; + j = 2; + default: + y = y + 1; + break; + } + j = 4; + j = 2; + pp: j = 8; + wait(); + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/test.f b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/test.f new file mode 100644 index 000000000..8ce95f804 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/test.f @@ -0,0 +1,4 @@ +test9/test.cpp +test9/tb.cpp +test9/monitor.cpp +test9/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/test.h b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/line_label/test9/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/define.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/tb.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/test.cpp new file mode 100644 index 000000000..11a11d34b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/test.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case misc: 18.sc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i; + + i = 4; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/test.f b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/test.f new file mode 100644 index 000000000..df637f6d7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/test.f @@ -0,0 +1,4 @@ +test1/test.cpp +test1/tb.cpp +test1/monitor.cpp +test1/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test1/test.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test1/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/define.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/tb.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/test.cpp new file mode 100644 index 000000000..b1c2968e0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/test.cpp @@ -0,0 +1,57 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case misc: 19.sc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i; + + i = 4; + + wait(); + + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/test.f b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/test.f new file mode 100644 index 000000000..0ff8be826 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/test.f @@ -0,0 +1,4 @@ +test2/test.cpp +test2/tb.cpp +test2/monitor.cpp +test2/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test2/test.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test2/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/define.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/tb.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/test.cpp new file mode 100644 index 000000000..92e432bd9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/test.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case misc: 20.sc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i; + + i = 4; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/test.f b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/test.f new file mode 100644 index 000000000..f4bc5ed9f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/test.f @@ -0,0 +1,4 @@ +test3/test.cpp +test3/tb.cpp +test3/monitor.cpp +test3/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test3/test.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test3/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/define.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/tb.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/test.cpp new file mode 100644 index 000000000..912d271f1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/test.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case misc: 21.sc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j=0,y=0,z=0; + + + for (i = 0; i < 7; i++) + { + i = z + + y; + y = z + j; + + wait(); + } + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/test.f b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/test.f new file mode 100644 index 000000000..4ac7cda08 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/test.f @@ -0,0 +1,4 @@ +test4/test.cpp +test4/tb.cpp +test4/monitor.cpp +test4/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test4/test.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test4/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/define.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/tb.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/test.cpp new file mode 100644 index 000000000..8216ac816 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/test.cpp @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case misc: 22.sc +*/ + +#include "systemc.h" +#include "test.h" + +int foobar (int a); + +void test::entry() +{ + int i,j=0,y=0,z=0; + + + for (i = 0; i < 7; i++) + { + z = z + + y; + y = z + j; + y = foobar (z); + wait(); + } + wait(); + +} + +int foobar (int a) +{ + return a + 1; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/test.f b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/test.f new file mode 100644 index 000000000..48933f17e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/test.f @@ -0,0 +1,4 @@ +test5/test.cpp +test5/tb.cpp +test5/monitor.cpp +test5/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test5/test.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test5/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/define.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/tb.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/test.cpp new file mode 100644 index 000000000..138f5ff1e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/test.cpp @@ -0,0 +1,89 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case misc: 23.sc +*/ + +#include "systemc.h" +#include "test.h" + +int foobar (int a, int b) +{ + return a + b; +} + +void test::entry() +{ + int i,j=0,y=0,z=0; + + + for (i = 0; i < 7; i++) + { + i = z + + y; + y = z + j; + y = z + j + i; + y = z + j + i; + y = z + j; + y = z + j + i; + y = z + (j - i); + y = z + (j - i); + y = z + (j - i); + y = z + (j - i); + + foobar (z,y); + foobar ( z,y); + y = foobar (z,y); + y = foobar ( z, y); + y = foobar ( + y, z); + y = foobar (z,y); + y = foobar (z,y) + ; + y = foobar (z,y); + y = foobar (foobar (y,z),y); + y = foobar (foobar ( z,y), y); + + wait(); + } + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/test.f b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/test.f new file mode 100644 index 000000000..208a2e652 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/test.f @@ -0,0 +1,4 @@ +test6/test.cpp +test6/tb.cpp +test6/monitor.cpp +test6/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test6/test.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test6/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/define.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/tb.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/test.cpp new file mode 100644 index 000000000..c474d4c5b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/test.cpp @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directive line_label. + Author: PRP + From Test Case misc: 24.sc +*/ + +#include "systemc.h" +#include "test.h" + +int a(int b) +{ + int i,j,y,z; + + + YY: for (i = 0; i < 7; i++) + { + z = 1; + } + + ::sc_core::wait(); + return 0; +} + +void test::entry() +{ + a(1); + ::sc_core::wait(); +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/test.f b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/test.f new file mode 100644 index 000000000..772c5048e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/test.f @@ -0,0 +1,4 @@ +test7/test.cpp +test7/tb.cpp +test7/monitor.cpp +test7/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/misc/test7/test.h b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/misc/test7/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/golden/test1.log b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/golden/test1.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/golden/test1.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/interface.h b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/interface.h new file mode 100644 index 000000000..e2c229b67 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/interface.h @@ -0,0 +1,89 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + interface.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + const sc_signal<bool>& reset_sig; + + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4), + i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/test1.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/test1.cpp new file mode 100644 index 000000000..62774b719 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test1/test1.cpp @@ -0,0 +1,53 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test1.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "interface.h" + +void t::entry() +{ + int i; + + o1 = i1 + i2; + + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/golden/test2.log b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/golden/test2.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/golden/test2.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/interface.h b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/interface.h new file mode 100644 index 000000000..e2c229b67 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/interface.h @@ -0,0 +1,89 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + interface.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + const sc_signal<bool>& reset_sig; + + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4), + i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/test2.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/test2.cpp new file mode 100644 index 000000000..40824db36 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test2/test2.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test2.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "interface.h" + +int x (int y, int z) +{ + return y+z; +} + +void t::entry() +{ + o1 = i1 + i2; + o2 = i1 + i2; + o3 = x (1,2); + o4 = x (1,2); + o5 = x ( 1,2); + o5 = x ( x(1,2),2); + o5 = x ( 1, x(1,2)); + + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/golden/test3.log b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/golden/test3.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/golden/test3.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/interface.h b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/interface.h new file mode 100644 index 000000000..e2c229b67 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/interface.h @@ -0,0 +1,89 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + interface.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + const sc_signal<bool>& reset_sig; + + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), i3(I3), i4(I4), + i5(I5), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/test3.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/test3.cpp new file mode 100644 index 000000000..179ac9b46 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/misc/test3/test3.cpp @@ -0,0 +1,53 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test3.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "interface.h" + +void t::entry() +{ + int i; + + o1 = i1 + i2; + o1 = i1 + i2; + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.cpp new file mode 100644 index 000000000..356af707a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.cpp @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies resource directive + Author: PRP + From Test Case resource: 25.cc +*/ +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + + int i,j; + + i = 9 + i1.read(); + o1 = 8 + i; + o2 = i2; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.f new file mode 100644 index 000000000..df637f6d7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.f @@ -0,0 +1,4 @@ +test1/test.cpp +test1/tb.cpp +test1/monitor.cpp +test1/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test1/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.cpp new file mode 100644 index 000000000..33c500faf --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +/* + Verifies resource directive + Author: PRP + From Test Case resource: 26.cc +*/ +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + + YY: for (i = 0; i < 7; i++) + { + y = i - 1; + j = i + 2; + } + + o1 = y + j; + wait(); + + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.f new file mode 100644 index 000000000..0ff8be826 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.f @@ -0,0 +1,4 @@ +test2/test.cpp +test2/tb.cpp +test2/monitor.cpp +test2/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test2/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.cpp new file mode 100644 index 000000000..0e7dea5fe --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies resource directive + Author: PRP + From Test Case resource: 28.cc +*/ +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + + YY: for (i = 0; i < 7; i++) + { + y = i - 1; + j = i + 2; + } + o1 = y + j; + + wait(); + + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.f new file mode 100644 index 000000000..f4bc5ed9f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.f @@ -0,0 +1,4 @@ +test3/test.cpp +test3/tb.cpp +test3/monitor.cpp +test3/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test3/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.cpp new file mode 100644 index 000000000..1be7a4d86 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies resource directive + Author: PRP + From Test Case resource: 29.cc +*/ +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + + YY: for (i = 0; i < 7; i++) + { + y = i - 1; + j = i + 2; + } + o1 = y + j; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.f new file mode 100644 index 000000000..4ac7cda08 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.f @@ -0,0 +1,4 @@ +test4/test.cpp +test4/tb.cpp +test4/monitor.cpp +test4/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test4/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.cpp new file mode 100644 index 000000000..d579684ab --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies resource directive + Author: PRP + From Test Case resource: 30.cc +*/ +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + + YY: for (i = 0; i < 7; i++) + { + y = i - 1; + j = i + 2; + } + y = i - 1; + j = i + 2; + o1 = y + j; + + wait(); + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.f new file mode 100644 index 000000000..48933f17e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.f @@ -0,0 +1,4 @@ +test5/test.cpp +test5/tb.cpp +test5/monitor.cpp +test5/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test5/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/define.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.cpp new file mode 100644 index 000000000..485e38bcf --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies resource directive + Author: PRP + From Test Case resource: 31.cc +*/ +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i; + int a[10], b[12]; + + for (i = 0; i < 10; i++) { + a[i] = 7; + b[i] = 6; + } + + wait(); + o1 = b[i]; + wait(); + +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.f b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.f new file mode 100644 index 000000000..208a2e652 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.f @@ -0,0 +1,4 @@ +test6/test.cpp +test6/tb.cpp +test6/monitor.cpp +test6/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.h b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/resource/test6/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/define.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/tb.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/test.cpp new file mode 100644 index 000000000..bcfdbea64 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/test.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directives translate_on/translate_off + Author: PRP + From Test Case translate_on: 15.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + a:i = 2; + if (i == 2) + { + foobart: i = 7; + i = 4; + i = 5; + } + else + i = 7; + + y = 3; + y = 2; + if (y == 3) { + z = 1; + } else { + z = 2; + } + + b:i = 3; + j = 5; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/test.f b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/test.f new file mode 100644 index 000000000..df637f6d7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/test.f @@ -0,0 +1,4 @@ +test1/test.cpp +test1/tb.cpp +test1/monitor.cpp +test1/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/test.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test1/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/define.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/tb.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/test.cpp new file mode 100644 index 000000000..c0e17e185 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/test.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directives translate_on/translate_off + Author: PRP + From Test Case translate_on: 16.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + + i = 7; + + y = 3; + + y = 2; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/test.f b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/test.f new file mode 100644 index 000000000..0ff8be826 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/test.f @@ -0,0 +1,4 @@ +test2/test.cpp +test2/tb.cpp +test2/monitor.cpp +test2/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/test.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test2/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/define.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/tb.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/test.cpp new file mode 100644 index 000000000..02fe30454 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/test.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directives translate_on/translate_off + Author: PRP + From Test Case translate_on: 17.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i; + + i = 4; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/test.f b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/test.f new file mode 100644 index 000000000..f4bc5ed9f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/test.f @@ -0,0 +1,4 @@ +test3/test.cpp +test3/tb.cpp +test3/monitor.cpp +test3/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/test.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/test.h new file mode 100644 index 000000000..07408cfa9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test3/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/define.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/tb.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/test.cpp new file mode 100644 index 000000000..6290e9682 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/test.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directives synthesis_on/synthesis_off + Author: PRP + From Test Case translate_on: syn1.cc +*/ + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + + i = 7; + + y = 3; + + y = 2; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/test.f b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/test.f new file mode 100644 index 000000000..4ac7cda08 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/test.f @@ -0,0 +1,4 @@ +test4/test.cpp +test4/tb.cpp +test4/monitor.cpp +test4/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/test.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/test.h new file mode 100644 index 000000000..7a9366b25 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test4/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is( reset_sig, true ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/define.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/golden/test.log b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/main.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/main.cpp new file mode 100644 index 000000000..852905b57 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/main.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/monitor.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/monitor.cpp new file mode 100644 index 000000000..103437eee --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/monitor.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/monitor.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/monitor.h new file mode 100644 index 000000000..a827f7c8a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/monitor.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/tb.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/tb.cpp new file mode 100644 index 000000000..dfc57d75a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/tb.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/tb.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/test.cpp b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/test.cpp new file mode 100644 index 000000000..2fec4ea5b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/test.cpp @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Verifies directives synthesis_on/synthesis_off + Author: PRP + From Test Case translate_on: syn2.cc +*/ + + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,y,z; + + + i = 7; + + y = 3; + + y = 2; + o1 = 7; + if (i2 == 4) { + o2 = 8; + } else { + o2 = 9; + } + + o1 = 6; + + wait(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/test.f b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/test.f new file mode 100644 index 000000000..48933f17e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/test.f @@ -0,0 +1,4 @@ +test5/test.cpp +test5/tb.cpp +test5/monitor.cpp +test5/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/test.h b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/directives/translate_on/test5/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/gcd/gcd.cpp b/src/systemc/tests/systemc/misc/synth/gcd/gcd.cpp new file mode 100644 index 000000000..2b6c45b21 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/gcd/gcd.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + gcd.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( gcd_cc ) +{ + SC_HAS_PROCESS( gcd_cc ); + + sc_in_clk clk; + + const sc_signal<bool>& reset; + const sc_signal<unsigned>& a; + const sc_signal<unsigned>& b; + sc_signal<unsigned>& c; + sc_signal<bool>& ready; + + gcd_cc( sc_module_name NAME, + sc_clock& CLK, + const sc_signal<bool>& RESET, + const sc_signal<unsigned>& A, + const sc_signal<unsigned>& B, + sc_signal<unsigned>& C, + sc_signal<bool>& READY ) + : + reset(RESET), + a(A), + b(B), + c(C), + ready(READY) + { + clk( CLK ); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + } + + void entry(); +}; + +void +gcd_cc::entry() +{ + unsigned tmp_a; + wait(); // Note that this wait() is required, otherwise, + // the reset is wrong! This is a problem with BC, + // not our frontend. + + while (true) { + unsigned tmp_b; + + c = tmp_a; + ready = true; + wait(); + + tmp_a = a; + tmp_b = b; + ready = false; + wait(); + + while (tmp_b != 0) { + + unsigned tmp_c = tmp_a; + tmp_a = tmp_b; + wait(); + + while (tmp_c >= tmp_b) { + tmp_c = tmp_c - tmp_b; + wait(); + } + + tmp_b = tmp_c; + wait(); + } + } +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/gcd/golden/gcd.log b/src/systemc/tests/systemc/misc/synth/gcd/golden/gcd.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/gcd/golden/gcd.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test1/define.h b/src/systemc/tests/systemc/misc/synth/inlining/test1/define.h new file mode 100644 index 000000000..9b4c36e61 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test1/define.h @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(5*CLOCK_PERIOD) +#define single_cycle wait() +#define set_value(var,val) wait(EVENT_TIME); var = val; wait(CLOCK_PERIOD - EVENT_TIME) +#define test_value(actual, expected) \ + wait (TEST_TIME); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait (CLOCK_PERIOD - TEST_TIME) +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test1/golden/test1.log b/src/systemc/tests/systemc/misc/synth/inlining/test1/golden/test1.log new file mode 100644 index 000000000..1f4fa7045 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test1/golden/test1.log @@ -0,0 +1,3 @@ +SystemC Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test1/main.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test1/main.cpp new file mode 100644 index 000000000..60cc94641 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test1/main.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test1/tb.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test1/tb.cpp new file mode 100644 index 000000000..a412a90f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test1/tb.cpp @@ -0,0 +1,48 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test1/tb.h b/src/systemc/tests/systemc/misc/synth/inlining/test1/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test1/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test1/test.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test1/test.cpp new file mode 100644 index 000000000..e8426d024 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test1/test.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "define.h" +#include "test.h" + +int incr (int x, int y) +{ + return x + y; +} + + +void test::entry() +{ + int i; + + wait(); + + o1 = incr (i1.read(), i2.read()); +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test1/test.h b/src/systemc/tests/systemc/misc/synth/inlining/test1/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test1/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test1/test1.f b/src/systemc/tests/systemc/misc/synth/inlining/test1/test1.f new file mode 100644 index 000000000..77d5ef1d5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test1/test1.f @@ -0,0 +1,3 @@ +test1/test.cpp +test1/tb.cpp +test1/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test2/define.h b/src/systemc/tests/systemc/misc/synth/inlining/test2/define.h new file mode 100644 index 000000000..9b4c36e61 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test2/define.h @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(5*CLOCK_PERIOD) +#define single_cycle wait() +#define set_value(var,val) wait(EVENT_TIME); var = val; wait(CLOCK_PERIOD - EVENT_TIME) +#define test_value(actual, expected) \ + wait (TEST_TIME); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait (CLOCK_PERIOD - TEST_TIME) +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test2/golden/test2.log b/src/systemc/tests/systemc/misc/synth/inlining/test2/golden/test2.log new file mode 100644 index 000000000..1f4fa7045 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test2/golden/test2.log @@ -0,0 +1,3 @@ +SystemC Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test2/main.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test2/main.cpp new file mode 100644 index 000000000..60cc94641 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test2/main.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test2/tb.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test2/tb.cpp new file mode 100644 index 000000000..a412a90f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test2/tb.cpp @@ -0,0 +1,48 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test2/tb.h b/src/systemc/tests/systemc/misc/synth/inlining/test2/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test2/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test2/test.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test2/test.cpp new file mode 100644 index 000000000..b9d408d10 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test2/test.cpp @@ -0,0 +1,71 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +// +// Verifies function inlining +// +// Author: PRP +// Date Created: 26 Feb 99 +// + +#include "systemc.h" +#include "define.h" +#include "test.h" + + +int incr1 (int x, int y) +{ + return x + y; +} + + +int incr (int x, int y) +{ + return incr1 (x, y); +} + + +void test::entry() +{ + int i; + + wait(); + + i = incr (i1.read(), i2.read()); + o1 = i; +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test2/test.h b/src/systemc/tests/systemc/misc/synth/inlining/test2/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test2/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test2/test2.f b/src/systemc/tests/systemc/misc/synth/inlining/test2/test2.f new file mode 100644 index 000000000..6ff147280 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test2/test2.f @@ -0,0 +1,3 @@ +test2/test.cpp +test2/tb.cpp +test2/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test3/define.h b/src/systemc/tests/systemc/misc/synth/inlining/test3/define.h new file mode 100644 index 000000000..9b4c36e61 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test3/define.h @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(5*CLOCK_PERIOD) +#define single_cycle wait() +#define set_value(var,val) wait(EVENT_TIME); var = val; wait(CLOCK_PERIOD - EVENT_TIME) +#define test_value(actual, expected) \ + wait (TEST_TIME); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait (CLOCK_PERIOD - TEST_TIME) +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test3/golden/test.log b/src/systemc/tests/systemc/misc/synth/inlining/test3/golden/test.log new file mode 100644 index 000000000..1f4fa7045 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test3/golden/test.log @@ -0,0 +1,3 @@ +SystemC Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test3/main.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test3/main.cpp new file mode 100644 index 000000000..60cc94641 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test3/main.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test3/tb.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test3/tb.cpp new file mode 100644 index 000000000..a412a90f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test3/tb.cpp @@ -0,0 +1,48 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test3/tb.h b/src/systemc/tests/systemc/misc/synth/inlining/test3/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test3/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test3/test.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test3/test.cpp new file mode 100644 index 000000000..b40e892be --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test3/test.cpp @@ -0,0 +1,72 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +// +// Verifies function inlining +// +// Author: PRP +// Date Created: 26 Feb 99 +// + +#include "systemc.h" +#include "define.h" +#include "test.h" + + + +int incr (int x, int y) +{ + if (y > 0) + return y; + if (x > 0) + return x; + else + return x + y; +} + + +void test::entry() +{ + int i; + + wait(); + + i = incr (i1.read(), i2.read()); + o1 = i; +} + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test3/test.f b/src/systemc/tests/systemc/misc/synth/inlining/test3/test.f new file mode 100644 index 000000000..9cb5d8fb4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test3/test.f @@ -0,0 +1,3 @@ +test3/test.cpp +test3/tb.cpp +test3/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test3/test.h b/src/systemc/tests/systemc/misc/synth/inlining/test3/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test3/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test4/define.h b/src/systemc/tests/systemc/misc/synth/inlining/test4/define.h new file mode 100644 index 000000000..9b4c36e61 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test4/define.h @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(5*CLOCK_PERIOD) +#define single_cycle wait() +#define set_value(var,val) wait(EVENT_TIME); var = val; wait(CLOCK_PERIOD - EVENT_TIME) +#define test_value(actual, expected) \ + wait (TEST_TIME); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait (CLOCK_PERIOD - TEST_TIME) +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test4/golden/test.log b/src/systemc/tests/systemc/misc/synth/inlining/test4/golden/test.log new file mode 100644 index 000000000..1f4fa7045 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test4/golden/test.log @@ -0,0 +1,3 @@ +SystemC Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test4/main.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test4/main.cpp new file mode 100644 index 000000000..60cc94641 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test4/main.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test4/tb.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test4/tb.cpp new file mode 100644 index 000000000..a412a90f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test4/tb.cpp @@ -0,0 +1,48 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test4/tb.h b/src/systemc/tests/systemc/misc/synth/inlining/test4/tb.h new file mode 100644 index 000000000..306b5a4ae --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test4/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test4/test.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test4/test.cpp new file mode 100644 index 000000000..609bbf3eb --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test4/test.cpp @@ -0,0 +1,73 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +// +// Verifies function inlining +// +// Author: PRP +// Date Created: 26 Feb 99 +// + +#include "systemc.h" +#include "define.h" +#include "test.h" + + + +int incr (int x, int y) +{ + ::sc_core::wait (); + while (x < 4) { + ::sc_core::wait(); + return x; + } + ::sc_core::wait(); + return y; +} + + +void test::entry() +{ + int i; + + ::sc_core::wait(); + + i = incr (i1.read(), i2.read()); + o1 = i; + ::sc_core::wait(); +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test4/test.f b/src/systemc/tests/systemc/misc/synth/inlining/test4/test.f new file mode 100644 index 000000000..75eba86b7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test4/test.f @@ -0,0 +1,3 @@ +test4/test.cpp +test4/tb.cpp +test4/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test4/test.h b/src/systemc/tests/systemc/misc/synth/inlining/test4/test.h new file mode 100644 index 000000000..5596f1f8d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test4/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test5/define.h b/src/systemc/tests/systemc/misc/synth/inlining/test5/define.h new file mode 100644 index 000000000..9b4c36e61 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test5/define.h @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(5*CLOCK_PERIOD) +#define single_cycle wait() +#define set_value(var,val) wait(EVENT_TIME); var = val; wait(CLOCK_PERIOD - EVENT_TIME) +#define test_value(actual, expected) \ + wait (TEST_TIME); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait (CLOCK_PERIOD - TEST_TIME) +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test5/golden/test.log b/src/systemc/tests/systemc/misc/synth/inlining/test5/golden/test.log new file mode 100644 index 000000000..1f4fa7045 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test5/golden/test.log @@ -0,0 +1,3 @@ +SystemC Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test5/main.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test5/main.cpp new file mode 100644 index 000000000..60cc94641 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test5/main.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test5/tb.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test5/tb.cpp new file mode 100644 index 000000000..a412a90f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test5/tb.cpp @@ -0,0 +1,48 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test5/tb.h b/src/systemc/tests/systemc/misc/synth/inlining/test5/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test5/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test5/test.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test5/test.cpp new file mode 100644 index 000000000..25e8a4a7f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test5/test.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +// +// Verifies function inlining +// +// Author: PRP +// Date Created: 26 Feb 99 +// + +#include "systemc.h" +#include "test.h" + +int test::incr (int x) +{ + int a, b, c; + + a = x + 1; + b = a + x; + o1 = x + i2.read() + b; + return b + c; +} + +void test::entry() +{ + int i; + + wait(); + + o2 = incr (i1); + wait(); +} + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test5/test.f b/src/systemc/tests/systemc/misc/synth/inlining/test5/test.f new file mode 100644 index 000000000..ff087ee5b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test5/test.f @@ -0,0 +1,3 @@ +test5/test.cpp +test5/tb.cpp +test5/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test5/test.h b/src/systemc/tests/systemc/misc/synth/inlining/test5/test.h new file mode 100644 index 000000000..31bb57a4a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test5/test.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + int incr (int); + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test6/define.h b/src/systemc/tests/systemc/misc/synth/inlining/test6/define.h new file mode 100644 index 000000000..9b4c36e61 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test6/define.h @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(5*CLOCK_PERIOD) +#define single_cycle wait() +#define set_value(var,val) wait(EVENT_TIME); var = val; wait(CLOCK_PERIOD - EVENT_TIME) +#define test_value(actual, expected) \ + wait (TEST_TIME); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait (CLOCK_PERIOD - TEST_TIME) +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test6/golden/test.log b/src/systemc/tests/systemc/misc/synth/inlining/test6/golden/test.log new file mode 100644 index 000000000..1f4fa7045 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test6/golden/test.log @@ -0,0 +1,3 @@ +SystemC Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test6/main.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test6/main.cpp new file mode 100644 index 000000000..60cc94641 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test6/main.cpp @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "systemc.h" +#include "test.h" +#include "tb.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test6/tb.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test6/tb.cpp new file mode 100644 index 000000000..a412a90f4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test6/tb.cpp @@ -0,0 +1,48 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test6/tb.h b/src/systemc/tests/systemc/misc/synth/inlining/test6/tb.h new file mode 100644 index 000000000..5e76fb35d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test6/tb.h @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test6/test.cpp b/src/systemc/tests/systemc/misc/synth/inlining/test6/test.cpp new file mode 100644 index 000000000..e492286d8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test6/test.cpp @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + +// +// Verifies function inlining +// +// Author: PRP +// Date Created: 26 Feb 99 +// + +#include "systemc.h" +#include "test.h" + +void test::entry() +{ + int i,j,h, temp; + + wait (); + j = i1.read(); + for (i = 0; i < 4; i = i + 1) + { // Default: no unrolling + j = j + 1; + wait(); + } + wait (); + temp = 4+j; + modify (o1, temp); + h = (i1 > i2) ? i3 : i4; + o2 = h; + wait (); + i= 9; + noModify (i); + wait(); +} + + +void test::modify (sc_signal<int>& i, int& j) +{ + i = i1 + j; +} + +void test::noModify (int i) +{ + o3 = i; +} diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test6/test.f b/src/systemc/tests/systemc/misc/synth/inlining/test6/test.f new file mode 100644 index 000000000..5fe85ff15 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test6/test.f @@ -0,0 +1,3 @@ +test6/test.cpp +test6/tb.cpp +test6/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/inlining/test6/test.h b/src/systemc/tests/systemc/misc/synth/inlining/test6/test.h new file mode 100644 index 000000000..8df47ed52 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/inlining/test6/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void modify (sc_signal<int>&, int&); + void noModify (int); + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/common.h b/src/systemc/tests/systemc/misc/synth/prime_flag/common.h new file mode 100644 index 000000000..c868bf6a6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_bv<16> bool_vector; +typedef sc_signal<bool_vector> signal_bool_vector; + +#endif diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/display.cpp b/src/systemc/tests/systemc/misc/synth/prime_flag/display.cpp new file mode 100644 index 000000000..e4f8ae94e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/display.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /*****************************************/ + /* Implementation Filename: display.cc */ + /*****************************************/ + +#include "display.h" + +void displayp::entry() +{ + bool_vector last_prime; + + while (true) { + + last_prime = prime.read(); + wait(); + + do { wait(); } while (prime_ready == 0); + cout << prime.read().to_uint() << endl; + + if (prime.read().to_uint() > 40) { + sc_stop(); + } + } +} diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/display.h b/src/systemc/tests/systemc/misc/synth/prime_flag/display.h new file mode 100644 index 000000000..44b7a90dd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/display.h @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + display.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /***************************************/ + /* Interface Filename: display.h */ + /***************************************/ + +#include "common.h" + +SC_MODULE( displayp ) +{ + SC_HAS_PROCESS( displayp ); + + sc_in_clk clk; + + // Inputs + const sc_signal<bool>& prime_ready; + const signal_bool_vector& prime; + + // Constructor + displayp (sc_module_name NAME, + sc_clock& TICK, + const sc_signal<bool>& PRIME_READY, + const signal_bool_vector& PRIME ) + + : + prime_ready (PRIME_READY), + prime (PRIME) + + { + clk (TICK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/golden/prime_flag.log b/src/systemc/tests/systemc/misc/synth/prime_flag/golden/prime_flag.log new file mode 100644 index 000000000..147abf5fd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/golden/prime_flag.log @@ -0,0 +1,18 @@ +SystemC Simulation +1 +Terminating process T1.entry +2 +3 +5 +7 +11 +13 +17 +19 +23 +29 +31 +37 +41 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/main.cpp b/src/systemc/tests/systemc/misc/synth/prime_flag/main.cpp new file mode 100644 index 000000000..cf63b5e05 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/main.cpp @@ -0,0 +1,67 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /***************************************/ + /* Main Filename: main.cc */ + /***************************************/ + +#include "reset.h" +#include "display.h" +#include "prime_numgen.h" + +int sc_main(int ac, char *av[]) +{ + +// Signal Instantiation + sc_signal<bool> reset ("reset"); + sc_signal<bool> prime_ready ("prime_ready"); + signal_bool_vector prime ("prime"); + +// Clock Instantiation + sc_clock clk ("CLK", 6, SC_NS, 0.5, 10, SC_NS, false); // 167 Mhz + +// Process Instantiation + prime_numgen D1 ("D1", clk, reset, prime_ready, prime); + + resetp T1 ("T1", clk, reset); + + displayp T2 ("T2", clk, prime_ready, prime); + +// Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/prime_flag.f b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_flag.f new file mode 100644 index 000000000..baf7285c1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_flag.f @@ -0,0 +1,4 @@ +prime_flag/reset.cpp +prime_flag/display.cpp +prime_flag/prime_numgen.cpp +prime_flag/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.cpp b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.cpp new file mode 100644 index 000000000..07c937abe --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.cpp @@ -0,0 +1,93 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + prime_numgen.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*** Prime Number Generator ***/ +/*** Implementation Filename: prime_numgen.cc ***/ +/******************************************************************************/ + +#include "prime_numgen.h" + +void prime_numgen::entry() +{ + + static unsigned int p2 = 1, + p3 = 0, + p5 = 0, + p7 = 0, + p11 = 0, + p13 = 0, + p17 = 0, + p19 = 0, + p23 = 0, + p29 = 0; + + // HANDSHAKING + prime_ready.write(0); + wait(); + + // COMPUTE LOOP + while (true) { + + // PRINT prime IF ALL OTHER VALUES ARE ZERO AND p2 IS NONZERO + if (p2 && !p3 && !p5 && !p7 && !p11 && !p13 && !p17 && !p19 && !p23 && !p29) + { + prime_ready.write(1); + prime.write(p2); // Printing prime value p2 + wait(); + + prime_ready.write(0); + } + wait(); + + // DETERMINE NEW PRIME NUMBER + if (p7 && p13) { p7--, p13--, p17++; } + else if (p5 && p17) { p5--, p17--, p2++, p3++, p13++; } + else if (p3 && p17) { p3--, p17--, p19++; } + else if (p2 && p19) { p2--, p19--, p23++; } + else if (p3 && p11) { p3--, p11--, p29++; } + else if (p29) { p29--, p7++, p11++; } + else if (p23) { p23--, p5++, p19++; } + else if (p19) { p19--, p7++, p11++; } + else if (p17) { p17 = 0; } + else if (p13) { p13--, p11++; } + else if (p11) { p11--, p13++; } + else if (p2 && p7) { p2--, p7--, p3++, p5++; } + else if (p2) { p2--, p3++, p5++; } + else { p5++, p11++; } + } +} diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.h b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.h new file mode 100644 index 000000000..f01ea57bf --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/prime_numgen.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + prime_numgen.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /***************************************/ + /* Interface Filename: prime_numgen.h */ + /***************************************/ + +#include "common.h" + +SC_MODULE( prime_numgen ) +{ + SC_HAS_PROCESS( prime_numgen ); + + sc_in_clk clk; + + // Inputs + const sc_signal<bool>& reset; + // Outputs + sc_signal<bool>& prime_ready; + signal_bool_vector& prime; + + // Constructor + prime_numgen (sc_module_name NAME, + sc_clock& TICK, + const sc_signal<bool>& RESET, + sc_signal<bool>& PRIME_READY, + signal_bool_vector& PRIME ) + + : + reset (RESET), + prime_ready (PRIME_READY), + prime (PRIME) + + { + clk (TICK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,false); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/reset.cpp b/src/systemc/tests/systemc/misc/synth/prime_flag/reset.cpp new file mode 100644 index 000000000..43e3ce8d8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/reset.cpp @@ -0,0 +1,53 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + reset.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /***************************************/ + /* Implementation Filename: reset.cc */ + /***************************************/ + +#include "reset.h" + +void resetp::entry() +{ + reset.write(0); + wait(3); + + reset.write(1); + wait(); + + halt(); +} diff --git a/src/systemc/tests/systemc/misc/synth/prime_flag/reset.h b/src/systemc/tests/systemc/misc/synth/prime_flag/reset.h new file mode 100644 index 000000000..c918604e5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/prime_flag/reset.h @@ -0,0 +1,67 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + reset.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /***************************************/ + /* Interface Filename: reset.h */ + /***************************************/ + +#include "common.h" + +SC_MODULE( resetp ) +{ + SC_HAS_PROCESS( resetp ); + + sc_in_clk clk; + + // Outputs + sc_signal<bool>& reset; + + // Constructor + resetp (sc_module_name NAME, + sc_clock& TICK, + sc_signal<bool>& RESET ) + + : + reset (RESET) + + { + clk (TICK); + SC_CTHREAD( entry, clk.neg() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/reduce/golden/reduce.log b/src/systemc/tests/systemc/misc/synth/reduce/golden/reduce.log new file mode 100644 index 000000000..a17537cd2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/reduce/golden/reduce.log @@ -0,0 +1,6 @@ +SystemC Simulation +1690 +1690 +1625 +2665 +1365 diff --git a/src/systemc/tests/systemc/misc/synth/reduce/reduce.cpp b/src/systemc/tests/systemc/misc/synth/reduce/reduce.cpp new file mode 100644 index 000000000..073aa86b5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/reduce/reduce.cpp @@ -0,0 +1,77 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + reduce.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +unsigned +reduce_imp(const sc_bv<8>& x) +{ + unsigned r = 0; + r = (r << 1) | x.and_reduce(); + r = (r << 1) | x.nand_reduce(); + r = (r << 1) | x.or_reduce(); + r = (r << 1) | x.nor_reduce(); + r = (r << 1) | x.xor_reduce(); + r = (r << 1) | x.xnor_reduce(); + + r = (r << 1) | and_reduce(x); + r = (r << 1) | nand_reduce(x); + r = (r << 1) | or_reduce(x); + r = (r << 1) | nor_reduce(x); + r = (r << 1) | xor_reduce(x); + r = (r << 1) | xnor_reduce(x); + + return r; +} + +int +sc_main(int argc, char* argv[]) +{ + sc_bv<8> u; + u = "10011011"; + cout << reduce_imp(u) << endl; + u = "11101001"; + cout << reduce_imp(u) << endl; + u = "01101001"; + cout << reduce_imp(u) << endl; + u = "11111111"; + cout << reduce_imp(u) << endl; + u = "00000000"; + cout << reduce_imp(u) << endl; + + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/scflow/t/golden/t.log b/src/systemc/tests/systemc/misc/synth/scflow/t/golden/t.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/scflow/t/golden/t.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/scflow/t/main.cpp b/src/systemc/tests/systemc/misc/synth/scflow/t/main.cpp new file mode 100644 index 000000000..d24ab5b6b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/scflow/t/main.cpp @@ -0,0 +1,43 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +int sc_main(int ac, char* av[]) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/scflow/t/t.cpp b/src/systemc/tests/systemc/misc/synth/scflow/t/t.cpp new file mode 100644 index 000000000..44eaf3c52 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/scflow/t/t.cpp @@ -0,0 +1,53 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + t.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "test.h" + +void t::entry() +{ + wait(); + wait (); + do { wait(); } while (cont1 == 0); + wait (); + o1 = 4; + wait (); + wait (); + wait (); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/scflow/t/t.f b/src/systemc/tests/systemc/misc/synth/scflow/t/t.f new file mode 100644 index 000000000..37c5d2058 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/scflow/t/t.f @@ -0,0 +1,2 @@ +t/t.cpp +t/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/scflow/t/test.h b/src/systemc/tests/systemc/misc/synth/scflow/t/test.h new file mode 100644 index 000000000..638eff008 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/scflow/t/test.h @@ -0,0 +1,102 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/synth-1.0/gcd/gcd.cpp b/src/systemc/tests/systemc/misc/synth/synth-1.0/gcd/gcd.cpp new file mode 100644 index 000000000..370324974 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/synth-1.0/gcd/gcd.cpp @@ -0,0 +1,175 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + gcd.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +struct gcd_cc : public sc_module { + sc_in_clk clk; + sc_in<bool> reset; + sc_in<unsigned> a; + sc_in<unsigned> b; + sc_out<unsigned> c; + sc_out<bool> ready; + + void gcd_compute(); + + SC_HAS_PROCESS( gcd_cc ); + + gcd_cc( sc_module_name name ) + { + SC_CTHREAD( gcd_compute, clk.pos() ); + reset_signal_is(reset,true); + } +}; + +void +gcd_cc::gcd_compute() +{ + unsigned tmp_a = 0; + wait(); // Note that this wait() is required, otherwise, + // the reset is wrong! This is a problem with BC, + // not our frontend. + + while (true) { + unsigned tmp_b; + + c = tmp_a; + ready = true; + wait(); + + tmp_a = a; + tmp_b = b; + ready = false; + wait(); + + while (tmp_b != 0) { + + unsigned tmp_c = tmp_a; + tmp_a = tmp_b; + wait(); + + while (tmp_c >= tmp_b) { + tmp_c = tmp_c - tmp_b; + wait(); + } + + tmp_b = tmp_c; + wait(); + } + } +} + +static int numbers[] = { 49597, 41218, 20635, 40894, 16767, 17233, 36246, 28171, 60879, 49566, 10971, 24107, 30561, 49648, 50031, 12559, 23787, 35674, 43320, 37558, 840, 18689, 62466, 6308, 46271, 49801, 43433, 22683, 35494, 35259, 29020, 19555, 10941, 49656, 60450, 27709, 1353, 31160, 55880, 62232, 15190, 1315, 20803, 45751, 50963, 5298, 58311, 9215, 2378 }; +static unsigned numbers_index = 0; + +struct testbench : public sc_module { + sc_in_clk clk; + sc_inout<bool> reset; + sc_in<bool> ready; + sc_inout<unsigned> a; + sc_inout<unsigned> b; + sc_in<unsigned> c; + + void reset_gen(); + void stimu_gen(); + void display(); + + SC_HAS_PROCESS( testbench ); + + testbench( sc_module_name name ) + { + SC_CTHREAD( reset_gen, clk.pos() ); + SC_CTHREAD( stimu_gen, clk.pos() ); + SC_METHOD( display ); + sensitive << ready; + } +}; + +void +testbench::reset_gen() +{ + reset = 0; + wait(); + reset = 1; + wait(); + wait(); + reset = 0; + wait(); + /* die */ +} + +void +testbench::stimu_gen() +{ + while (true) { + do { wait(); } while (ready == 0); + a = (unsigned) numbers[numbers_index++ % (sizeof(numbers)/sizeof(numbers[0]))]; + b = (unsigned) numbers[(numbers_index*numbers_index) % (sizeof(numbers)/sizeof(numbers[0]))]; + numbers_index++; + } +} + +void +testbench::display() +{ + if (ready) { + cout << "reset = " << reset << " ready = " << ready + << " a = " << a << " b = " << b << " c = " << c << endl; + } +} + +int sc_main(int argc, char* argv[] ) +{ + sc_signal<unsigned> a("a"), b("b"), c("c"); + sc_clock clk("clk", 20, SC_NS); + sc_signal<bool> reset("reset"), ready("ready"); + + a = 0; + b = 0; + c = 0; + reset = false; + ready = false; + + gcd_cc gcd("gcd"); + gcd(clk, reset, a, b, c, ready); + + testbench tb("tb"); + tb(clk, reset, ready, a, b, c); + + sc_start(2000000, SC_NS); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/synth-1.0/gcd/golden/gcd.log b/src/systemc/tests/systemc/misc/synth/synth-1.0/gcd/golden/gcd.log new file mode 100644 index 000000000..77a93afc2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/synth-1.0/gcd/golden/gcd.log @@ -0,0 +1,1109 @@ +SystemC Simulation +reset = 1 ready = 1 a = 0 b = 0 c = 0 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 +reset = 0 ready = 1 a = 12559 b = 24107 c = 1 +reset = 0 ready = 1 a = 35674 b = 29020 c = 1 +reset = 0 ready = 1 a = 37558 b = 60879 c = 2 +reset = 0 ready = 1 a = 18689 b = 45751 c = 1 +reset = 0 ready = 1 a = 6308 b = 31160 c = 1 +reset = 0 ready = 1 a = 49801 b = 62232 c = 76 +reset = 0 ready = 1 a = 22683 b = 49597 c = 1 +reset = 0 ready = 1 a = 35259 b = 43320 c = 1 +reset = 0 ready = 1 a = 19555 b = 50963 c = 3 +reset = 0 ready = 1 a = 49656 b = 35259 c = 1 +reset = 0 ready = 1 a = 27709 b = 62466 c = 3 +reset = 0 ready = 1 a = 31160 b = 6308 c = 1 +reset = 0 ready = 1 a = 62232 b = 10941 c = 76 +reset = 0 ready = 1 a = 1315 b = 49597 c = 3 +reset = 0 ready = 1 a = 45751 b = 49801 c = 1 +reset = 0 ready = 1 a = 5298 b = 49566 c = 1 +reset = 0 ready = 1 a = 9215 b = 41218 c = 6 +reset = 0 ready = 1 a = 49597 b = 41218 c = 1 +reset = 0 ready = 1 a = 20635 b = 49566 c = 1 +reset = 0 ready = 1 a = 16767 b = 49801 c = 1 +reset = 0 ready = 1 a = 36246 b = 49597 c = 1 +reset = 0 ready = 1 a = 60879 b = 10941 c = 1 +reset = 0 ready = 1 a = 10971 b = 6308 c = 21 +reset = 0 ready = 1 a = 30561 b = 62466 c = 1 +reset = 0 ready = 1 a = 50031 b = 35259 c = 3 +reset = 0 ready = 1 a = 23787 b = 50963 c = 3 +reset = 0 ready = 1 a = 43320 b = 43320 c = 1 +reset = 0 ready = 1 a = 840 b = 49597 c = 43320 +reset = 0 ready = 1 a = 62466 b = 62232 c = 1 +reset = 0 ready = 1 a = 46271 b = 31160 c = 6 +reset = 0 ready = 1 a = 43433 b = 45751 c = 1 +reset = 0 ready = 1 a = 35494 b = 60879 c = 1 +reset = 0 ready = 1 a = 29020 b = 29020 c = 1 +reset = 0 ready = 1 a = 10941 b = 24107 c = 29020 +reset = 0 ready = 1 a = 60450 b = 49597 c = 1 +reset = 0 ready = 1 a = 1353 b = 58311 c = 1 +reset = 0 ready = 1 a = 55880 b = 20635 c = 33 +reset = 0 ready = 1 a = 15190 b = 12559 c = 5 +reset = 0 ready = 1 a = 20803 b = 1353 c = 1 +reset = 0 ready = 1 a = 50963 b = 23787 c = 1 +reset = 0 ready = 1 a = 58311 b = 16767 c = 1 +reset = 0 ready = 1 a = 2378 b = 49597 c = 9 +reset = 0 ready = 1 a = 41218 b = 16767 c = 1 +reset = 0 ready = 1 a = 40894 b = 23787 c = 1 +reset = 0 ready = 1 a = 17233 b = 1353 c = 1 +reset = 0 ready = 1 a = 28171 b = 12559 c = 1 +reset = 0 ready = 1 a = 49566 b = 20635 c = 1 +reset = 0 ready = 1 a = 24107 b = 58311 c = 1 +reset = 0 ready = 1 a = 49648 b = 49597 c = 1 diff --git a/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_blast/golden/pr-207_blast.log b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_blast/golden/pr-207_blast.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_blast/golden/pr-207_blast.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_blast/pr-207_blast.cpp b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_blast/pr-207_blast.cpp new file mode 100644 index 000000000..acf33e58b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_blast/pr-207_blast.cpp @@ -0,0 +1,129 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + pr-207_blast.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + + +struct my_pair { + char x; + char y; +}; + +typedef sc_signal<bool> sig_bool; +typedef sc_signal<char> sig_char; +typedef sc_signal<unsigned char> sig_uchar; + +SC_MODULE( pr207 ) +{ + SC_HAS_PROCESS( pr207 ); + + sc_in_clk clk; + + pr207(sc_module_name NAME, + sc_clock& CLK, + + const sig_bool& RESET, + const sig_bool& START, + const sig_char& C1, + const sig_char& C2, + const sig_uchar& IDX1, + const sig_uchar& IDX2, + sig_char& D1, + sig_char& D2, + sig_bool& READY + ) + : + reset(RESET), + start(START), + c1(C1), + c2(C2), + idx1(IDX1), + idx2(IDX2), + d1(D1), + d2(D2), + ready(READY) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + } + void entry(); + + const sig_bool& reset; + const sig_bool& start; + const sig_char& c1; + const sig_char& c2; + const sig_uchar& idx1; + const sig_uchar& idx2; + sig_char& d1; + sig_char& d2; + sig_bool& ready; + +}; + +void +pr207::entry() +{ + my_pair pair_array[10]; + + ready = true; + d1 = 0; + d2 = 0; + wait(); + while (true) { + do { wait(); } while (start == 0); + ready = false; + wait(); + pair_array[idx1.read()].x = c1; + pair_array[idx1.read()].y = c2; + wait(); + pair_array[idx2.read()] = pair_array[idx1.read()]; + wait(); + char d1_tmp = pair_array[idx2.read()].y; + wait(); + char d2_tmp = pair_array[idx2.read()].x; + wait(); + d1 = d1_tmp; + d2 = d2_tmp; + ready = true; + } +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_mem/golden/pr-207_mem.log b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_mem/golden/pr-207_mem.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_mem/golden/pr-207_mem.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_mem/pr-207_mem.cpp b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_mem/pr-207_mem.cpp new file mode 100644 index 000000000..ea4967f8f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_mem/pr-207_mem.cpp @@ -0,0 +1,129 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + pr-207_mem.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +struct my_pair { + char x; + char y; +}; + +typedef sc_signal<bool> sig_bool; +typedef sc_signal<char> sig_char; +typedef sc_signal<unsigned char> sig_uchar; + +SC_MODULE( pr207 ) +{ + SC_HAS_PROCESS( pr207 ); + + sc_in_clk clk; + + pr207(sc_module_name NAME, + sc_clock& CLK, + + const sig_bool& RESET, + const sig_bool& START, + const sig_char& C1, + const sig_char& C2, + const sig_uchar& IDX1, + const sig_uchar& IDX2, + sig_char& D1, + sig_char& D2, + sig_bool& READY + ) + : + reset(RESET), + start(START), + c1(C1), + c2(C2), + idx1(IDX1), + idx2(IDX2), + d1(D1), + d2(D2), + ready(READY) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + } + void entry(); + + const sig_bool& reset; + const sig_bool& start; + const sig_char& c1; + const sig_char& c2; + const sig_uchar& idx1; + const sig_uchar& idx2; + sig_char& d1; + sig_char& d2; + sig_bool& ready; + +}; + +void +pr207::entry() +{ + my_pair pair_array[10]; + + ready = true; + d1 = 0; + d2 = 0; + wait(); + while (true) { + do { wait(); } while (start == 0); + ready = false; + wait(); + pair_array[idx1.read()].x = c1; + pair_array[idx1.read()].y = c2; + wait(); + pair_array[idx2.read()] = pair_array[idx1.read()]; + wait(); + char d1_tmp = pair_array[idx2.read()].y; + wait(); + char d2_tmp = pair_array[idx2.read()].x; + wait(); + d1 = d1_tmp; + d2 = d2_tmp; + ready = true; + } +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} + diff --git a/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_rf/golden/pr-207_rf.log b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_rf/golden/pr-207_rf.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_rf/golden/pr-207_rf.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_rf/pr-207_rf.cpp b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_rf/pr-207_rf.cpp new file mode 100644 index 000000000..37b62a95b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/synth_gnats/pr-207/pr-207_rf/pr-207_rf.cpp @@ -0,0 +1,129 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + pr-207_rf.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +struct my_pair { + char x; + char y; +}; + +typedef sc_signal<bool> sig_bool; +typedef sc_signal<char> sig_char; +typedef sc_signal<unsigned char> sig_uchar; + +SC_MODULE( pr207 ) +{ + SC_HAS_PROCESS( pr207 ); + + sc_in_clk clk; + + pr207(sc_module_name NAME, + sc_clock& CLK, + + const sig_bool& RESET, + const sig_bool& START, + const sig_char& C1, + const sig_char& C2, + const sig_uchar& IDX1, + const sig_uchar& IDX2, + sig_char& D1, + sig_char& D2, + sig_bool& READY + ) + : + reset(RESET), + start(START), + c1(C1), + c2(C2), + idx1(IDX1), + idx2(IDX2), + d1(D1), + d2(D2), + ready(READY) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset,true); + } + void entry(); + + const sig_bool& reset; + const sig_bool& start; + const sig_char& c1; + const sig_char& c2; + const sig_uchar& idx1; + const sig_uchar& idx2; + sig_char& d1; + sig_char& d2; + sig_bool& ready; + +}; + +void +pr207::entry() +{ + my_pair pair_array[10]; + + ready = true; + d1 = 0; + d2 = 0; + wait(); + while (true) { + do { wait(); } while (start == 0); + ready = false; + wait(); + pair_array[idx1.read()].x = c1; + pair_array[idx1.read()].y = c2; + wait(); + pair_array[idx2.read()] = pair_array[idx1.read()]; + wait(); + char d1_tmp = pair_array[idx2.read()].y; + wait(); + char d2_tmp = pair_array[idx2.read()].x; + wait(); + d1 = d1_tmp; + d2 = d2_tmp; + ready = true; + } +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/golden/test1.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/golden/test1.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/golden/test1.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test.h new file mode 100644 index 000000000..4a591ce30 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test1.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test1.cpp new file mode 100644 index 000000000..4ff400163 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test1/test1.cpp @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test1.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + wait (); + + do { wait(); } while (cont1 == 0); + + + +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/golden/test2.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/golden/test2.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/golden/test2.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test.h new file mode 100644 index 000000000..4a591ce30 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test2.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test2.cpp new file mode 100644 index 000000000..e128e0372 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test2/test2.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test2.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + while (1) { + do { wait(); } while (cont1 == 0); + if (i2 == 1) + break; + /* error: wait needs to be inserted between do { wait(); } while + and break */ + } + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/golden/test3.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/golden/test3.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/golden/test3.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test.h new file mode 100644 index 000000000..5bd25d99e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test3.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test3.cpp new file mode 100644 index 000000000..411e2f4e7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test3/test3.cpp @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test3.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + while (1) { + if (i2 == 1) + continue; + /* error: do { wait(); } while transformation does not allow continue stmt + before it if no wait follows the do { wait(); } while */ + do { wait(); } while (cont1 == 0); + if (i2 == 1) + break; + } + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/golden/test4.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/golden/test4.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/golden/test4.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test.h new file mode 100644 index 000000000..5bd25d99e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test4.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test4.cpp new file mode 100644 index 000000000..d8c42acd3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test4/test4.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test4.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + if (i1 == 1) { + while (i1 == 1) { + do { wait(); } while (cont1 == 1); + } + } else { + wait(); + } + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/golden/test5.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/golden/test5.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/golden/test5.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test.h new file mode 100644 index 000000000..5bd25d99e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk (CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test5.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test5.cpp new file mode 100644 index 000000000..74a0f56e2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test5/test5.cpp @@ -0,0 +1,179 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test5.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void t::entry() +{ + wait(); + /* error: control nesting too deep - error reported in siu_do { wait(); } while .c */ + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) +#if !defined( _MSC_VER ) + // running into limitations of VC6 here + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) + if (i1 == 1) +#endif + wait(); + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/golden/test6.log b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/golden/test6.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/golden/test6.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test1.h b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test1.h new file mode 100644 index 000000000..570465d8e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test1.h @@ -0,0 +1,105 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test1.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( t ) +{ + SC_HAS_PROCESS( t ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + t ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); + void a(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test6.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test6.cpp new file mode 100644 index 000000000..3f1f002d4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/misc/test6/test6.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test6.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test1.h" + +void t::a() +{ + do { wait(); } while (cont1 == 1); + +} + +void t::entry() +{ + a(); + wait(); +} + +int sc_main(int argc, char* argv[] ) +{ + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test01/define.h new file mode 100644 index 000000000..9b4c36e61 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/define.h @@ -0,0 +1,54 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(5*CLOCK_PERIOD) +#define single_cycle wait() +#define set_value(var,val) wait(EVENT_TIME); var = val; wait(CLOCK_PERIOD - EVENT_TIME) +#define test_value(actual, expected) \ + wait (TEST_TIME); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait (CLOCK_PERIOD - TEST_TIME) +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test01/golden/test.log new file mode 100644 index 000000000..d75ef208f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/golden/test.log @@ -0,0 +1,4 @@ +SystemC Simulation +Begin Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test01/main.cpp new file mode 100644 index 000000000..b754b436b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/main.cpp @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.cpp new file mode 100644 index 000000000..7c819fbf9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + reset_sig = 1; + cont1 = 0; + single_cycle; + single_cycle; + reset_sig = 0; + + long_wait; + + set_value(cont1,1); + single_cycle; + test_value(o1.read(),4); + long_wait; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.cpp new file mode 100644 index 000000000..ca94c1583 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + wait(); + wait (); + do { wait(); } while (cont1 == 1); + wait (); + o1 = 4; + wait (); + wait (); + wait (); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.f new file mode 100644 index 000000000..18d0009a8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.f @@ -0,0 +1,3 @@ +test01/test.cpp +test01/tb.cpp +test01/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.h new file mode 100644 index 000000000..56820dca5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test01/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test02/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test02/golden/test.log new file mode 100644 index 000000000..ae1be6e37 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/golden/test.log @@ -0,0 +1,30 @@ +SystemC Simulation +Begin Simulation +[Cycle No: 0] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 1] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 2] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 3] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 4] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 5] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 6] i1 = 5 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 7] i1 = 5 o1 = 0 o2 = 0 cont1 = 1 +[Cycle No: 8] i1 = 5 o1 = 0 o2 = 0 cont1 = 1 +[Cycle No: 9] i1 = 5 o1 = 0 o2 = 0 cont1 = 1 +[Cycle No: 10] i1 = 5 o1 = 2 o2 = 0 cont1 = 1 +[Cycle No: 11] i1 = 5 o1 = 2 o2 = 3 cont1 = 1 +[Cycle No: 12] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 13] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 14] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 15] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +Mismatch. Expected: 2. Actual: 0 +[Cycle No: 16] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +Mismatch. Expected: 3. Actual: 0 +[Cycle No: 17] i1 = 0 o1 = 2 o2 = 0 cont1 = 0 +[Cycle No: 18] i1 = 0 o1 = 2 o2 = 3 cont1 = 0 +[Cycle No: 19] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 20] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 21] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +[Cycle No: 22] i1 = 0 o1 = 0 o2 = 0 cont1 = 0 +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test02/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.cpp new file mode 100644 index 000000000..97bb148ec --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + reset_sig = 1; + cont1 = 0; + i1 = 0; + i2 = 0; + single_cycle; + reset_sig = 0; + + i1 = 5; + single_cycle; + single_cycle; + single_cycle; + single_cycle; + single_cycle; + single_cycle; + + set_value(cont1,1); + single_cycle; + single_cycle; + + test_value(o1,2); + test_value(o2,3); + + // 2nd iteration. Test 'else' clause. + i1 = 0; + i2 = 0; + cont1 = 0; + single_cycle; + single_cycle; + single_cycle; + single_cycle; + + test_value(o1,2); + test_value(o2,3); + + long_wait; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.cpp new file mode 100644 index 000000000..bbd1a5933 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + while (true) { + o1 = 0; o2 = 0; + wait(); + wait(); + wait (); + if (i1 == 5) { + do { wait(); } while (cont1 == 0); + wait (); + } else { + wait (); + } + wait (); + o1 = 2; + wait (); + o2 = 3; + wait (); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.f new file mode 100644 index 000000000..030dc67dd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.f @@ -0,0 +1,4 @@ +test02/test.cpp +test02/tb.cpp +test02/monitor.cpp +test02/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test02/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test03/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test03/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test03/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.cpp new file mode 100644 index 000000000..92b753daa --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.cpp @@ -0,0 +1,65 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + while (true) { + o1 = 0; + do { wait(); } while (cont1 == 1); + wait(); + wait (); + if (i1 == 5) { + if (i2 == 5) { + do { wait(); } while (cont2 == 1); + wait (); + o1 = 1; + } else { + wait(); + o1 = 2; + } + } else { + wait(); + o1 = 3; + } + wait (); + wait (); + wait (); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.f new file mode 100644 index 000000000..44bca3f91 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.f @@ -0,0 +1,4 @@ +test03/test.cpp +test03/tb.cpp +test03/monitor.cpp +test03/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test03/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test04/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test04/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test04/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.cpp new file mode 100644 index 000000000..b10e4c6a7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 1); + wait(); + o1 = 0; + wait (); + if (i1 == 5) { + do { wait(); } while (cont2 == 1); + } else { + wait (); + } + o1 = 6; + wait (); + wait (); + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.f new file mode 100644 index 000000000..2a530a6e3 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.f @@ -0,0 +1,4 @@ +test04/test.cpp +test04/tb.cpp +test04/monitor.cpp +test04/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test04/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test05/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test05/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test05/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.cpp new file mode 100644 index 000000000..b6a5cc9b0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 1); + wait(); + o1 = 0; + o2 = 0; + o3 = 0; + o4 = 0; + o5 = 0; + wait (); + if (i1 == 5) { + if (i2 == 5) { + if (i3 == 5) { + do { wait(); } while (cont2 == 1); + } else { + wait (); + } + o1 = 9; + o2 = 10; + wait(); + } else { + wait (); + } + o3 = 5; + o4 = 10; + wait(); + wait(); + } else { + wait (); + } + o5 = 6; + wait (); + wait (); + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.f new file mode 100644 index 000000000..a2d56602a --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.f @@ -0,0 +1,4 @@ +test05/test.cpp +test05/tb.cpp +test05/monitor.cpp +test05/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test05/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test06/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test06/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test06/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.cpp new file mode 100644 index 000000000..8e0b65f6c --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 50.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 0); + wait(); + o1 = 0; + o2 = 0; + o3 = 0; + o4 = 0; + o5 = 0; + wait (); + if (i1 == 5) { + if (i2 == 5) { + if (i3 == 5) { + do { wait(); } while (cont2 == 0); + } else { + wait (); + } + o1 = 9; + o2 = 10; + } else { + wait (); + } + o3 = 5; + o4 = 10; + wait(); + wait(); + } else { + wait (); + } + o5 = 6; + wait (); + wait (); + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.f new file mode 100644 index 000000000..687c574e6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.f @@ -0,0 +1,4 @@ +test06/test.cpp +test06/tb.cpp +test06/monitor.cpp +test06/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test06/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test07/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test07/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test07/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.cpp new file mode 100644 index 000000000..5c3f91119 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.cpp @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 51.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 0); + wait(); + o1 = 0; + o2 = 0; + o3 = 0; + o4 = 0; + o5 = 0; + wait (); + if (i1 == 25) { + if (i2 == 15) { + if (i3 == 5) { + wait (); + } else { + if (i4 == 1) { + wait (); + o5 = 2; + } else { + do { wait(); } while (cont2 != 8); + } + } + o1 = 9; + o2 = 10; + } else { + wait(); + wait(); + } + o3 = 5; + o4 = 20; + wait(); + wait(); + } else { + wait(); + } + o5 = 6; + wait (); + wait (); + wait (); + + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.f new file mode 100644 index 000000000..06081cb35 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.f @@ -0,0 +1,4 @@ +test07/test.cpp +test07/tb.cpp +test07/monitor.cpp +test07/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test07/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test08/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test08/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test08/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.cpp new file mode 100644 index 000000000..d59304852 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.cpp @@ -0,0 +1,87 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 52.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 == 0); + wait(); + o1 = 0; + o2 = 0; + o3 = 0; + o4 = 0; + o5 = 0; + wait (); + if (i1 == 25) { + if (i2 == 15) { + if (i3 == 5) { + wait (); + } else { + if (i4 == 1) { + wait (); + o5 = 2; + } else { + do { wait(); } while (cont2 != 8); + wait (); + } + } + o1 = 9; + o2 = 10; + } else { + wait(); + wait(); + } + o3 = 5; + o4 = 20; + wait(); + wait(); + } else { + wait(); + } + o5 = 6; + wait (); + wait (); + wait (); + + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.f new file mode 100644 index 000000000..97efb0322 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.f @@ -0,0 +1,4 @@ +test08/test.cpp +test08/tb.cpp +test08/monitor.cpp +test08/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test08/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test09/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.cpp new file mode 100644 index 000000000..2a4edae69 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 53.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + + wait(); + while (i1 < 4) { + o1 = 0; + wait (); + do { wait(); } while (cont2 != 1); + o1 = 1; + wait (); + } + wait(); + + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.f new file mode 100644 index 000000000..1dd8094ef --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.f @@ -0,0 +1,4 @@ +test09/test.cpp +test09/tb.cpp +test09/monitor.cpp +test09/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test09/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test10/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test10/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test10/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.cpp new file mode 100644 index 000000000..d6cdb4529 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.cpp @@ -0,0 +1,57 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 54.sc */ +void test::entry() +{ + while (true) { + + wait(); + o1 = 2; + do { wait(); } while (cont1 != 1); + wait(); + while (1) { + wait (); + o1 = i2 + 1; + do { wait(); } while (cont1 != 1); + } + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.f new file mode 100644 index 000000000..328dc35a0 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.f @@ -0,0 +1,4 @@ +test10/test.cpp +test10/tb.cpp +test10/monitor.cpp +test10/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test10/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test11/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test11/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test11/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.cpp new file mode 100644 index 000000000..4eca67444 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.cpp @@ -0,0 +1,64 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 55.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait(); + if (i2 == 1) + o1 = 9; + else + o1 = 10; + wait (); + switch (i3) { + case 1: o2 = 8; do { wait(); } while (cont2 != 1); break; + case 2: o2 = 9; wait(); break; + case 3: o2 = 10; wait(); break; + default: o2 = 11; wait(); break; + } + wait(); + o1 = 5; + wait(); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.f new file mode 100644 index 000000000..715ba8512 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.f @@ -0,0 +1,4 @@ +test11/test.cpp +test11/tb.cpp +test11/monitor.cpp +test11/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test11/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test12/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test12/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test12/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.cpp new file mode 100644 index 000000000..c517882da --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.cpp @@ -0,0 +1,65 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 56.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait(); + o1 = 9; + switch (i3) { + case 1: o2 = 8; + if (i2 > 4) + do { wait(); } while (cont1 != 1); + else + wait(); + break; + case 2: o2 = 9; wait(); break; + case 3: o2 = 10; wait(); break; + default: o2 = 11; wait(); break; + } + wait(); + o1 = 5; + wait(); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.f new file mode 100644 index 000000000..e193e228f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.f @@ -0,0 +1,4 @@ +test12/test.cpp +test12/tb.cpp +test12/monitor.cpp +test12/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test12/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test13/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test13/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test13/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.cpp new file mode 100644 index 000000000..26c93fdcf --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.cpp @@ -0,0 +1,90 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 57.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait (); + o1 = 9; + + switch (i5) { + case 1: + if (i2 > 4) { + o2 = 80; + do { wait(); } while (cont2 != 1); + } else { + o2 = 81; + wait(); + } + break; + case 2: + o2 = 9; + if (i4 == 5) { + wait(); wait(); break; + } + else + wait(); + break; + case 3: + o2 = 10; + wait(); + while (i3 < 5) { + wait(); + o3 = i4 + 1; + if (i4 > 7) break; + wait(); + } + wait (); + break; + default: o2 = 11; wait(); break; + } + if (i3 == 3) { + o1 = 4; + wait(); + } else { + o1 = 5; + wait(); + } + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.f new file mode 100644 index 000000000..b12d0f35b --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.f @@ -0,0 +1,4 @@ +test13/test.cpp +test13/tb.cpp +test13/monitor.cpp +test13/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test13/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test14/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test14/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test14/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.cpp new file mode 100644 index 000000000..5c82a908d --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.cpp @@ -0,0 +1,76 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 58.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait(); + o1 = 0; + wait (); + if (i1 > 5) { + if (i2 > 3) { + do { wait(); } while (cont2 != 1); + o1 = 9; + if (i2 > 6) + o2 = 6; + else + o2 = 7; + wait (); + if (i2 > 9) + o2 = 8; + else + o2 = 9; + } else { + o2 = 10; + wait(); + } + } else { + o2 = 11; + wait(); + } + wait (); + o1 = 1; + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.f new file mode 100644 index 000000000..5db160f14 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.f @@ -0,0 +1,4 @@ +test14/test.cpp +test14/tb.cpp +test14/monitor.cpp +test14/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test14/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test15/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test15/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test15/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.cpp new file mode 100644 index 000000000..faf5894a1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.cpp @@ -0,0 +1,70 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 59.sc */ +void test::entry() +{ + while (true) { + + do { wait(); } while (cont1 != 1); + wait(); + o1 = 5; + do { wait(); } while (cont2 != 1); + o1 = 1; + do { wait(); } while (cont1 != 1); + o1 = 2; + wait (); + o1 = 3; + if (i2 == 5) { + do { wait(); } while (cont2 != 1); + do { wait(); } while (cont1 != 1); + o1 = 4; + wait (); + wait (); + do { wait(); } while (cont2 != 1); + do { wait(); } while (cont1 != 1); + } else { + wait(); + } + o1 = 0; + wait (); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.f new file mode 100644 index 000000000..418eb1dff --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.f @@ -0,0 +1,4 @@ +test15/test.cpp +test15/tb.cpp +test15/monitor.cpp +test15/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test15/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test16/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test16/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test16/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.cpp new file mode 100644 index 000000000..c85de0a63 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.cpp @@ -0,0 +1,61 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 62.sc */ +void test::entry() +{ + while (true) { + + wait(); + do { wait(); } while (cont1 != 1); + wait(); + o2 = 8; + wait(); + while (i2 < 6) { + wait(); + o1 = 7; + do { wait(); } while (cont2 != 1); + } + wait(); + o2 = 0; + wait(); + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.f new file mode 100644 index 000000000..6593d828f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.f @@ -0,0 +1,4 @@ +test16/test.cpp +test16/tb.cpp +test16/monitor.cpp +test16/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test16/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/define.h b/src/systemc/tests/systemc/misc/synth/wait_until/test17/define.h new file mode 100644 index 000000000..d671993cd --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/define.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + define.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#define CLOCK_PERIOD 100 +#define TB_CLOCK_PERIOD 50 +#define DUTY_CYCLE 0.5 +#define EVENT_TIME 50 +#define TEST_TIME 50 + +#define long_wait wait(10) +#define single_cycle wait(2) +#define set_value(var,val) wait(); var = val; wait() +#define test_value(actual, expected) \ + wait (); if (expected != actual) \ + cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; \ + wait () +#define test_value_now(actual, expected) \ + if (expected != actual) cout << "Mismatch. Expected: " << expected \ + << ". Actual: " << actual << endl; + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/golden/test.log b/src/systemc/tests/systemc/misc/synth/wait_until/test17/golden/test.log new file mode 100644 index 000000000..510bd7f39 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/golden/test.log @@ -0,0 +1,5 @@ +SystemC Simulation +Begin Simulation +End Simulation + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/main.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test17/main.cpp new file mode 100644 index 000000000..f63c6fde6 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/main.cpp @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// Main routine + +#include "test.h" +#include "tb.h" +#include "monitor.h" +#include "define.h" + +int sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock tb_clock("TBClock", TB_CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 0, SC_NS); + sc_clock mon_clock("MonClock", CLOCK_PERIOD, SC_NS, DUTY_CYCLE, 75, SC_NS); + + sc_signal<bool> reset_sig; + + sc_signal<int> i1; + sc_signal<int> i2; + sc_signal<int> i3; + sc_signal<int> i4; + sc_signal<int> i5; + + sc_signal<bool> cont1; + sc_signal<bool> cont2; + sc_signal<bool> cont3; + + sc_signal<int> o1; + sc_signal<int> o2; + sc_signal<int> o3; + sc_signal<int> o4; + sc_signal<int> o5; + + test TEST ("TEST", clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + tb TB ("TB", tb_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + monitor MONITOR ("MONITOR", mon_clock, reset_sig, i1, i2, i3, i4, i5, + cont1, cont2, cont3, o1, o2, o3, o4, o5); + + // Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.cpp new file mode 100644 index 000000000..0a1f6643e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.cpp @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int cycleNo = 0; + + while (true) { + cout << "[Cycle No: " << cycleNo << "]" << + " i1 = " << i1 << + " o1 = " << o1 << + " o2 = " << o2 << + " cont1 = " << cont1 << + endl; + cycleNo++; + wait(); + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.h b/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.h new file mode 100644 index 000000000..d8f80b16e --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/monitor.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for monitor process + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + monitor ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.cpp new file mode 100644 index 000000000..6dc93138f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "tb.h" +#include "define.h" + +void tb::entry() +{ + cout << "Begin Simulation" << endl; + + + cout << "End Simulation" << endl; + + sc_stop(); + +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.h b/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.h new file mode 100644 index 000000000..1fecb570f --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/tb.h @@ -0,0 +1,103 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test bench + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( tb ) +{ + SC_HAS_PROCESS( tb ); + + sc_in_clk clk; + + // Output Reset Port + sc_signal<bool>& reset_sig; + + // Output Data Ports + sc_signal<int>& i1; + sc_signal<int>& i2; + sc_signal<int>& i3; + sc_signal<int>& i4; + sc_signal<int>& i5; + + // Output Control Ports + sc_signal<bool>& cont1; + sc_signal<bool>& cont2; + sc_signal<bool>& cont3; + + // Input Data Ports + const sc_signal<int>& o1; + const sc_signal<int>& o2; + const sc_signal<int>& o3; + const sc_signal<int>& o4; + const sc_signal<int>& o5; + + // Constructor + tb ( + sc_module_name NAME, + sc_clock& CLK, + + sc_signal<bool>& RESET_SIG, + + sc_signal<int>& I1, + sc_signal<int>& I2, + sc_signal<int>& I3, + sc_signal<int>& I4, + sc_signal<int>& I5, + + sc_signal<bool>& CONT1, + sc_signal<bool>& CONT2, + sc_signal<bool>& CONT3, + + const sc_signal<int>& O1, + const sc_signal<int>& O2, + const sc_signal<int>& O3, + const sc_signal<int>& O4, + const sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.cpp b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.cpp new file mode 100644 index 000000000..ec4680efb --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "test.h" + +/* From Test Case 61.sc */ +void test::entry() +{ + while (true) { + + wait(); + o1 = 2; + do { wait(); } while (cont1 != 1); + wait(); + if (i3 == 4) { + wait(); + while (1) { + wait (); + o1 = i2 + 1; + do { wait(); } while (cont2 != 2); + } + } else { + wait(); + } + + } +} + diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.f b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.f new file mode 100644 index 000000000..b2695ac54 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.f @@ -0,0 +1,4 @@ +test17/test.cpp +test17/tb.cpp +test17/monitor.cpp +test17/main.cpp diff --git a/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.h b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.h new file mode 100644 index 000000000..ccf974819 --- /dev/null +++ b/src/systemc/tests/systemc/misc/synth/wait_until/test17/test.h @@ -0,0 +1,104 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Common interface file for test cases + Author: PRP + */ + +#include "systemc.h" + +SC_MODULE( test ) +{ + SC_HAS_PROCESS( test ); + + sc_in_clk clk; + + // Input Reset Port + const sc_signal<bool>& reset_sig; + + // Input Data Ports + const sc_signal<int>& i1; + const sc_signal<int>& i2; + const sc_signal<int>& i3; + const sc_signal<int>& i4; + const sc_signal<int>& i5; + + // Input Control Ports + const sc_signal<bool>& cont1; + const sc_signal<bool>& cont2; + const sc_signal<bool>& cont3; + + // Output Data Ports + sc_signal<int>& o1; + sc_signal<int>& o2; + sc_signal<int>& o3; + sc_signal<int>& o4; + sc_signal<int>& o5; + + // Constructor + test ( + sc_module_name NAME, + sc_clock& CLK, + + const sc_signal<bool>& RESET_SIG, + + const sc_signal<int>& I1, + const sc_signal<int>& I2, + const sc_signal<int>& I3, + const sc_signal<int>& I4, + const sc_signal<int>& I5, + + const sc_signal<bool>& CONT1, + const sc_signal<bool>& CONT2, + const sc_signal<bool>& CONT3, + + sc_signal<int>& O1, + sc_signal<int>& O2, + sc_signal<int>& O3, + sc_signal<int>& O4, + sc_signal<int>& O5) + : reset_sig(RESET_SIG), i1(I1), i2(I2), + i3(I3), i4(I4), i5(I5), cont1 (CONT1), cont2 (CONT2), + cont3 (CONT3), o1(O1), o2(O2), o3(O3), o4(O4), o5(O5) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + reset_signal_is(reset_sig,true); + } + + void entry(); +}; |