1 files changed, 48 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/unit/control/timing/timing.cpp b/src/systemc/tests/systemc/misc/unit/control/timing/timing.cpp
new file mode 100644
index 000000000..db47e9b6e
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/unit/control/timing/timing.cpp
@@ -0,0 +1,48 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  timing.cpp -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "rdy.h"
+#include "tb.h" 	/** Definition of testbench Structure **/
+
+int sc_main(int ac, char *av[])
+{
+  sc_clock clk( "CLK", 20, SC_NS, 0.5, 0, SC_NS); // Clock function
+  testbench tb1("TB1", clk);	// Testbench Instantiation
+  sc_start( 120, SC_NS );          // Simulation control
+  return 0;
+}