1 files changed, 83 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/rdy_gen.h b/src/systemc/tests/systemc/misc/unit/control/wait_until/rdy_gen.h
new file mode 100644
index 000000000..70d10e356
--- /dev/null
+++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/rdy_gen.h
@@ -0,0 +1,83 @@
+/*****************************************************************************
+
+  Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+  more contributor license agreements.  See the NOTICE file distributed
+  with this work for additional information regarding copyright ownership.
+  Accellera licenses this file to you under the Apache License, Version 2.0
+  (the "License"); you may not use this file except in compliance with the
+  License.  You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+  Unless required by applicable law or agreed to in writing, software
+  distributed under the License is distributed on an "AS IS" BASIS,
+  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+  implied.  See the License for the specific language governing
+  permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  rdy_gen.h -- 
+
+  Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+  changes you are making here.
+
+      Name, Affiliation, Date:
+  Description of Modification:
+
+ *****************************************************************************/
+
+/******************************************************************************/
+/***************************    RDY_GEN 		 **********************/
+/******************************************************************************/
+
+SC_MODULE( RDY_GEN )
+{
+    SC_HAS_PROCESS( RDY_GEN );
+
+    sc_in_clk clk;
+
+  sc_signal<bool>& ready;  // Output
+ 
+  RDY_GEN (   sc_module_name        	NAME,
+                sc_clock&		TICK_P,
+                sc_signal<bool>&  	READY )
+ 
+    :
+		ready (READY)
+
+  {
+       clk (TICK_P);
+	   SC_CTHREAD( entry, clk.pos() );
+  }
+ 
+  void entry();
+ 
+};
+
+void
+RDY_GEN::entry()
+{
+  ready.write(1);
+  wait();
+  cout << sc_time_stamp() << " : "
+       << "WRITING ready = 1" << endl;
+
+  ready.write(0);
+  wait(); 
+  cout << sc_time_stamp() << " : "
+       << "WRITING ready = 0" << endl;
+
+  ready.write(1);
+  wait();
+  cout << sc_time_stamp() << " : "
+       << "WRITING ready = 1" << endl;
+}