diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/unit/control/wait_until')
5 files changed, 272 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/golden/waiting.log b/src/systemc/tests/systemc/misc/unit/control/wait_until/golden/waiting.log new file mode 100644 index 000000000..680547393 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/golden/waiting.log @@ -0,0 +1,8 @@ +SystemC Simulation +20 ns : WRITING ready = 1 +20 ns : READY = 1 DETECTED +40 ns : WRITING ready = 0 +60 ns : WRITING ready = 1 +60 ns : READY = 1 DETECTED +80 ns : READY = 1 DETECTED +100 ns : READY = 1 DETECTED diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/rdy_gen.h b/src/systemc/tests/systemc/misc/unit/control/wait_until/rdy_gen.h new file mode 100644 index 000000000..70d10e356 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/rdy_gen.h @@ -0,0 +1,83 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + rdy_gen.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** RDY_GEN **********************/ +/******************************************************************************/ + +SC_MODULE( RDY_GEN ) +{ + SC_HAS_PROCESS( RDY_GEN ); + + sc_in_clk clk; + + sc_signal<bool>& ready; // Output + + RDY_GEN ( sc_module_name NAME, + sc_clock& TICK_P, + sc_signal<bool>& READY ) + + : + ready (READY) + + { + clk (TICK_P); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); + +}; + +void +RDY_GEN::entry() +{ + ready.write(1); + wait(); + cout << sc_time_stamp() << " : " + << "WRITING ready = 1" << endl; + + ready.write(0); + wait(); + cout << sc_time_stamp() << " : " + << "WRITING ready = 0" << endl; + + ready.write(1); + wait(); + cout << sc_time_stamp() << " : " + << "WRITING ready = 1" << endl; +} diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/tb.h b/src/systemc/tests/systemc/misc/unit/control/wait_until/tb.h new file mode 100644 index 000000000..cf43c63e9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/tb.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** Testbench Function **********************/ +/******************************************************************************/ + +SC_MODULE( testbench ) +{ + sc_signal<bool> ready; + RDY_GEN rd1; + WAIT_RDY wt1; + + testbench ( sc_module_name NAME, + sc_clock& TICK_P ) + + : ready ("ready"), + rd1 ("RD1", TICK_P, ready), + wt1 ("WT1", TICK_P, ready) + {} +}; diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/wait_rdy.h b/src/systemc/tests/systemc/misc/unit/control/wait_until/wait_rdy.h new file mode 100644 index 000000000..bfd36bbac --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/wait_rdy.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + wait_rdy.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** WAIT_RDY **********************/ +/******************************************************************************/ + +SC_MODULE( WAIT_RDY ) +{ + SC_HAS_PROCESS( WAIT_RDY ); + + sc_in_clk clk; + + const sc_signal<bool>& ready; // Input + + WAIT_RDY ( sc_module_name NAME, + sc_clock& TICK_P, + const sc_signal<bool>& READY ) + + : + ready (READY) + + { + clk (TICK_P); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); + +}; + +void +WAIT_RDY::entry() +{ + while (true) { + do { wait(); } while (ready != 1); + + cout << sc_time_stamp() << " : " + << "READY = 1 DETECTED" << endl; + } +} diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/waiting.cpp b/src/systemc/tests/systemc/misc/unit/control/wait_until/waiting.cpp new file mode 100644 index 000000000..8eaa80da9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/waiting.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + waiting.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "rdy_gen.h" +#include "wait_rdy.h" +#include "tb.h" /** Definition of testbench Structure **/ + +int +sc_main(int ac, char *av[]) +{ + sc_clock clk( "CLK", 20, SC_NS, 0.5, 0, SC_NS); // Clock function + testbench tb1("TB1", clk); // Testbench Instantiation + + sc_start( 120, SC_NS ); // Simulation control + return 0; +} |