diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/unit/control')
23 files changed, 1334 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/unit/control/demo1/demo1.f b/src/systemc/tests/systemc/misc/unit/control/demo1/demo1.f new file mode 100644 index 000000000..a9e7a24d8 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/demo1/demo1.f @@ -0,0 +1,3 @@ +demo1/main.cpp +demo1/proc1.cpp +demo1/proc2.cpp diff --git a/src/systemc/tests/systemc/misc/unit/control/demo1/golden/demo1.log b/src/systemc/tests/systemc/misc/unit/control/demo1/golden/demo1.log new file mode 100644 index 000000000..bbcbfa1b2 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/demo1/golden/demo1.log @@ -0,0 +1,11 @@ +SystemC Simulation +Ready = False +Ack = False +Ready = True +Ack = True +Ready = False +Ack = False +Ready = True +Ack = True +Ready = False +Ack = False diff --git a/src/systemc/tests/systemc/misc/unit/control/demo1/main.cpp b/src/systemc/tests/systemc/misc/unit/control/demo1/main.cpp new file mode 100644 index 000000000..386c9dec7 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/demo1/main.cpp @@ -0,0 +1,56 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Main file for handshaking simulation */ + +#include "systemc.h" +#include "proc1.h" +#include "proc2.h" + +int sc_main(int ac, char *av[]) +{ + sc_signal<bool> data_ready("Ready"); + sc_signal<bool> data_ack("Ack"); + + sc_clock clock("CLOCK", 10, SC_NS, 0.5, 0.0, SC_NS); + + proc1 Master("MasterProcess", clock, data_ack, data_ready); + proc2 Slave("SlaveProcess", clock, data_ready, data_ack); + + sc_start(100, SC_NS); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/unit/control/demo1/proc1.cpp b/src/systemc/tests/systemc/misc/unit/control/demo1/proc1.cpp new file mode 100644 index 000000000..6c0fb35fb --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/demo1/proc1.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + proc1.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename proc1.cc */ +/* This is the implementation file for synchronous process `proc1' */ + +#include "systemc.h" +#include "proc1.h" + +void proc1::entry() +{ + data_ready.write(false); + wait(); + cout << "Ready \t = False" << endl; + + while(true) { + data_ready.write(true); + do { wait(); } while (data_ack != true); + cout << "Ack \t = True" << endl; + + data_ready.write(false); + do { wait(); } while (data_ack != false); + cout << "Ack \t = False" << endl; + } +} // end of entry function + diff --git a/src/systemc/tests/systemc/misc/unit/control/demo1/proc1.h b/src/systemc/tests/systemc/misc/unit/control/demo1/proc1.h new file mode 100644 index 000000000..873170e65 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/demo1/proc1.h @@ -0,0 +1,64 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + proc1.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename proc1.h */ +/* This is the interface file for synchronous process `proc1' */ + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in_clk clk; + + const sc_signal<bool>& data_ack; //input + sc_signal<bool>& data_ready; //output + + //Constructor + proc1(sc_module_name NAME, + sc_clock& CLK, + const sc_signal<bool>& DATA_ACK, + sc_signal<bool>& DATA_READY) + : data_ack(DATA_ACK), data_ready(DATA_READY) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + // Process functionality in member function below + void entry(); +}; + diff --git a/src/systemc/tests/systemc/misc/unit/control/demo1/proc2.cpp b/src/systemc/tests/systemc/misc/unit/control/demo1/proc2.cpp new file mode 100644 index 000000000..ef0c0e004 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/demo1/proc2.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + proc2.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename proc2.cc */ +/* This is the implementation file for synchronous process `proc2' */ + +#include "systemc.h" +#include "proc2.h" + +void proc2::entry() +{ + data_ack.write(false); + wait(); + cout << "Ack \t = False" << endl; + + while (true) { + do { wait(); } while (data_ready != true); + data_ack.write(true); + cout << "Ready \t = True" << endl; + + do { wait(); } while (data_ready != false); + data_ack.write(false); + cout << "Ready \t = False" << endl; + } +} // end of entry function + diff --git a/src/systemc/tests/systemc/misc/unit/control/demo1/proc2.h b/src/systemc/tests/systemc/misc/unit/control/demo1/proc2.h new file mode 100644 index 000000000..1c6ad7c77 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/demo1/proc2.h @@ -0,0 +1,64 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + proc2.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename proc2.h */ +/* This is the interface file for synchronous process `proc2' */ + +SC_MODULE( proc2 ) +{ + SC_HAS_PROCESS( proc2 ); + + sc_in_clk clk; + + const sc_signal<bool>& data_ready; //input + sc_signal<bool>& data_ack; //output + + //Constructor + proc2(sc_module_name NAME, + sc_clock& CLK, + const sc_signal<bool>& DATA_READY, + sc_signal<bool>& DATA_ACK) + : data_ready(DATA_READY), data_ack(DATA_ACK) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + // Process functionality in member function below + void entry(); +}; + diff --git a/src/systemc/tests/systemc/misc/unit/control/posedge/golden/posedge.log b/src/systemc/tests/systemc/misc/unit/control/posedge/golden/posedge.log new file mode 100644 index 000000000..38978c665 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/posedge/golden/posedge.log @@ -0,0 +1,9 @@ +SystemC Simulation +10 ns : ready = 0 (RDY) +30 ns : ready = 0 (RDY) +40 ns : POSEDGE READY DETECTED +50 ns : ready = 1 (RDY) +70 ns : ready = 0 (RDY) +80 ns : POSEDGE READY DETECTED +90 ns : ready = 1 (RDY) +Terminating process TB1.RD1.entry diff --git a/src/systemc/tests/systemc/misc/unit/control/posedge/posedge.cpp b/src/systemc/tests/systemc/misc/unit/control/posedge/posedge.cpp new file mode 100644 index 000000000..89968ae01 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/posedge/posedge.cpp @@ -0,0 +1,52 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + posedge.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "rdy.h" +#include "stim.h" +#include "tb.h" /** Definition of testbench Structure **/ + +/******************************************************************************/ +/*************************** Main Function *********************************/ +/******************************************************************************/ +int sc_main(int ac, char *av[]) +{ + sc_clock clk( "CLK", 20, SC_NS, 0.5, 0, SC_NS); // Clock function + testbench tb1("TB1", clk); // Testbench Instantiation + sc_start( 120, SC_NS ); // Simulation control + return 0; +} diff --git a/src/systemc/tests/systemc/misc/unit/control/posedge/rdy.h b/src/systemc/tests/systemc/misc/unit/control/posedge/rdy.h new file mode 100644 index 000000000..d9c988538 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/posedge/rdy.h @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + rdy.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +/******************************************************************************/ +/*************************** rdy Function **********************/ +/******************************************************************************/ + +SC_MODULE( RDY ) +{ + SC_HAS_PROCESS( RDY ); + + sc_in_clk clk; + + /*** Input and Output Ports ***/ + sc_signal<bool>& data; + + /*** Constructor ***/ + RDY ( sc_module_name NAME, + sc_clock& TICK_N, + sc_signal<bool>& DATA ) + + : + data (DATA) + + { + clk (TICK_N); + SC_CTHREAD( entry, clk.neg() ); + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +RDY::entry() +{ + // IMPLICIT wait(); AT FIRST NEGEDGE + cout << sc_time_stamp() << " : " // Time 10 + << "ready = " << data + << "\t\t (RDY) " + << endl; + data.write(0); + + wait(); // Time 30 + cout << sc_time_stamp() << " : " + << "ready = " << data + << "\t\t (RDY) " + << endl; + data.write(1); + + wait(); // Time 50 + cout << sc_time_stamp() << " : " + << "ready = " << data + << "\t\t (RDY) " + << endl; + data.write(0); + + wait(); // Time 70 + cout << sc_time_stamp() << " : " + << "ready = " << data + << "\t\t (RDY) " + << endl; + data.write(1); + + wait(); // Time 90 + cout << sc_time_stamp() << " : " + << "ready = " << data + << "\t\t (RDY) " + << endl; + + halt(); +} diff --git a/src/systemc/tests/systemc/misc/unit/control/posedge/stim.h b/src/systemc/tests/systemc/misc/unit/control/posedge/stim.h new file mode 100644 index 000000000..18e2dd617 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/posedge/stim.h @@ -0,0 +1,80 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stim.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +/******************************************************************************/ +/*************************** stim Function **********************/ +/******************************************************************************/ + +SC_MODULE( STIM ) +{ + SC_HAS_PROCESS( STIM ); + + sc_in_clk clk; + + /*** Input and Output Ports ***/ + const sc_signal<bool>& data; + + /*** Constructor ***/ + STIM ( sc_module_name NAME, + sc_clock& TICK_P, + const sc_signal<bool>& DATA ) + + : + data (DATA) + + { + clk (TICK_P); + SC_CTHREAD( entry, clk.pos() ); + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +STIM::entry() +{ + while(true) { + at_posedge(data); + cout << sc_time_stamp() << " : " + << "POSEDGE READY DETECTED" + << endl; + } +} diff --git a/src/systemc/tests/systemc/misc/unit/control/posedge/tb.h b/src/systemc/tests/systemc/misc/unit/control/posedge/tb.h new file mode 100644 index 000000000..095450002 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/posedge/tb.h @@ -0,0 +1,58 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** Testbench Function **********************/ +/******************************************************************************/ + +SC_MODULE( testbench ) +{ + sc_signal<bool> ready; + STIM st1; + RDY rd1; + + /*** Constructor ***/ + testbench ( sc_module_name NAME, + sc_clock& TICK ) + + : sc_module(), + st1 ("ST1", TICK, ready), + rd1 ("RD1", TICK, ready) + { + end_module(); + } +}; diff --git a/src/systemc/tests/systemc/misc/unit/control/timing/golden/timing.log b/src/systemc/tests/systemc/misc/unit/control/timing/golden/timing.log new file mode 100644 index 000000000..fcf7ffb4a --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/timing/golden/timing.log @@ -0,0 +1,33 @@ +SystemC Simulation + +START OF SIM -- CLOCK AT NEGEDGE (10,30,50,...) +10 ns : ready[S] = 0 a[V] = 0 + a = 0 +10 ns : ready[S] = 0 a[V] = 0 + ready = 0 +10 ns : ready[S] = 0 a[V] = 0 + +CLK +30 ns : ready[S] = 0 a[V] = 0 + a = 1 +30 ns : ready[S] = 0 a[V] = 1 + ready = 1 +30 ns : ready[S] = 0 a[V] = 1 + +CLK +50 ns : ready[S] = 1 a[V] = 1 + a = 0 +50 ns : ready[S] = 1 a[V] = 0 + ready = 0 +50 ns : ready[S] = 1 a[V] = 0 + +CLK +70 ns : ready[S] = 0 a[V] = 0 + a = 1 +70 ns : ready[S] = 0 a[V] = 1 + ready = 1 +70 ns : ready[S] = 0 a[V] = 1 + +CLK +90 ns : ready[S] = 1 a[V] = 1 +Terminating process TB1.RD1.entry diff --git a/src/systemc/tests/systemc/misc/unit/control/timing/rdy.h b/src/systemc/tests/systemc/misc/unit/control/timing/rdy.h new file mode 100644 index 000000000..a4e825581 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/timing/rdy.h @@ -0,0 +1,148 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + rdy.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +/******************************************************************************/ +/*************************** rdy Function **********************/ +/******************************************************************************/ + +SC_MODULE( RDY ) +{ + SC_HAS_PROCESS( RDY ); + + sc_in_clk clk; + + /*** Input and Output Ports ***/ + sc_signal<bool>& data; + + /*** Constructor ***/ + RDY ( sc_module_name NAME, + sc_clock& TICK_N, + sc_signal<bool>& DATA ) + + : + data (DATA) + + { + clk (TICK_N); + SC_CTHREAD( entry, clk.neg() ); + } + + /*** Call to Process Functionality ***/ + void entry(); + +}; + +void +RDY::entry() +{ + // int a; + int a = 0; + + cout << "\nSTART OF SIM -- CLOCK AT NEGEDGE (10,30,50,...) " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + + a = 0; cout << "\t\t\t a = 0 " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + data.write(0); cout << " ready = 0 " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + wait(); cout << "\nCLK " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + + a = 1; cout << "\t\t a = 1 " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + data.write(1); cout << " ready = 1 " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + wait(); cout << "\nCLK " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + + a = 0; cout << "\t\t a = 0 " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + data.write(0); cout << " ready = 0 " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + wait(); cout << "\nCLK " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + + a = 1; cout << "\t\t a = 1 " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + data.write(1); cout << " ready = 1 " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + wait(); cout << "\nCLK " << endl; + cout << sc_time_stamp() << " : " + << " ready[S] = " << data + << " a[V] = " << a + << endl; + + halt(); +} diff --git a/src/systemc/tests/systemc/misc/unit/control/timing/tb.h b/src/systemc/tests/systemc/misc/unit/control/timing/tb.h new file mode 100644 index 000000000..08790979f --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/timing/tb.h @@ -0,0 +1,53 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** Testbench Function **********************/ +/******************************************************************************/ + +SC_MODULE( testbench ) +{ + sc_signal<bool> ready; + RDY rd1; + + testbench ( sc_module_name NAME, + sc_clock& TICK_N ) + + : ready ("ready"), + rd1 ("RD1", TICK_N, ready) + {} +}; diff --git a/src/systemc/tests/systemc/misc/unit/control/timing/timing.cpp b/src/systemc/tests/systemc/misc/unit/control/timing/timing.cpp new file mode 100644 index 000000000..db47e9b6e --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/timing/timing.cpp @@ -0,0 +1,48 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + timing.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "rdy.h" +#include "tb.h" /** Definition of testbench Structure **/ + +int sc_main(int ac, char *av[]) +{ + sc_clock clk( "CLK", 20, SC_NS, 0.5, 0, SC_NS); // Clock function + testbench tb1("TB1", clk); // Testbench Instantiation + sc_start( 120, SC_NS ); // Simulation control + return 0; +} diff --git a/src/systemc/tests/systemc/misc/unit/control/wait/golden/wait.log b/src/systemc/tests/systemc/misc/unit/control/wait/golden/wait.log new file mode 100644 index 000000000..6d243dcc5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait/golden/wait.log @@ -0,0 +1 @@ +SystemC Simulation diff --git a/src/systemc/tests/systemc/misc/unit/control/wait/wait.cpp b/src/systemc/tests/systemc/misc/unit/control/wait/wait.cpp new file mode 100644 index 000000000..bc3044caa --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait/wait.cpp @@ -0,0 +1,153 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + wait.cpp -- + + Original Author: Daniel Aarno, Intel, Corp 2015-07-23 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include <systemc> + +using sc_core::sc_time; +using sc_core::SC_US; + +namespace { +int first_line = 0; + +bool endsWith(const std::string &str, const std::string &ending) { + if (ending.size() > str.size()) { + return false; + } + return std::equal(ending.rbegin(), ending.rend(), str.rbegin()); +} + +bool waitFunIsTrue() { + if (sc_core::sc_time_stamp() < sc_time(2000, SC_US)) { + return false; + } + + if (sc_core::sc_time_stamp() < sc_time(3000, SC_US)) { + sc_time delay(10, SC_US); + SC_WAITN(delay); + return false; + } + + if (sc_core::sc_time_stamp() < sc_time(4000, SC_US)) { + return false; + } + + return true; +} + +SC_MODULE(Wait) { + SC_CTOR(Wait) : clk( "clk", 10, SC_US, 0.5, 100, SC_US) { + SC_THREAD(thread); + sensitive << clk; + } + + void thread() { + sc_time delay(10, SC_US); + wait(delay); // 1st + + first_line = __LINE__ + 1; + SC_WAITN(delay); // Wait some time + wait(delay); // 2nd + + SC_WAIT(); // Wait for clk + wait(delay); // 3rd + + SC_WAIT_UNTIL(sc_core::sc_time_stamp() > sc_time(1000, SC_US)); + wait(delay); // 4th + + SC_WAIT_UNTIL(waitFunIsTrue()); + } + + sc_core::sc_clock clk; +}; + +} // namespace + +int sc_main(int argc, char ** argv) { + Wait w("dut"); + + sc_core::sc_process_handle hnd( sc_core::sc_find_object("dut.thread") ); + const sc_core::sc_process_b *thread + = dynamic_cast<sc_core::sc_process_b*>(hnd.get_process_object()); + sc_assert(hnd.valid() && thread); + + sc_assert(thread->file == NULL); // 1st wait(delay) + sc_assert(thread->lineno == 0); + sc_core::sc_start(sc_time(15, SC_US)); + + int lineno = first_line; + sc_assert(endsWith(thread->file, "wait.cpp")); // SC_WAITN + sc_assert(thread->lineno == lineno); + sc_core::sc_start(sc_time(10, SC_US)); + sc_assert(thread->file == NULL); // 2nd wait(delay) + sc_assert(thread->lineno == 0); + sc_core::sc_start(sc_time(10, SC_US)); + + lineno += 3; + sc_assert(endsWith(thread->file, "wait.cpp")); // SC_WAIT + sc_assert(thread->lineno == lineno); + sc_core::sc_start(sc_time(70, SC_US)); + sc_assert(thread->file == NULL); // 3rd wait(delay) + sc_assert(thread->lineno == 0); + sc_core::sc_start(sc_time(10, SC_US)); + + lineno += 3; + sc_assert(endsWith(thread->file, "wait.cpp")); // SC_WAIT_UNTIL + sc_assert(thread->lineno == lineno); + sc_core::sc_start(sc_time(900, SC_US)); + sc_assert(thread->file == NULL); // 4th wait(delay) + sc_assert(thread->lineno == 0); + + // Ensure that SC_WAIT_UNTIL can handle nested wait calls + sc_core::sc_start(sc_time(10, SC_US)); + lineno += 3; + sc_assert(endsWith(thread->file, "wait.cpp")); // 2nd SC_WAIT_UNTIL + sc_assert(thread->lineno == lineno); + sc_core::sc_start(sc_time(980, SC_US)); // time should be 2005 + sc_assert(endsWith(thread->file, "wait.cpp")); // SC_WAITN in waitFunIsTrue + sc_assert(thread->lineno == 60); + sc_core::sc_start(sc_time(95, SC_US)); + sc_assert(endsWith(thread->file, "wait.cpp")); + sc_assert(thread->lineno == 60); + sc_core::sc_start(sc_time(910, SC_US)); + sc_assert(endsWith(thread->file, "wait.cpp")); // 2nd SC_WAIT_UNTIL + sc_assert(thread->lineno == lineno); + sc_core::sc_start(sc_time(1000, SC_US)); + sc_assert(thread->file == NULL); // done + sc_assert(thread->lineno == 0); + + return 0; +} diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/golden/waiting.log b/src/systemc/tests/systemc/misc/unit/control/wait_until/golden/waiting.log new file mode 100644 index 000000000..680547393 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/golden/waiting.log @@ -0,0 +1,8 @@ +SystemC Simulation +20 ns : WRITING ready = 1 +20 ns : READY = 1 DETECTED +40 ns : WRITING ready = 0 +60 ns : WRITING ready = 1 +60 ns : READY = 1 DETECTED +80 ns : READY = 1 DETECTED +100 ns : READY = 1 DETECTED diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/rdy_gen.h b/src/systemc/tests/systemc/misc/unit/control/wait_until/rdy_gen.h new file mode 100644 index 000000000..70d10e356 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/rdy_gen.h @@ -0,0 +1,83 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + rdy_gen.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** RDY_GEN **********************/ +/******************************************************************************/ + +SC_MODULE( RDY_GEN ) +{ + SC_HAS_PROCESS( RDY_GEN ); + + sc_in_clk clk; + + sc_signal<bool>& ready; // Output + + RDY_GEN ( sc_module_name NAME, + sc_clock& TICK_P, + sc_signal<bool>& READY ) + + : + ready (READY) + + { + clk (TICK_P); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); + +}; + +void +RDY_GEN::entry() +{ + ready.write(1); + wait(); + cout << sc_time_stamp() << " : " + << "WRITING ready = 1" << endl; + + ready.write(0); + wait(); + cout << sc_time_stamp() << " : " + << "WRITING ready = 0" << endl; + + ready.write(1); + wait(); + cout << sc_time_stamp() << " : " + << "WRITING ready = 1" << endl; +} diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/tb.h b/src/systemc/tests/systemc/misc/unit/control/wait_until/tb.h new file mode 100644 index 000000000..cf43c63e9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/tb.h @@ -0,0 +1,55 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tb.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** Testbench Function **********************/ +/******************************************************************************/ + +SC_MODULE( testbench ) +{ + sc_signal<bool> ready; + RDY_GEN rd1; + WAIT_RDY wt1; + + testbench ( sc_module_name NAME, + sc_clock& TICK_P ) + + : ready ("ready"), + rd1 ("RD1", TICK_P, ready), + wt1 ("WT1", TICK_P, ready) + {} +}; diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/wait_rdy.h b/src/systemc/tests/systemc/misc/unit/control/wait_until/wait_rdy.h new file mode 100644 index 000000000..bfd36bbac --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/wait_rdy.h @@ -0,0 +1,75 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + wait_rdy.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/******************************************************************************/ +/*************************** WAIT_RDY **********************/ +/******************************************************************************/ + +SC_MODULE( WAIT_RDY ) +{ + SC_HAS_PROCESS( WAIT_RDY ); + + sc_in_clk clk; + + const sc_signal<bool>& ready; // Input + + WAIT_RDY ( sc_module_name NAME, + sc_clock& TICK_P, + const sc_signal<bool>& READY ) + + : + ready (READY) + + { + clk (TICK_P); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); + +}; + +void +WAIT_RDY::entry() +{ + while (true) { + do { wait(); } while (ready != 1); + + cout << sc_time_stamp() << " : " + << "READY = 1 DETECTED" << endl; + } +} diff --git a/src/systemc/tests/systemc/misc/unit/control/wait_until/waiting.cpp b/src/systemc/tests/systemc/misc/unit/control/wait_until/waiting.cpp new file mode 100644 index 000000000..8eaa80da9 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/control/wait_until/waiting.cpp @@ -0,0 +1,51 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + waiting.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "rdy_gen.h" +#include "wait_rdy.h" +#include "tb.h" /** Definition of testbench Structure **/ + +int +sc_main(int ac, char *av[]) +{ + sc_clock clk( "CLK", 20, SC_NS, 0.5, 0, SC_NS); // Clock function + testbench tb1("TB1", clk); // Testbench Instantiation + + sc_start( 120, SC_NS ); // Simulation control + return 0; +} |