diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/unit/data/general/concat_port')
8 files changed, 453 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/unit/data/general/concat_port/common.h b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/common.h new file mode 100644 index 000000000..0f0b2b812 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/common.h @@ -0,0 +1,48 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_bv<8> bool_vector8; +typedef sc_bv<16> bool_vector16; +typedef sc_signal<bool_vector8> signal_bool_vector8; +typedef sc_signal<bool_vector16> signal_bool_vector16; + +#endif diff --git a/src/systemc/tests/systemc/misc/unit/data/general/concat_port/concat_port.cpp b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/concat_port.cpp new file mode 100644 index 000000000..b3ac6f5c1 --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/concat_port.cpp @@ -0,0 +1,85 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + concat_port.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /*********************************************/ + /* Implementation Filename: concat_port.cc */ + /*********************************************/ + +#include "concat_port.h" + +void +concat_port::entry() +{ + bool_vector8 tmp_a; + bool_vector8 tmp_b; + + while (true) { + + done.write(0); + do { wait(); } while (ready != 1); + + tmp_a = a.read(); + tmp_b = b.read(); + + switch (mode.read()) { + + case 0: c.write( (tmp_a.range(7,4), tmp_b.range(7,4)) ); + d.write( (tmp_a, tmp_b) ); + break; + + case 1: c.write( (tmp_a.range(0,7)) ); + d.write( (tmp_a.range(0,7), tmp_b.range(0,7)) ); + break; + + case 2: c.write( (tmp_a[0], tmp_b.range(1,4), tmp_a.range(7,5)) ); + d.write( (tmp_a.range(7,4), tmp_b.range(7,4), + tmp_a.range(3,0), tmp_b.range(3,0)) ); + break; + + case 3: c.write( ("1", tmp_b.range(2,0), "0", tmp_a.range(2,0)) ); + d.write( ("11", tmp_a.range(6,0), tmp_b.range(6,0)) ); + break; + + default: cout << "Error: Mode " << mode.read() + << " does not exist!" << endl; + break; + + } + done.write(1); + wait(); + } +} diff --git a/src/systemc/tests/systemc/misc/unit/data/general/concat_port/concat_port.f b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/concat_port.f new file mode 100644 index 000000000..0b1d172ff --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/concat_port.f @@ -0,0 +1,3 @@ +concat_port/concat_port.cpp +concat_port/stimgen.cpp +concat_port/main.cpp diff --git a/src/systemc/tests/systemc/misc/unit/data/general/concat_port/concat_port.h b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/concat_port.h new file mode 100644 index 000000000..155c4cbed --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/concat_port.h @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + concat_port.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /**************************************/ + /* Interface Filename: concat_port.h */ + /**************************************/ + +#include "common.h" + +SC_MODULE( concat_port ) +{ + SC_HAS_PROCESS( concat_port ); + + sc_in_clk clk; + + // Inputs + const signal_bool_vector8& a; + const signal_bool_vector8& b; + const sc_signal<int>& mode; + const sc_signal<bool>& ready; + // Outputs + signal_bool_vector8& c; + signal_bool_vector16& d; + sc_signal<bool>& done; + + // Constructor + concat_port (sc_module_name NAME, + sc_clock& TICK, + const signal_bool_vector8& A, + const signal_bool_vector8& B, + const sc_signal<int>& MODE, + const sc_signal<bool>& READY, + signal_bool_vector8& C, + signal_bool_vector16& D, + sc_signal<bool>& DONE ) + + : + a (A), + b (B), + mode (MODE), + ready (READY), + c (C), + d (D), + done (DONE) + + { + clk (TICK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; diff --git a/src/systemc/tests/systemc/misc/unit/data/general/concat_port/golden/concat_port.log b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/golden/concat_port.log new file mode 100644 index 000000000..c3569520e --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/golden/concat_port.log @@ -0,0 +1,11 @@ +SystemC Simulation +a = 01010101 b = 11110000 mode = 0 + c = 01011111 d = 0101010111110000 +a = 01010101 b = 11110000 mode = 1 + c = 10101010 d = 1010101000001111 +a = 01010101 b = 11110000 mode = 2 + c = 10001010 d = 0101111101010000 +a = 01010101 b = 11110000 mode = 3 + c = 10000101 d = 1110101011110000 + +Info: /OSCI/SystemC: Simulation stopped by user. diff --git a/src/systemc/tests/systemc/misc/unit/data/general/concat_port/main.cpp b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/main.cpp new file mode 100644 index 000000000..13603f8de --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/main.cpp @@ -0,0 +1,68 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /***************************************/ + /* Main Filename: main.cc */ + /***************************************/ + +#include "concat_port.h" +#include "stimgen.h" + +int sc_main(int ac, char *av[]) +{ + +// Signal Instantiation + signal_bool_vector8 a ("a"); + signal_bool_vector8 b ("b"); + signal_bool_vector8 c ("c"); + signal_bool_vector16 d ("d"); + sc_signal<int> mode ("mode"); + sc_signal<bool> ready ("ready"); + sc_signal<bool> done ("done"); + +// Clock Instantiation + sc_clock clk( "clock", 10, SC_NS, 0.5, 0, SC_NS); + +// Process Instantiation + concat_port D1 ("D1", clk, a, b, mode, ready, c, d, done); + + stimgen T1 ("T1", clk, c, d, done, a, b, mode, ready); + +// Simulation Run Control + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/unit/data/general/concat_port/stimgen.cpp b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/stimgen.cpp new file mode 100644 index 000000000..cfd9e7a6c --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/stimgen.cpp @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimgen.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /*******************************************/ + /* Implementation Filename: stimgen.cc */ + /*******************************************/ + +#include "stimgen.h" + +void +stimgen::entry() +{ + ready.write(0); + wait(); + + a.write("01010101"); + b.write("11110000"); + ready.write(1); + + for (int i=0; i < 4; i++) { + mode.write(i); + wait(); + cout << "a = " << a << " b = " << b << " mode = " << mode << endl; + do { wait(); } while (done != 1); + cout << "\t c = " << c << " d = " << d << endl; + } + + ready.write(0); + wait(); + + sc_stop(); +} diff --git a/src/systemc/tests/systemc/misc/unit/data/general/concat_port/stimgen.h b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/stimgen.h new file mode 100644 index 000000000..d0b43049a --- /dev/null +++ b/src/systemc/tests/systemc/misc/unit/data/general/concat_port/stimgen.h @@ -0,0 +1,86 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + stimgen.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + + /**************************************/ + /* Interface Filename: stimgen.h */ + /**************************************/ + +#include "common.h" + +SC_MODULE( stimgen ) +{ + SC_HAS_PROCESS( stimgen ); + + sc_in_clk clk; + + // Inputs + const signal_bool_vector8& c; + const signal_bool_vector16& d; + const sc_signal<bool>& done; + // Outputs + signal_bool_vector8& a; + signal_bool_vector8& b; + sc_signal<int>& mode; + sc_signal<bool>& ready; + + // Constructor + stimgen (sc_module_name NAME, + sc_clock& TICK, + const signal_bool_vector8& C, + const signal_bool_vector16& D, + const sc_signal<bool>& DONE, + signal_bool_vector8& A, + signal_bool_vector8& B, + sc_signal<int>& MODE, + sc_signal<bool>& READY ) + + : + c (C), + d (D), + done (DONE), + a (A), + b (B), + mode (MODE), + ready (READY) + + { + clk (TICK); + SC_CTHREAD( entry, clk.pos() ); + } + + void entry(); +}; |