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Diffstat (limited to 'src/systemc/tests/systemc/misc/user_guide/chpt12.1/ram.h')
-rw-r--r-- | src/systemc/tests/systemc/misc/user_guide/chpt12.1/ram.h | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt12.1/ram.h b/src/systemc/tests/systemc/misc/user_guide/chpt12.1/ram.h new file mode 100644 index 000000000..cbbcd56f5 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt12.1/ram.h @@ -0,0 +1,74 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + ram.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename ram.h */ +/* This is the interface file for asynchronous process 'ram' */ + +#include "common.h" + +SC_MODULE( ram ) +{ + SC_HAS_PROCESS( ram ); + + const signal_bool_vector32& datain; //input + const sc_signal<bool>& cs; //input + const sc_signal<bool>& we; //input + const signal_bool_vector10& addr; //input + signal_bool_vector32& dataout; //output + + //Constructor + ram(sc_module_name NAME, + const signal_bool_vector32& DATAIN, + const sc_signal<bool>& CS, + const sc_signal<bool>& WE, + const signal_bool_vector10& ADDR, + signal_bool_vector32& DATAOUT) + : datain(DATAIN), cs(CS), we(WE), + addr(ADDR), dataout(DATAOUT) + { + SC_METHOD( entry ); + sensitive << datain; + sensitive << cs; + sensitive << we; + sensitive << addr; + } + + // Process functionality in member function below + void entry(); +}; + + |