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Diffstat (limited to 'src/systemc/tests/systemc/misc/user_guide/chpt12.2')
8 files changed, 432 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt12.2/accessor.cpp b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/accessor.cpp new file mode 100644 index 000000000..dbab69698 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/accessor.cpp @@ -0,0 +1,84 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + accessor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename accessor.cc */ +/* This is the implementation file for synchronous process 'accessor' */ + +#include "accessor.h" + +void accessor::entry() +{ + int addr; + int datao; + int datai; + + addr = 10; + datao = 0xdeadbeef; + + while (true) { + // Write memory location first + chip_select.write(true); + write_enable.write(true); + address.write(addr); + dataout.write(datao); + cout << "Accessor: Data Written = " << hex << datao << " at address " + << hex << addr << endl; + wait(memory_latency); // To make all the outputs appear at the interface + + // some process functionality not shown here during which chip + // chip select is deasserted and bus is tristated + chip_select.write(false); + dataout.write(0); + wait(); + + // Now read memory location + chip_select.write(true); + write_enable.write(false); + address.write(addr); + wait(memory_latency); // For data to appear + + datai = datain.read().to_int(); + cout << "Accessor: Data Read = " << hex << datai << " from address " + << hex << addr << endl; + chip_select.write(false); + wait(); + + addr++; + datao++; + } +} // end of entry function + diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt12.2/accessor.h b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/accessor.h new file mode 100644 index 000000000..74e1ad141 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/accessor.h @@ -0,0 +1,79 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + accessor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename accessor.h */ +/* This is the interface file for synchronous process 'accessor' */ + +#include "common.h" + +SC_MODULE( accessor ) +{ + SC_HAS_PROCESS( accessor ); + + sc_in_clk clk; + + const signal_bool_vector32& datain; //input + sc_signal<bool>& chip_select; //output + sc_signal<bool>& write_enable; //output + signal_bool_vector10& address; //output + signal_bool_vector32& dataout; //output + + // Parameter + const int memory_latency; + + //Constructor + accessor(sc_module_name NAME, + sc_clock& CLK, + const signal_bool_vector32& DATAIN, + sc_signal<bool>& CHIP_SELECT, + sc_signal<bool>& WRITE_ENABLE, + signal_bool_vector10& ADDRESS, + signal_bool_vector32& DATAOUT, + const int MEMORY_LATENCY = 1) + : datain(DATAIN), chip_select(CHIP_SELECT), + write_enable(WRITE_ENABLE), address(ADDRESS), dataout(DATAOUT), + memory_latency(MEMORY_LATENCY) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + // Process functionality in member function below + void entry(); +}; + + diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt12.2/chpt12.2.f b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/chpt12.2.f new file mode 100644 index 000000000..b0f5c4a21 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/chpt12.2.f @@ -0,0 +1,3 @@ +chpt12.2/accessor.cpp +chpt12.2/main.cpp +chpt12.2/ram.cpp diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt12.2/common.h b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/common.h new file mode 100644 index 000000000..5bdfda659 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/common.h @@ -0,0 +1,46 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + common.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#ifndef COMMON_H +#define COMMON_H + +#include "systemc.h" + +typedef sc_signal<sc_bv<10> > signal_bool_vector10; +typedef sc_signal<sc_bv<32> > signal_bool_vector32; + +#endif diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt12.2/golden/chpt12.2.log b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/golden/chpt12.2.log new file mode 100644 index 000000000..6ac89b345 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/golden/chpt12.2.log @@ -0,0 +1,18 @@ +SystemC Simulation +Accessor: Data Written = deadbeef at address a +Accessor: Data Read = deadbeef from address a +Accessor: Data Written = deadbef0 at address b +Accessor: Data Read = deadbef0 from address b +Accessor: Data Written = deadbef1 at address c +Accessor: Data Read = deadbef1 from address c +Accessor: Data Written = deadbef2 at address d +Accessor: Data Read = deadbef2 from address d +Accessor: Data Written = deadbef3 at address e +Accessor: Data Read = deadbef3 from address e +Accessor: Data Written = deadbef4 at address f +Accessor: Data Read = deadbef4 from address f +Accessor: Data Written = deadbef5 at address 10 +Accessor: Data Read = deadbef5 from address 10 +Accessor: Data Written = deadbef6 at address 11 +Accessor: Data Read = deadbef6 from address 11 +Accessor: Data Written = deadbef7 at address 12 diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt12.2/main.cpp b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/main.cpp new file mode 100644 index 000000000..148ed84db --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/main.cpp @@ -0,0 +1,59 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Main file for memory simulation */ + +#include "accessor.h" +#include "ram.h" + +int sc_main(int ac, char *av[]) +{ + sc_signal<bool> cs("CS"); + sc_signal<bool> we("WE"); + signal_bool_vector10 addr("Address"); + signal_bool_vector32 data1("Data1"); + signal_bool_vector32 data2("Data2"); + const int delay_cycles = 2; + + sc_clock clk("Clock", 20, SC_NS, 0.5, 0.0, SC_NS); + + accessor A("Accessor", clk, data1, cs, we, addr, data2, delay_cycles); + ram R("Ram", clk, data2, cs, we, addr, data1, delay_cycles); + + sc_start(1060, SC_NS); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt12.2/ram.cpp b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/ram.cpp new file mode 100644 index 000000000..2aa9a5c47 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/ram.cpp @@ -0,0 +1,62 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + ram.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename ram.cc */ +/* This is the implementation file for asynchronous process `ram' */ + +#include "ram.h" + +void ram::entry() +{ + int address; + + while (true) { + do { wait(); } while (cs != true); + address = addr.read().to_int(); + if (we.read() == true) { // Write operation + wait(wait_cycles-1); + memory[address] = datain.read().to_int(); + } + else { // Read operation + if (wait_cycles > 2) + wait(wait_cycles-2); // Introduce delay needed + dataout.write(memory[address]); + wait(); + } + } +} // end of entry function + diff --git a/src/systemc/tests/systemc/misc/user_guide/chpt12.2/ram.h b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/ram.h new file mode 100644 index 000000000..f1b3b824b --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/chpt12.2/ram.h @@ -0,0 +1,81 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + ram.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename ram.h */ +/* This is the interface file for synchronous process 'ram' */ + +#include "common.h" + +SC_MODULE( ram ) +{ + SC_HAS_PROCESS( ram ); + + sc_in_clk clk; + + const signal_bool_vector32& datain; //input + const sc_signal<bool>& cs; //input + const sc_signal<bool>& we; //input + const signal_bool_vector10& addr; //input + signal_bool_vector32& dataout; //output + + // Internal variable + int memory[4000]; + + // Parameter + const int wait_cycles; // Number of cycles it takes to access memory + + //Constructor + ram(sc_module_name NAME, + sc_clock& TICK, + const signal_bool_vector32& DATAIN, + const sc_signal<bool>& CS, + const sc_signal<bool>& WE, + const signal_bool_vector10& ADDR, + signal_bool_vector32& DATAOUT, + const int WAIT_CYCLES = 1) + : datain(DATAIN), cs(CS), we(WE), + addr(ADDR), dataout(DATAOUT), wait_cycles(WAIT_CYCLES) + { + clk(TICK); + SC_CTHREAD( entry, clk.pos() ); + } + + // Process functionality in member function below + void entry(); +}; + + |