diff options
Diffstat (limited to 'src/systemc/tests/systemc/misc/user_guide/newsched')
16 files changed, 1783 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test1/golden/test1.log b/src/systemc/tests/systemc/misc/user_guide/newsched/test1/golden/test1.log new file mode 100644 index 000000000..102bd3432 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test1/golden/test1.log @@ -0,0 +1,38 @@ +SystemC Simulation + +Info: (I703) tracing timescale unit set: 1 ns (systemc.vcd) +Seen other edge +AsyncBlock: Value read = 0 +AsyncProc: Value read = 0 +Seen other edge +AsyncBlock: Value read = 100 +Sync: Value written = 100 value1 read = 0 value2 read = 0 +AsyncProc: Value read = 100 +Seen other edge +AsyncBlock: Value read = 100 +Waited one cycle + +AsyncProc: Value read = 100 +Seen other edge +AsyncBlock: Value read = 101 +Sync: Value written = 101 value1 read = 100 value2 read = 100 +AsyncProc: Value read = 101 +Seen other edge +AsyncBlock: Value read = 101 +Waited one cycle + +AsyncProc: Value read = 101 +Seen other edge +AsyncBlock: Value read = 102 +Sync: Value written = 102 value1 read = 101 value2 read = 101 +AsyncProc: Value read = 102 +Seen other edge +AsyncBlock: Value read = 102 +Waited one cycle + +AsyncProc: Value read = 102 +Seen other edge +AsyncBlock: Value read = 103 +Sync: Value written = 103 value1 read = 102 value2 read = 102 +AsyncProc: Value read = 103 +Seen other edge diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test1/test1.cpp b/src/systemc/tests/systemc/misc/user_guide/newsched/test1/test1.cpp new file mode 100644 index 000000000..101387b96 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test1/test1.cpp @@ -0,0 +1,176 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test1.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Corner case testing for new scheduler. + Case 1. Checking triggering of a sc_async/sc_aproc + vis-a-vis a synchronous process. + This test checks to ensure that a synch. and async. sensitive + to a clock are triggered correctly. + */ + +#include "systemc.h" + +SC_MODULE( syncproc ) +{ + SC_HAS_PROCESS( syncproc ); + + sc_in<bool> clk; + + const sc_signal<int>& in1; + const sc_signal<int>& in2; + sc_signal<int>& out; + + syncproc(sc_module_name NAME, + sc_signal_in_if<bool>& CLK, + const sc_signal<int>& IN1, + const sc_signal<int>& IN2, + sc_signal<int>& OUT_) + : in1(IN1), in2(IN2), out(OUT_) + { + SC_CTHREAD( entry, clk.pos() ); + clk(CLK); + out = 0; + } + + void entry() + { + int i = 100; + while (true) { + out = i; + wait(); + while (in1.read() != i) { + cout << "Sync: Value written = " << i << " value1 read = " << in1.read() << " value2 read = " << in2.read() << endl; + wait(); + cout << "Waited one cycle\n" << endl; + } + i++; + } + } +}; + +SC_MODULE( asyncproc ) +{ + SC_HAS_PROCESS( asyncproc ); + + const sc_signal<int>& in; + sc_signal<int>& out; + sc_in<bool> clock; + + asyncproc(sc_module_name NAME, + const sc_signal<int>& IN_, + sc_signal<int>& OUT_, + sc_signal_in_if<bool>& CLOCK) + : in(IN_), out(OUT_) + { + out = 0; + clock(CLOCK); + SC_THREAD( entry ); + sensitive << clock.pos(); + } + + void entry() + { + wait(); + while (true) { + if (clock.posedge()) { + out = in; + cout << "AsyncProc: Value read = " << in.read() << endl; + } + else { + cout << "Error" << endl; + } + wait(); + } + } +}; + +SC_MODULE( asyncblock ) +{ + SC_HAS_PROCESS( asyncblock ); + + const sc_signal<int>& in; + sc_signal<int>& out; + sc_in<bool> clock; + + asyncblock(sc_module_name NAME, + const sc_signal<int>& IN_, + sc_signal<int>& OUT_, + sc_signal_in_if<bool>& CLOCK) + : in(IN_), out(OUT_) + { + clock(CLOCK); + out = 0; + SC_METHOD( entry ); + sensitive << clock; + } + + void entry() + { + if (clock.posedge()) { + out = in; + cout << "AsyncBlock: Value read = " << in.read() << endl; + } + else { + cout << "Seen other edge" << endl; + } + } +}; + + +int +sc_main(int ac, char *av[]) +{ + sc_signal<int> a, b, c; + + sc_clock clock("Clock", 20, SC_NS, 0.5); + + syncproc P1("P1", clock, a, b, c); + asyncproc P2("P2", c, a, clock); + asyncblock P3("P3", c, b, clock); + + sc_trace_file *tf = sc_create_vcd_trace_file("systemc"); + tf->set_time_unit(1, SC_NS); + sc_trace(tf, a, "SYNC-IN1"); + sc_trace(tf, b, "SYNC-IN2"); + sc_trace(tf, c, "SYNC2-OUT"); + sc_trace(tf, clock, "Clock"); + + sc_start(160, SC_NS); + return 0; + +} diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test2/golden/test2.log b/src/systemc/tests/systemc/misc/user_guide/newsched/test2/golden/test2.log new file mode 100644 index 000000000..33f68dce4 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test2/golden/test2.log @@ -0,0 +1,34 @@ +SystemC Simulation + +Info: (I703) tracing timescale unit set: 1 ns (systemc.vcd) +Seen other edge +AsyncBlock: Value read = 0 +AsyncProc: Value read = 100 +Seen other edge +AsyncBlock: Value read = 100 +Sync: Value written = 100 value1 read = 110 value2 read = 0 +Seen other edge +AsyncBlock: Value read = 100 +Waited one cycle + +AsyncProc: Value read = 101 +Seen other edge +AsyncBlock: Value read = 101 +Sync: Value written = 101 value1 read = 111 value2 read = 100 +Seen other edge +AsyncBlock: Value read = 101 +Waited one cycle + +AsyncProc: Value read = 102 +Seen other edge +AsyncBlock: Value read = 102 +Sync: Value written = 102 value1 read = 112 value2 read = 101 +Seen other edge +AsyncBlock: Value read = 102 +Waited one cycle + +AsyncProc: Value read = 103 +Seen other edge +AsyncBlock: Value read = 103 +Sync: Value written = 103 value1 read = 113 value2 read = 102 +Seen other edge diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test2/test2.cpp b/src/systemc/tests/systemc/misc/user_guide/newsched/test2/test2.cpp new file mode 100644 index 000000000..8b6201c96 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test2/test2.cpp @@ -0,0 +1,170 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test2.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Corner case testing for new scheduler. + Case 2: Checking single cycle interaction between + sc_sync and async, in conjunction with triggering of + sc_sync and async that are sensitive to a clock + */ + +#include "systemc.h" + +SC_MODULE( syncproc ) +{ + SC_HAS_PROCESS( syncproc ); + + sc_in<bool> clk; + + const sc_signal<int>& in1; + const sc_signal<int>& in2; + sc_signal<int>& out; + + syncproc(sc_module_name NAME, + sc_signal_in_if<bool>& CLK, + const sc_signal<int>& IN1, + const sc_signal<int>& IN2, + sc_signal<int>& OUT_) + : in1(IN1), in2(IN2), out(OUT_) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + out = 0; + } + + void entry() + { + int i = 100; + while (true) { + out = i; + wait(); + while (in2.read() != i) { + cout << "Sync: Value written = " << i << " value1 read = " << in1.read() << " value2 read = " << in2.read() << endl; + wait(); + cout << "Waited one cycle\n" << endl; + } + i++; + } + } +}; + +SC_MODULE( asyncproc ) +{ + SC_HAS_PROCESS( asyncproc ); + + const sc_signal<int>& in; + sc_signal<int>& out; + sc_in<bool> clock; + + asyncproc(sc_module_name NAME, + const sc_signal<int>& IN_, + sc_signal<int>& OUT_, + sc_signal_in_if<bool>& CLOCK) + : in(IN_), out(OUT_) + { + clock(CLOCK); + out = 0; + SC_THREAD( entry ); + sensitive << in; + } + + void entry() + { + wait(); + while (true) { + out = in + 10; + cout << "AsyncProc: Value read = " << in.read() << endl; + wait(); + } + } +}; + +SC_MODULE( asyncblock ) +{ + SC_HAS_PROCESS( asyncblock ); + + const sc_signal<int>& in; + sc_signal<int>& out; + sc_in<bool> clock; + + asyncblock(sc_module_name NAME, + const sc_signal<int>& IN_, + sc_signal<int>& OUT_, + sc_signal_in_if<bool>& CLOCK) + : in(IN_), out(OUT_) + { + clock(CLOCK); + out = 0; + SC_METHOD( entry ); + sensitive << clock; + } + + void entry() + { + if (clock.posedge()) { + out = in; + cout << "AsyncBlock: Value read = " << in.read() << endl; + } + else { + cout << "Seen other edge" << endl; + } + } +}; + + +int +sc_main(int ac, char *av[]) +{ + sc_signal<int> a, b, c; + + sc_clock clock("Clock", 20, SC_NS, 0.5); + + syncproc P1("P1", clock, a, b, c); + asyncproc P2("P2", c, a, clock); + asyncblock P3("P3", c, b, clock); + + sc_trace_file *tf = sc_create_vcd_trace_file("systemc"); + tf->set_time_unit(1, SC_NS); + sc_trace(tf, a, "SYNC-IN1"); + sc_trace(tf, b, "SYNC-IN2"); + sc_trace(tf, c, "SYNC2-OUT"); + sc_trace(tf, clock, "Clock"); + + sc_start(160, SC_NS); + return 0; + +} diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test3/golden/test3.log b/src/systemc/tests/systemc/misc/user_guide/newsched/test3/golden/test3.log new file mode 100644 index 000000000..694dcb348 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test3/golden/test3.log @@ -0,0 +1,18 @@ +SystemC Simulation +AsyncBlock: Negedge +AsyncProc: Posedge +AsyncBlock: Negedge +AsyncProc: Posedge +AsyncBlock: Negedge +AsyncProc: Posedge +AsyncBlock: Negedge +AsyncProc: Posedge +AsyncBlock: Negedge +AsyncProc: Posedge +AsyncBlock: Negedge +AsyncProc: Posedge +AsyncBlock: Negedge +AsyncProc: Posedge +AsyncBlock: Negedge +AsyncProc: Posedge +AsyncBlock: Negedge diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test3/test3.cpp b/src/systemc/tests/systemc/misc/user_guide/newsched/test3/test3.cpp new file mode 100644 index 000000000..eda07c614 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test3/test3.cpp @@ -0,0 +1,111 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test3.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Corner case testing for new scheduler. + Case 3: Checking sensitive_pos() and sensitive_neg() methods +*/ + +#include "systemc.h" + +SC_MODULE( asyncproc ) +{ + SC_HAS_PROCESS( asyncproc ); + + sc_in<bool> clock; + + asyncproc(sc_module_name NAME, + sc_signal_in_if<bool>& CLOCK) + { + clock(CLOCK); + SC_THREAD( entry ); + sensitive << clock.pos(); + } + + void entry() + { + wait(); + while (true) { + if (clock.posedge()) { + cout << "AsyncProc: Posedge\n"; + } + else { + cout << "AsyncProc: ERROR" << endl; + } + wait(); + } + } +}; + +SC_MODULE( asyncblock ) +{ + SC_HAS_PROCESS( asyncblock ); + + sc_in<bool> clock; + + asyncblock(sc_module_name NAME, + sc_signal_in_if<bool>& CLOCK) + { + clock(CLOCK); + SC_METHOD( entry ); + sensitive << clock.neg(); + } + + void entry() + { + if (clock.posedge()) { + cout << "AsyncBlock: ERROR\n"; + } + else { + cout << "AsyncBlock: Negedge" << endl; + } + } +}; + + +int +sc_main(int ac, char *av[]) +{ + sc_clock clock("Clock", 20, SC_NS, 0.5); + + asyncproc P2("P2", clock); + asyncblock P3("P3", clock); + + sc_start(160, SC_NS); + return 0; + +} diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test4/golden/test4.log b/src/systemc/tests/systemc/misc/user_guide/newsched/test4/golden/test4.log new file mode 100644 index 000000000..c4c8ca893 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test4/golden/test4.log @@ -0,0 +1,121 @@ +SystemC Simulation +[ Gate = 1 - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 11 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 12 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 13 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 14 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Gate = 1 - ] +[ Posedge(D) - ] +[ A = 15 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 16 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 17 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 18 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Gate = 1 - ] +[ Posedge(D) - ] +[ A = 19 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 20 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 21 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 22 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Gate = 1 - ] +[ Posedge(D) - ] +[ A = 23 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 24 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 25 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 26 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Gate = 1 - ] +[ Posedge(D) - ] +[ A = 27 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 28 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 29 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 30 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test4/test4.cpp b/src/systemc/tests/systemc/misc/user_guide/newsched/test4/test4.cpp new file mode 100644 index 000000000..f9d97063f --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test4/test4.cpp @@ -0,0 +1,199 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test4.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Corner case testing for new scheduler. + Case 4: Checking gated clocks and triggering of processes + */ + +#include "systemc.h" + +SC_MODULE( cgater ) +{ + SC_HAS_PROCESS( cgater ); + + const sc_signal<bool>& gate; + sc_in<bool> clock_in; + sc_out<bool> clock_out; + + cgater(sc_module_name NAME, + const sc_signal<bool>& GATE, + sc_signal_in_if<bool>& CLOCK_IN, + sc_signal_out_if<bool>& CLOCK_OUT) + : gate(GATE) + { + clock_in(CLOCK_IN); + clock_out(CLOCK_OUT); + SC_METHOD( entry ); + sensitive << gate; + sensitive << clock_in; + } + + void entry() + { + clock_out = clock_in & gate; + } +}; + +SC_MODULE( watcher ) +{ + SC_HAS_PROCESS( watcher ); + + const sc_signal<bool>& gate; + sc_in<bool> clock; + sc_in<bool> dclock; + const sc_signal<int>& a; + + watcher(sc_module_name NAME, + const sc_signal<bool>& GATE, + sc_signal_in_if<bool>& CLOCK, + sc_signal_in_if<bool>& DCLOCK, + const sc_signal<int>& A) + : gate(GATE), a(A) + { + clock(CLOCK); + dclock(DCLOCK); + SC_METHOD( entry ); + sensitive << clock; + sensitive << a; + sensitive << gate; + sensitive << dclock; + } + + void entry() + { + cout << "[ "; + if (clock.posedge()) cout << "Posedge - "; + if (clock.negedge()) cout << "Negedge - "; + if (dclock.posedge()) cout << "Posedge(D) - "; + if (dclock.negedge()) cout << "Negedge(D) - "; + if (a.event()) cout << "A = " << a.read() << " - "; + if (gate.event()) cout << "Gate = " << gate.read() << " - "; + cout << "]" << endl; + } +}; + + +SC_MODULE( gategen ) +{ + SC_HAS_PROCESS( gategen ); + + sc_in<bool> clk; + + sc_signal<bool>& gate; + + gategen(sc_module_name NAME, + sc_signal_in_if<bool>& CLK, + sc_signal<bool>& GATE) + : gate(GATE) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + gate = 1; + } + + void entry() + { + while (true) { + gate = 1; wait(3); + gate = 0; wait (3); + } + } +}; + +SC_MODULE( trigp ) +{ + SC_HAS_PROCESS( trigp ); + + sc_in<bool> clk; + + sc_signal<int>& out; + + trigp(sc_module_name NAME, + sc_signal_in_if<bool>& CLK, + sc_signal<int>& OUT_) + : out(OUT_) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + out = 0; + } + + void entry() + { + int i = 11; + while (true) { + out = i++; + wait(); + } + } +}; + +int +sc_main(int ac, char *av[]) +{ + // sc_clock clock1("Clock1", 20, SC_NS, 0.5); + // sc_clock dclock("Derived"); + sc_signal<bool> clock1( "Clock1" ); + sc_signal<bool> dclock( "Derived" ); + + sc_signal<bool> Gate; + sc_signal<int> Output; + + cgater CG("CG", Gate, clock1, dclock); + watcher W("W", Gate, clock1, dclock, Output); + gategen G("G", clock1, Gate); + trigp T("T", dclock, Output); + + sc_trace_file *tf = sc_create_vcd_trace_file("systemc"); + sc_trace(tf, clock1, "Clock"); + sc_trace(tf, dclock, "Dclock"); + sc_trace(tf, Gate, "Gate"); + sc_trace(tf, Output, "Out"); + + sc_start(0, SC_NS); + clock1.write(0); + sc_start(5, SC_NS); + for (int i=0; i < 30; i++) { + clock1.write(1); + sc_start(5, SC_NS); + clock1.write(0); + sc_start(5, SC_NS); + } + + return 0; +} diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test5/golden/test5.log b/src/systemc/tests/systemc/misc/user_guide/newsched/test5/golden/test5.log new file mode 100644 index 000000000..c4c8ca893 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test5/golden/test5.log @@ -0,0 +1,121 @@ +SystemC Simulation +[ Gate = 1 - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 11 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 12 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 13 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 14 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Gate = 1 - ] +[ Posedge(D) - ] +[ A = 15 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 16 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 17 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 18 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Gate = 1 - ] +[ Posedge(D) - ] +[ A = 19 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 20 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 21 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 22 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Gate = 1 - ] +[ Posedge(D) - ] +[ A = 23 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 24 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 25 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 26 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Gate = 1 - ] +[ Posedge(D) - ] +[ A = 27 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 28 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - ] +[ A = 29 - ] +[ Negedge - ] +[ Negedge(D) - ] +[ Posedge - ] +[ Posedge(D) - Gate = 0 - ] +[ Negedge(D) - A = 30 - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] +[ Posedge - ] +[ Negedge - ] diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test5/test5.cpp b/src/systemc/tests/systemc/misc/user_guide/newsched/test5/test5.cpp new file mode 100644 index 000000000..2338cde83 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test5/test5.cpp @@ -0,0 +1,189 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test5.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Corner case testing for new scheduler. + Case 4: Checking gated clocks and triggering of processes + */ + +#include "systemc.h" + +SC_MODULE( cgater ) +{ + SC_HAS_PROCESS( cgater ); + + const sc_signal<bool>& gate; + sc_in<bool> clock_in; + sc_out<bool> clock_out; + + cgater(sc_module_name NAME, + const sc_signal<bool>& GATE, + sc_signal_in_if<bool>& CLOCK_IN, + sc_signal_out_if<bool>& CLOCK_OUT) + : gate(GATE) + { + clock_in(CLOCK_IN); + clock_out(CLOCK_OUT); + SC_METHOD( entry ); + sensitive << gate; + sensitive << clock_in; + } + + void entry() + { + clock_out = clock_in & gate; + } +}; + +SC_MODULE( watcher ) +{ + SC_HAS_PROCESS( watcher ); + + const sc_signal<bool>& gate; + sc_in<bool> clock; + sc_in<bool> dclock; + const sc_signal<int>& a; + + watcher(sc_module_name NAME, + const sc_signal<bool>& GATE, + sc_signal_in_if<bool>& CLOCK, + sc_signal_in_if<bool>& DCLOCK, + const sc_signal<int>& A) + : gate(GATE), a(A) + { + clock(CLOCK); + dclock(DCLOCK); + SC_METHOD( entry ); + sensitive << clock; + sensitive << a; + sensitive << gate; + sensitive << dclock; + } + + void entry() + { + cout << "[ "; + if (clock.posedge()) cout << "Posedge - "; + if (clock.negedge()) cout << "Negedge - "; + if (dclock.posedge()) cout << "Posedge(D) - "; + if (dclock.negedge()) cout << "Negedge(D) - "; + if (a.event()) cout << "A = " << a.read() << " - "; + if (gate.event()) cout << "Gate = " << gate.read() << " - "; + cout << "]" << endl; + } +}; + + +SC_MODULE( gategen ) +{ + SC_HAS_PROCESS( gategen ); + + sc_in<bool> clk; + + sc_signal<bool>& gate; + + gategen(sc_module_name NAME, + sc_signal_in_if<bool>& CLK, + sc_signal<bool>& GATE) + : gate(GATE) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + gate = 1; + } + + void entry() + { + while (true) { + gate = 1; wait(3); + gate = 0; wait (3); + } + } +}; + +SC_MODULE( trigp ) +{ + SC_HAS_PROCESS( trigp ); + + sc_in<bool> clk; + + sc_signal<int>& out; + + trigp(sc_module_name NAME, + sc_signal_in_if<bool>& CLK, + sc_signal<int>& OUT_) + : out(OUT_) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + out = 0; + } + + void entry() + { + int i = 11; + while (true) { + out = i++; + wait(); + } + } +}; + +int +sc_main(int ac, char *av[]) +{ + sc_clock clock1("Clock1", 20, SC_NS, 0.5); + // sc_clock dclock("Derived", -1); + sc_signal<bool> dclock( "Derived" ); + + sc_signal<bool> Gate; + sc_signal<int> Output; + + cgater CG("CG", Gate, clock1, dclock); + watcher W("W", Gate, clock1, dclock, Output); + gategen G("G", clock1, Gate); + trigp T("T", dclock, Output); + + sc_trace_file *tf = sc_create_vcd_trace_file("systemc"); + sc_trace(tf, clock1, "Clock"); + sc_trace(tf, dclock, "Dclock"); + sc_trace(tf, Gate, "Gate"); + sc_trace(tf, Output, "Out"); + + sc_start(600, SC_NS); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test6/golden/test6.log b/src/systemc/tests/systemc/misc/user_guide/newsched/test6/golden/test6.log new file mode 100644 index 000000000..8b5d0ffef --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test6/golden/test6.log @@ -0,0 +1,22 @@ +SystemC Simulation +[ ] +[ Posedge(1) - Posedge(2) - ASync1 Out = 1 - ASync2 Out = 1 - ] +[ Sync1 Out = 11 - ASync1 Out = 2 - Sync2 Out = 11 - ASync2 Out = 2 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 3 - ASync2 Out = 3 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 12 - ASync1 Out = 4 - Sync2 Out = 12 - ASync2 Out = 4 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 5 - ASync2 Out = 5 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 13 - ASync1 Out = 6 - Sync2 Out = 13 - ASync2 Out = 6 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 7 - ASync2 Out = 7 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 14 - ASync1 Out = 8 - Sync2 Out = 14 - ASync2 Out = 8 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 9 - ASync2 Out = 9 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 15 - ASync1 Out = 10 - Sync2 Out = 15 - ASync2 Out = 10 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 11 - ASync2 Out = 11 - ] diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test6/test6.cpp b/src/systemc/tests/systemc/misc/user_guide/newsched/test6/test6.cpp new file mode 100644 index 000000000..a1446e8aa --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test6/test6.cpp @@ -0,0 +1,165 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test6.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Corner case testing for new scheduler. + Case 5: Checking multiple clock transitions at the same time + */ + +#include "systemc.h" + +SC_MODULE( triga ) +{ + SC_HAS_PROCESS( triga ); + + sc_in<bool> clock; + sc_signal<int>& out; + + int i; + + triga(sc_module_name NAME, + sc_signal_in_if<bool>& CLOCK, + sc_signal<int>& OUT_) + : out(OUT_) + { + clock(CLOCK); + SC_METHOD( entry ); + sensitive << clock; + i = 0; + out = i++; + } + + void entry() + { + out = i++; + } +}; + +SC_MODULE( watcher ) +{ + SC_HAS_PROCESS( watcher ); + + sc_in<bool> clock1; + sc_in<bool> clock2; + const sc_signal<int>& in1; + const sc_signal<int>& in2; + const sc_signal<int>& in3; + const sc_signal<int>& in4; + + watcher(sc_module_name NAME, + sc_signal_in_if<bool>& CLOCK1, + sc_signal_in_if<bool>& CLOCK2, + const sc_signal<int>& IN1, + const sc_signal<int>& IN2, + const sc_signal<int>& IN3, + const sc_signal<int>& IN4) + : in1(IN1), in2(IN2), in3(IN3), in4(IN4) + { + clock1(CLOCK1); clock2(CLOCK2); + SC_METHOD( entry ); + sensitive << clock1 << clock2 << in1 << in2 << in3 << in4; + } + + void entry() + { + cout << "[ "; + if (clock1.posedge()) cout << "Posedge(1) - "; + if (clock1.negedge()) cout << "Negedge(1) - "; + if (clock2.posedge()) cout << "Posedge(2) - "; + if (clock2.negedge()) cout << "Negedge(2) - "; + if (in1.event()) cout << "Sync1 Out = " << in1.read() << " - "; + if (in2.event()) cout << "ASync1 Out = " << in2.read() << " - "; + if (in3.event()) cout << "Sync2 Out = " << in3.read() << " - "; + if (in4.event()) cout << "ASync2 Out = " << in4.read() << " - "; + cout << "]" << endl; + } +}; + + +SC_MODULE( trigp ) +{ + SC_HAS_PROCESS( trigp ); + + sc_in<bool> clk; + + sc_signal<int>& out; + + trigp(sc_module_name NAME, + sc_signal_in_if<bool>& CLK, + sc_signal<int>& OUT_) + : out(OUT_) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + out = 0; + } + + void entry() + { + int i = 11; + while (true) { + out = i++; + wait(); + } + } +}; + +int +sc_main(int ac, char *av[]) +{ + sc_clock clock1("Clock1", 20, SC_NS, 0.5); + sc_clock clock2("Clock2", 20, SC_NS, 0.5); + + sc_signal<int> sig1, sig2, sig3, sig4; + + triga T1("T1", clock1, sig2); + triga T2("T2", clock2, sig4); + trigp T3("T3", clock1, sig1); + trigp T4("T4", clock2, sig3); + watcher W("W", clock1, clock2, sig1, sig2, sig3, sig4); + + sc_trace_file *tf = sc_create_vcd_trace_file("systemc"); + sc_trace(tf, clock1, "Clock1"); + sc_trace(tf, clock2, "Clock2"); + sc_trace(tf, sig1, "Sync1"); + sc_trace(tf, sig2, "Async1"); + sc_trace(tf, sig3, "Sync2"); + sc_trace(tf, sig4, "Async2"); + + sc_start(100, SC_NS); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test7/golden/test7.log b/src/systemc/tests/systemc/misc/user_guide/newsched/test7/golden/test7.log new file mode 100644 index 000000000..be038115a --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test7/golden/test7.log @@ -0,0 +1,22 @@ +SystemC Simulation +[ ] +[ Posedge(1) - Posedge(2) - ASync1 Out = 1 - ASync2 Out = 1 - ] +[ Sync1 Out = 11 - ASync1 Out = 2 - Sync2 Out = 11 - ASync2 Out = 2 - ] +[ Negedge(1) - ] +[ ASync1 Out = 3 - ] +[ Posedge(1) - Negedge(2) - ] +[ Sync1 Out = 12 - ASync1 Out = 4 - ASync2 Out = 3 - ] +[ Negedge(1) - ] +[ ASync1 Out = 5 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 13 - ASync1 Out = 6 - Sync2 Out = 12 - ASync2 Out = 4 - ] +[ Negedge(1) - ] +[ ASync1 Out = 7 - ] +[ Posedge(1) - Negedge(2) - ] +[ Sync1 Out = 14 - ASync1 Out = 8 - ASync2 Out = 5 - ] +[ Negedge(1) - ] +[ ASync1 Out = 9 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 15 - ASync1 Out = 10 - Sync2 Out = 13 - ASync2 Out = 6 - ] +[ Negedge(1) - ] +[ ASync1 Out = 11 - ] diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test7/test7.cpp b/src/systemc/tests/systemc/misc/user_guide/newsched/test7/test7.cpp new file mode 100644 index 000000000..a9bc31693 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test7/test7.cpp @@ -0,0 +1,167 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test7.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* + Corner case testing for new scheduler. + Case 5: Checking multiple clock transitions at the same time + */ + +#include "systemc.h" + +SC_MODULE( triga ) +{ + SC_HAS_PROCESS( triga ); + + sc_in<bool> clock; + sc_signal<int>& out; + + int i; + + triga(sc_module_name NAME, + sc_signal_in_if<bool>& CLOCK, + sc_signal<int>& OUT_) + : out(OUT_) + { + clock(CLOCK); + SC_METHOD( entry ); + sensitive << clock; + i = 0; + out = i++; + } + + void entry() + { + out = i++; + } +}; + +SC_MODULE( watcher ) +{ + SC_HAS_PROCESS( watcher ); + + sc_in<bool> clock1; + sc_in<bool> clock2; + const sc_signal<int>& in1; + const sc_signal<int>& in2; + const sc_signal<int>& in3; + const sc_signal<int>& in4; + + watcher(sc_module_name NAME, + sc_signal_in_if<bool>& CLOCK1, + sc_signal_in_if<bool>& CLOCK2, + const sc_signal<int>& IN1, + const sc_signal<int>& IN2, + const sc_signal<int>& IN3, + const sc_signal<int>& IN4) + : in1(IN1), in2(IN2), in3(IN3), in4(IN4) + { + clock1(CLOCK1); + clock2(CLOCK2); + SC_METHOD( entry ); + sensitive << clock1 << clock2; + sensitive << in1 << in2 << in3 << in4; + } + + void entry() + { + cout << "[ "; + if (clock1.posedge()) cout << "Posedge(1) - "; + if (clock1.negedge()) cout << "Negedge(1) - "; + if (clock2.posedge()) cout << "Posedge(2) - "; + if (clock2.negedge()) cout << "Negedge(2) - "; + if (in1.event()) cout << "Sync1 Out = " << in1.read() << " - "; + if (in2.event()) cout << "ASync1 Out = " << in2.read() << " - "; + if (in3.event()) cout << "Sync2 Out = " << in3.read() << " - "; + if (in4.event()) cout << "ASync2 Out = " << in4.read() << " - "; + cout << "]" << endl; + } +}; + + +SC_MODULE( trigp ) +{ + SC_HAS_PROCESS( trigp ); + + sc_in<bool> clk; + + sc_signal<int>& out; + + trigp(sc_module_name NAME, + sc_signal_in_if<bool>& CLK, + sc_signal<int>& OUT_) + : out(OUT_) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + out = 0; + } + + void entry() + { + int i = 11; + while (true) { + out = i++; + wait(); + } + } +}; + +int +sc_main(int ac, char *av[]) +{ + sc_clock clock1("Clock1", 20, SC_NS, 0.5); + sc_clock clock2("Clock2", 40, SC_NS, 0.5); + + sc_signal<int> sig1, sig2, sig3, sig4; + + triga T1("T1", clock1, sig2); + triga T2("T2", clock2, sig4); + trigp T3("T3", clock1, sig1); + trigp T4("T4", clock2, sig3); + watcher W("W", clock1, clock2, sig1, sig2, sig3, sig4); + + sc_trace_file *tf = sc_create_vcd_trace_file("systemc"); + sc_trace(tf, clock1, "Clock1"); + sc_trace(tf, clock2, "Clock2"); + sc_trace(tf, sig1, "Sync1"); + sc_trace(tf, sig2, "Async1"); + sc_trace(tf, sig3, "Sync2"); + sc_trace(tf, sig4, "Async2"); + + sc_start(100, SC_NS); + return 0; +} diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test8/golden/test8.log b/src/systemc/tests/systemc/misc/user_guide/newsched/test8/golden/test8.log new file mode 100644 index 000000000..33a2eacbf --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test8/golden/test8.log @@ -0,0 +1,43 @@ +SystemC Simulation +[ ] +[ ASync1 Out = 1 - ASync2 Out = 1 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 11 - ASync1 Out = 2 - Sync2 Out = 11 - ASync2 Out = 2 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 3 - ASync2 Out = 3 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 12 - ASync1 Out = 4 - Sync2 Out = 12 - ASync2 Out = 4 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 5 - ASync2 Out = 5 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 13 - ASync1 Out = 6 - Sync2 Out = 13 - ASync2 Out = 6 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 7 - ASync2 Out = 7 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 14 - ASync1 Out = 8 - Sync2 Out = 14 - ASync2 Out = 8 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 9 - ASync2 Out = 9 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 15 - ASync1 Out = 10 - Sync2 Out = 15 - ASync2 Out = 10 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 11 - ASync2 Out = 11 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 16 - ASync1 Out = 12 - Sync2 Out = 16 - ASync2 Out = 12 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 13 - ASync2 Out = 13 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 17 - ASync1 Out = 14 - Sync2 Out = 17 - ASync2 Out = 14 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 15 - ASync2 Out = 15 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 18 - ASync1 Out = 16 - Sync2 Out = 18 - ASync2 Out = 16 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 17 - ASync2 Out = 17 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 19 - ASync1 Out = 18 - Sync2 Out = 19 - ASync2 Out = 18 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 19 - ASync2 Out = 19 - ] +[ Posedge(1) - Posedge(2) - ] +[ Sync1 Out = 20 - ASync1 Out = 20 - Sync2 Out = 20 - ASync2 Out = 20 - ] +[ Negedge(1) - Negedge(2) - ] +[ ASync1 Out = 21 - ASync2 Out = 21 - ] diff --git a/src/systemc/tests/systemc/misc/user_guide/newsched/test8/test8.cpp b/src/systemc/tests/systemc/misc/user_guide/newsched/test8/test8.cpp new file mode 100644 index 000000000..9d4fe3d00 --- /dev/null +++ b/src/systemc/tests/systemc/misc/user_guide/newsched/test8/test8.cpp @@ -0,0 +1,187 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test8.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// $Log: test8.cpp,v $ +// Revision 1.1.1.1 2006/12/15 20:26:23 acg +// systemc_tests-2.3 +// +// Revision 1.2 2006/01/24 21:05:50 acg +// Andy Goodrich: replacement of deprecated features with their non-deprecated +// counterparts. +// + +/* + Corner case testing for new scheduler. + Case 5: Checking multiple clock transitions at the same time + */ + +#include "systemc.h" + +SC_MODULE( triga ) +{ + SC_HAS_PROCESS( triga ); + + sc_in<bool> clock; + sc_signal<int>& out; + + int i; + + triga(sc_module_name NAME, + sc_signal_in_if<bool>& CLOCK, + sc_signal<int>& OUT_) + : out(OUT_) + { + clock(CLOCK); + SC_METHOD( entry ); + sensitive << clock; + i = 0; + out = i++; + } + + void entry() + { + out = i++; + } +}; + +SC_MODULE( watcher ) +{ + SC_HAS_PROCESS( watcher ); + + sc_in<bool> clock1; + sc_in<bool> clock2; + const sc_signal<int>& in1; + const sc_signal<int>& in2; + const sc_signal<int>& in3; + const sc_signal<int>& in4; + + watcher(sc_module_name NAME, + sc_signal_in_if<bool>& CLOCK1, + sc_signal_in_if<bool>& CLOCK2, + const sc_signal<int>& IN1, + const sc_signal<int>& IN2, + const sc_signal<int>& IN3, + const sc_signal<int>& IN4) + : in1(IN1), in2(IN2), in3(IN3), in4(IN4) + { + clock1(CLOCK1); + clock2(CLOCK2); + SC_METHOD( entry ); + sensitive << clock1; sensitive << clock2; + sensitive << in1; sensitive << in2; sensitive << in3; sensitive << in4; + } + + void entry() + { + cout << "[ "; + if (clock1.posedge()) cout << "Posedge(1) - "; + if (clock1.negedge()) cout << "Negedge(1) - "; + if (clock2.posedge()) cout << "Posedge(2) - "; + if (clock2.negedge()) cout << "Negedge(2) - "; + if (in1.event()) cout << "Sync1 Out = " << in1.read() << " - "; + if (in2.event()) cout << "ASync1 Out = " << in2.read() << " - "; + if (in3.event()) cout << "Sync2 Out = " << in3.read() << " - "; + if (in4.event()) cout << "ASync2 Out = " << in4.read() << " - "; + cout << "]" << endl; + } +}; + + +SC_MODULE( trigp ) +{ + SC_HAS_PROCESS( trigp ); + + sc_in<bool> clk; + + sc_signal<int>& out; + + trigp(sc_module_name NAME, + sc_signal_in_if<bool>& CLK, + sc_signal<int>& OUT_) + : out(OUT_) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + out = 0; + } + + void entry() + { + int i = 11; + while (true) { + out = i++; + wait(); + } + } +}; + +int +sc_main(int ac, char *av[]) +{ + // sc_clock clock1("Clock1", 20, SC_NS, 0.5); + // sc_clock clock2("Clock2", 20, SC_NS, 0.5); + sc_signal<bool> clock1( "Clock1" ); + sc_signal<bool> clock2( "Clock2" ); + + sc_signal<int> sig1, sig2, sig3, sig4; + + triga T1("T1", clock1, sig2); + triga T2("T2", clock2, sig4); + trigp T3("T3", clock1, sig1); + trigp T4("T4", clock2, sig3); + watcher W("W", clock1, clock2, sig1, sig2, sig3, sig4); + + sc_trace_file *tf = sc_create_vcd_trace_file("systemc"); + sc_trace(tf, clock1, "Clock1"); + sc_trace(tf, clock2, "Clock2"); + sc_trace(tf, sig1, "Sync1"); + sc_trace(tf, sig2, "Async1"); + sc_trace(tf, sig3, "Sync2"); + sc_trace(tf, sig4, "Async2"); + + sc_start(0, SC_NS); + clock1 = 0; + clock2 = 0; + sc_start(5, SC_NS); + for (int i = 0; i< 10; i++) { + clock1 = 1; clock2 = 1; + sc_start(5, SC_NS); + clock1 = 0; clock2 = 0; + sc_start(5, SC_NS); + } + return 0; +} |