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-rw-r--r--src/systemc/tests/systemc/tracing/wif_trace/mixed/golden/mixed.awif462
-rw-r--r--src/systemc/tests/systemc/tracing/wif_trace/mixed/isaac.h272
-rw-r--r--src/systemc/tests/systemc/tracing/wif_trace/mixed/mixed.cpp129
3 files changed, 863 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/tracing/wif_trace/mixed/golden/mixed.awif b/src/systemc/tests/systemc/tracing/wif_trace/mixed/golden/mixed.awif
new file mode 100644
index 000000000..2444304f7
--- /dev/null
+++ b/src/systemc/tests/systemc/tracing/wif_trace/mixed/golden/mixed.awif
@@ -0,0 +1,462 @@
+
+type scalar "BIT" enum '0', '1' ;
+type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ;
+
+declare O0 "a" BIT 0 31 variable ;
+start_trace O0 ;
+declare O1 "b" BIT 0 31 variable ;
+start_trace O1 ;
+declare O2 "sum" BIT 0 31 variable ;
+start_trace O2 ;
+declare O3 "clk" BIT variable ;
+start_trace O3 ;
+comment "All initial values are dumped below at time 0 sec = 0 timescale units." ;
+assign O0 "00000000000000000000000011110011" ;
+assign O1 "00000000000000000100101010001101" ;
+assign O2 "00000000000000000000000000000000" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000110011000100010" ;
+assign O1 "00000000000000000100110100100001" ;
+assign O2 "00000000000000000100101110000000" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000101011001111001" ;
+assign O1 "00000000000000000000011011101001" ;
+assign O2 "00000000000000001011001101000011" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000010100010110101" ;
+assign O1 "00000000000000000001110000100100" ;
+assign O2 "00000000000000000101110101100010" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000001111110101111" ;
+assign O1 "00000000000000000001110111101111" ;
+assign O2 "00000000000000000100010011011001" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000100000111000010" ;
+assign O1 "00000000000000000001101011111011" ;
+assign O2 "00000000000000000011110110011110" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000011111101110100" ;
+assign O1 "00000000000000000011011100011101" ;
+assign O2 "00000000000000000101110010111101" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000000111110111101" ;
+assign O1 "00000000000000000111010101111010" ;
+assign O2 "00000000000000000111011010010001" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000001111000011000" ;
+assign O1 "00000000000000000111101000101001" ;
+assign O2 "00000000000000001000010100110111" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000110111111111010" ;
+assign O1 "00000000000000000111000110111101" ;
+assign O2 "00000000000000001001100001000001" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000101111000100100" ;
+assign O1 "00000000000000000110101010111001" ;
+assign O2 "00000000000000001110000110110111" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000000101110001111" ;
+assign O1 "00000000000000000100111110100100" ;
+assign O2 "00000000000000001100100011011101" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000110100001101111" ;
+assign O1 "00000000000000000100110100001101" ;
+assign O2 "00000000000000000101101100110011" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000000101100010111" ;
+assign O1 "00000000000000000100111111001110" ;
+assign O2 "00000000000000001011010101111100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000111111101111001" ;
+assign O1 "00000000000000000101001000001111" ;
+assign O2 "00000000000000000101101011100101" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000101100110010100" ;
+assign O1 "00000000000000000011000111000100" ;
+assign O2 "00000000000000001101000110001000" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000010100100000000" ;
+assign O1 "00000000000000000101101000001101" ;
+assign O2 "00000000000000001000101101011000" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000100110001111011" ;
+assign O1 "00000000000000000000111010011001" ;
+assign O2 "00000000000000001000001100001101" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000111101101101111" ;
+assign O1 "00000000000000000111011000100111" ;
+assign O2 "00000000000000000101101100010100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000001111010101110" ;
+assign O1 "00000000000000000001110011010111" ;
+assign O2 "00000000000000001111000110010110" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000110101110010100" ;
+assign O1 "00000000000000000010000101011000" ;
+assign O2 "00000000000000000011101110000101" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000100111010000001" ;
+assign O1 "00000000000000000010010011011110" ;
+assign O2 "00000000000000001000110011101100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000111011101001101" ;
+assign O1 "00000000000000000001001100001010" ;
+assign O2 "00000000000000000111001101011111" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000101010001110110" ;
+assign O1 "00000000000000000111101010111110" ;
+assign O2 "00000000000000001000101001010111" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000100100010101110" ;
+assign O1 "00000000000000000101001001010100" ;
+assign O2 "00000000000000001100111100110100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000000000011101010" ;
+assign O1 "00000000000000000101111010101101" ;
+assign O2 "00000000000000001001101100000010" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000001100000010000" ;
+assign O1 "00000000000000000011111011101010" ;
+assign O2 "00000000000000000101111110010111" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000111011001111011" ;
+assign O1 "00000000000000000001011000111011" ;
+assign O2 "00000000000000000101011011111010" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000000000101101101" ;
+assign O1 "00000000000000000111111010111111" ;
+assign O2 "00000000000000001000110010110110" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000110111001010110" ;
+assign O1 "00000000000000000011110111110001" ;
+assign O2 "00000000000000001000000000101100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000000111000000100" ;
+assign O1 "00000000000000000011010001111101" ;
+assign O2 "00000000000000001010110001000111" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000101100010101011" ;
+assign O1 "00000000000000000011111110001011" ;
+assign O2 "00000000000000000100001010000001" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000001101000111001" ;
+assign O1 "00000000000000000000001001011111" ;
+assign O2 "00000000000000001001100000110110" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000101100101111110" ;
+assign O1 "00000000000000000010010100010110" ;
+assign O2 "00000000000000000001110010011000" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000111010000001100" ;
+assign O1 "00000000000000000110100111100100" ;
+assign O2 "00000000000000000111111010010100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000010100111101101" ;
+assign O1 "00000000000000000000101001001111" ;
+assign O2 "00000000000000001101110111110000" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000001111111010000" ;
+assign O1 "00000000000000000110010110110100" ;
+assign O2 "00000000000000000011010000111100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000100000001101101" ;
+assign O1 "00000000000000000010000011011011" ;
+assign O2 "00000000000000001000010110000100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000001100000110010" ;
+assign O1 "00000000000000000000001011010101" ;
+assign O2 "00000000000000000110000101001000" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000111111100000010" ;
+assign O1 "00000000000000000010110101101110" ;
+assign O2 "00000000000000000001101100000111" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000100100110110010" ;
+assign O1 "00000000000000000101110100101001" ;
+assign O2 "00000000000000001010110001110000" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000001010010111110" ;
+assign O1 "00000000000000000000010101000110" ;
+assign O2 "00000000000000001010011011011011" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000010001000111100" ;
+assign O1 "00000000000000000001110010011010" ;
+assign O2 "00000000000000000001101000000100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000011101011110001" ;
+assign O1 "00000000000000000100001100100011" ;
+assign O2 "00000000000000000011111011010110" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000010110100010100" ;
+assign O1 "00000000000000000011000100000001" ;
+assign O2 "00000000000000000111111000010100" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000011000110011011" ;
+assign O1 "00000000000000000110110101010100" ;
+assign O2 "00000000000000000101111000010101" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000000000100100100" ;
+assign O1 "00000000000000000000110110111010" ;
+assign O2 "00000000000000001001111011101111" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000101100111010101" ;
+assign O1 "00000000000000000110110001001001" ;
+assign O2 "00000000000000000000111011011110" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000000011011000110" ;
+assign O1 "00000000000000000110001010101100" ;
+assign O2 "00000000000000001100011000011110" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
+delta_time 10000 ;
+assign O0 "00000000000000000001100101110001" ;
+assign O1 "00000000000000000111101111001100" ;
+assign O2 "00000000000000000110100101110010" ;
+assign O3 '1' ;
+
+delta_time 10000 ;
+assign O3 '0' ;
+
diff --git a/src/systemc/tests/systemc/tracing/wif_trace/mixed/isaac.h b/src/systemc/tests/systemc/tracing/wif_trace/mixed/isaac.h
new file mode 100644
index 000000000..9625be2ac
--- /dev/null
+++ b/src/systemc/tests/systemc/tracing/wif_trace/mixed/isaac.h
@@ -0,0 +1,272 @@
+#ifndef __ISAAC_HPP
+#define __ISAAC_HPP
+
+
+/*
+
+ C++ TEMPLATE VERSION OF Robert J. Jenkins Jr.'s
+ ISAAC Random Number Generator.
+
+ Ported from vanilla C to to template C++ class
+ by Quinn Tyler Jackson on 16-23 July 1998.
+
+ quinn@qtj.net
+
+ The function for the expected period of this
+ random number generator, according to Jenkins is:
+
+ f(a,b) = 2**((a+b*(3+2^^a)-1)
+
+ (where a is ALPHA and b is bitwidth)
+
+ So, for a bitwidth of 32 and an ALPHA of 8,
+ the expected period of ISAAC is:
+
+ 2^^(8+32*(3+2^^8)-1) = 2^^8295
+
+ Jackson has been able to run implementations
+ with an ALPHA as high as 16, or
+
+ 2^^2097263
+
+*/
+
+
+typedef unsigned int UINT32;
+const UINT32 GOLDEN_RATIO = UINT32(0x9e3779b9);
+
+
+template <UINT32 ALPHA = (8)>
+class QTIsaac
+{
+ public:
+
+ typedef unsigned char byte;
+
+ struct randctx
+ {
+ randctx(void)
+ {
+ randrsl = new UINT32[N];
+ randmem = new UINT32[N];
+ }
+
+ ~randctx(void)
+ {
+ delete [] randrsl;
+ delete [] randmem;
+ }
+
+ UINT32 randcnt;
+ UINT32* randrsl;
+ UINT32* randmem;
+ UINT32 randa;
+ UINT32 randb;
+ UINT32 randc;
+ };
+
+ QTIsaac(UINT32 a = 0, UINT32 b = 0, UINT32 c = 0);
+ virtual ~QTIsaac(void);
+
+ UINT32 rand(void);
+ virtual void randinit(randctx* ctx, bool bUseSeed);
+ virtual void srand(
+ UINT32 a = 0, UINT32 b = 0, UINT32 c = 0, UINT32* s = NULL);
+
+ enum {N = (1<<ALPHA)};
+
+ protected:
+
+ virtual void isaac(randctx* ctx);
+
+ UINT32 ind(UINT32* mm, UINT32 x);
+ void rngstep(
+ UINT32 mix, UINT32& a, UINT32& b, UINT32*& mm, UINT32*& m,
+ UINT32*& m2, UINT32*& r, UINT32& x, UINT32& y);
+ virtual void shuffle(
+ UINT32& a, UINT32& b, UINT32& c, UINT32& d, UINT32& e, UINT32& f,
+ UINT32& g, UINT32& h);
+
+ private:
+ randctx m_rc;
+};
+
+
+template<UINT32 ALPHA>
+QTIsaac<ALPHA>::QTIsaac(UINT32 a, UINT32 b, UINT32 c) : m_rc()
+{
+ srand(a, b, c);
+}
+
+
+template<UINT32 ALPHA>
+QTIsaac<ALPHA>::~QTIsaac(void)
+{
+ // DO NOTHING
+}
+
+
+template<UINT32 ALPHA>
+void QTIsaac<ALPHA>::srand(UINT32 a, UINT32 b, UINT32 c, UINT32* s)
+{
+ for(int i = 0; i < N; i++)
+ {
+ m_rc.randrsl[i] = s != NULL ? s[i] : 0;
+ }
+
+ m_rc.randa = a;
+ m_rc.randb = b;
+ m_rc.randc = c;
+
+ randinit(&m_rc, true);
+}
+
+
+template<UINT32 ALPHA>
+inline UINT32 QTIsaac<ALPHA>::rand(void)
+{
+ return 0x7fffffff & (!m_rc.randcnt-- ?
+ (isaac(&m_rc), m_rc.randcnt=(N-1), m_rc.randrsl[m_rc.randcnt]) :
+ m_rc.randrsl[m_rc.randcnt]);
+}
+
+
+template<UINT32 ALPHA>
+inline void QTIsaac<ALPHA>::randinit(randctx* ctx, bool bUseSeed)
+{
+ UINT32 a,b,c,d,e,f,g,h;
+ int i;
+
+ a = b = c = d = e = f = g = h = GOLDEN_RATIO;
+
+ UINT32* m = (ctx->randmem);
+ UINT32* r = (ctx->randrsl);
+
+ if(!bUseSeed)
+ {
+ ctx->randa = 0;
+ ctx->randb = 0;
+ ctx->randc = 0;
+ }
+
+ // scramble it
+ for(i=0; i < 4; ++i)
+ {
+ shuffle(a,b,c,d,e,f,g,h);
+ }
+
+ if(bUseSeed)
+ {
+ // initialize using the contents of r[] as the seed
+
+ for(i=0; i < N; i+=8)
+ {
+ a+=r[i ]; b+=r[i+1]; c+=r[i+2]; d+=r[i+3];
+ e+=r[i+4]; f+=r[i+5]; g+=r[i+6]; h+=r[i+7];
+
+ shuffle(a,b,c,d,e,f,g,h);
+
+ m[i ]=a; m[i+1]=b; m[i+2]=c; m[i+3]=d;
+ m[i+4]=e; m[i+5]=f; m[i+6]=g; m[i+7]=h;
+ }
+
+ //do a second pass to make all of the seed affect all of m
+
+ for(i=0; i < N; i += 8)
+ {
+ a+=m[i ]; b+=m[i+1]; c+=m[i+2]; d+=m[i+3];
+ e+=m[i+4]; f+=m[i+5]; g+=m[i+6]; h+=m[i+7];
+
+ shuffle(a,b,c,d,e,f,g,h);
+
+ m[i ]=a; m[i+1]=b; m[i+2]=c; m[i+3]=d;
+ m[i+4]=e; m[i+5]=f; m[i+6]=g; m[i+7]=h;
+ }
+ }
+ else
+ {
+ // fill in mm[] with messy stuff
+
+ shuffle(a,b,c,d,e,f,g,h);
+
+ m[i ]=a; m[i+1]=b; m[i+2]=c; m[i+3]=d;
+ m[i+4]=e; m[i+5]=f; m[i+6]=g; m[i+7]=h;
+
+ }
+
+ isaac(ctx); // fill in the first set of results
+ ctx->randcnt = N; // prepare to use the first set of results
+}
+
+
+template<UINT32 ALPHA>
+inline UINT32 QTIsaac<ALPHA>::ind(UINT32* mm, UINT32 x)
+{
+ return (*(UINT32*)((byte*)(mm) + ((x) & ((N-1)<<2))));
+}
+
+
+template<UINT32 ALPHA>
+inline void QTIsaac<ALPHA>::rngstep(UINT32 mix, UINT32& a, UINT32& b, UINT32*& mm, UINT32*& m, UINT32*& m2, UINT32*& r, UINT32& x, UINT32& y)
+{
+ x = *m;
+ a = (a^(mix)) + *(m2++);
+ *(m++) = y = ind(mm,x) + a + b;
+ *(r++) = b = ind(mm,y>>ALPHA) + x;
+}
+
+
+template<UINT32 ALPHA>
+inline void QTIsaac<ALPHA>::shuffle(UINT32& a, UINT32& b, UINT32& c, UINT32& d, UINT32& e, UINT32& f, UINT32& g, UINT32& h)
+{
+ a^=b<<11; d+=a; b+=c;
+ b^=c>>2; e+=b; c+=d;
+ c^=d<<8; f+=c; d+=e;
+ d^=e>>16; g+=d; e+=f;
+ e^=f<<10; h+=e; f+=g;
+ f^=g>>4; a+=f; g+=h;
+ g^=h<<8; b+=g; h+=a;
+ h^=a>>9; c+=h; a+=b;
+}
+
+
+template<UINT32 ALPHA>
+inline void QTIsaac<ALPHA>::isaac(randctx* ctx)
+{
+ UINT32 x,y;
+
+ UINT32* mm = ctx->randmem;
+ UINT32* r = ctx->randrsl;
+
+ UINT32 a = (ctx->randa);
+ UINT32 b = (ctx->randb + (++ctx->randc));
+
+ UINT32* m = mm;
+ UINT32* m2 = (m+(N/2));
+ UINT32* mend = m2;
+
+ for(; m<mend; )
+ {
+ rngstep((a<<13), a, b, mm, m, m2, r, x, y);
+ rngstep((a>>6) , a, b, mm, m, m2, r, x, y);
+ rngstep((a<<2) , a, b, mm, m, m2, r, x, y);
+ rngstep((a>>16), a, b, mm, m, m2, r, x, y);
+ }
+
+ m2 = mm;
+
+ for(; m2<mend; )
+ {
+ rngstep((a<<13), a, b, mm, m, m2, r, x, y);
+ rngstep((a>>6) , a, b, mm, m, m2, r, x, y);
+ rngstep((a<<2) , a, b, mm, m, m2, r, x, y);
+ rngstep((a>>16), a, b, mm, m, m2, r, x, y);
+ }
+
+ ctx->randb = b;
+ ctx->randa = a;
+}
+
+
+#endif // __ISAAC_HPP
+
diff --git a/src/systemc/tests/systemc/tracing/wif_trace/mixed/mixed.cpp b/src/systemc/tests/systemc/tracing/wif_trace/mixed/mixed.cpp
new file mode 100644
index 000000000..bb52e29d9
--- /dev/null
+++ b/src/systemc/tests/systemc/tracing/wif_trace/mixed/mixed.cpp
@@ -0,0 +1,129 @@
+/*****************************************************************************
+
+ Licensed to Accellera Systems Initiative Inc. (Accellera) under one or
+ more contributor license agreements. See the NOTICE file distributed
+ with this work for additional information regarding copyright ownership.
+ Accellera licenses this file to you under the Apache License, Version 2.0
+ (the "License"); you may not use this file except in compliance with the
+ License. You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+ implied. See the License for the specific language governing
+ permissions and limitations under the License.
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ mixed.cpp --
+
+ Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15
+
+ *****************************************************************************/
+
+/*****************************************************************************
+
+ MODIFICATION LOG - modifiers, enter your name, affiliation, date and
+ changes you are making here.
+
+ Name, Affiliation, Date:
+ Description of Modification:
+
+ *****************************************************************************/
+
+#include "systemc.h"
+#include "isaac.h"
+
+QTIsaac<8> rng;
+
+SC_MODULE( adder )
+{
+ SC_HAS_PROCESS( adder );
+
+ sc_in<bool> clk;
+ sc_in<int> a;
+ sc_in<int> b;
+ sc_out<int> sum;
+
+ adder( sc_module_name NAME,
+ sc_clock& CLK,
+ sc_signal<int>& A,
+ sc_signal<int>& B,
+ sc_signal<int>& SUM )
+ : a(A), b(B), sum(SUM)
+ {
+ clk(CLK);
+ SC_METHOD( entry );
+ sensitive << clk;
+ sensitive << a;
+ sensitive << b;
+ }
+ void entry();
+};
+
+void
+adder::entry()
+{
+ if (clk.posedge()) {
+ sum = a + b;
+ }
+}
+
+SC_MODULE( stim )
+{
+ SC_HAS_PROCESS( stim );
+
+ sc_in_clk clk;
+ sc_out<int> a;
+ sc_out<int> b;
+
+ stim( sc_module_name NAME,
+ sc_clock& CLK,
+ sc_signal<int>& A,
+ sc_signal<int>& B )
+ : a(A), b(B)
+ {
+ clk(CLK);
+ SC_CTHREAD( entry, clk.pos() );
+ }
+ void entry();
+};
+
+void
+stim::entry()
+{
+ while (true) {
+ a = rng.rand() % 32768;
+ b = rng.rand() % 32768;
+ wait();
+ }
+}
+
+int
+sc_main( int argc, char* argv[] )
+{
+ sc_signal<int> a("a");
+ sc_signal<int> b("b");
+ sc_signal<int> sum("sum");
+ sc_clock clk("clk", 20, SC_NS);
+
+ a = 0;
+ b = 0;
+ sum = 0;
+
+ adder add("add", clk, a, b, sum);
+ stim sti("sti", clk, a, b);
+
+ sc_trace_file* tf = sc_create_wif_trace_file("mixed");
+ sc_trace(tf, a, "a");
+ sc_trace(tf, b, "b");
+ sc_trace(tf, sum, "sum");
+ sc_trace(tf, clk, "clk");
+ sc_start(1000, SC_NS);
+ sc_close_wif_trace_file( tf );
+ return 0;
+}
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