diff options
Diffstat (limited to 'src/systemc/tests/systemc/tracing')
88 files changed, 11485 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/sc_signal_ports/golden/test.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/sc_signal_ports/golden/test.vcd new file mode 100644 index 000000000..f6330342b --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/sc_signal_ports/golden/test.vcd @@ -0,0 +1,202 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 32 aaaaa sig_int [31:0] $end +$var wire 1 aaaab sig_bool $end +$var wire 1 aaaac sig_logic $end +$var wire 1 aaaad sig_resolved $end +$var wire 1 aaaae sig_rv1 $end +$scope module a $end +$var wire 1 aaaaf out_rv1 $end +$var wire 1 aaaag out_resolved $end +$var wire 1 aaaah out_logic $end +$var wire 1 aaaai out_bool $end +$var wire 32 aaaaj out_int [31:0] $end +$var wire 1 aaaak in_rv1 $end +$var wire 1 aaaal in_resolved $end +$var wire 1 aaaam in_logic $end +$var wire 1 aaaan in_bool $end +$var wire 32 aaaao in_int [31:0] $end +$upscope $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b0 aaaaa +0aaaab +xaaaac +xaaaad +Xaaaae +Xaaaaf +xaaaag +xaaaah +0aaaai +b0 aaaaj +Xaaaak +xaaaal +xaaaam +0aaaan +b0 aaaao +$end + +#1000 +b1 aaaaa +1aaaab +1aaaac +1aaaad +1aaaae +1aaaaf +1aaaag +1aaaah +1aaaai +b1 aaaaj +1aaaak +1aaaal +1aaaam +1aaaan +b1 aaaao + +#2000 +b10 aaaaa +0aaaab +zaaaac +zaaaad +Zaaaae +Zaaaaf +zaaaag +zaaaah +0aaaai +b10 aaaaj +Zaaaak +zaaaal +zaaaam +0aaaan +b10 aaaao + +#3000 +b11 aaaaa +1aaaab +xaaaac +xaaaad +Xaaaae +Xaaaaf +xaaaag +xaaaah +1aaaai +b11 aaaaj +Xaaaak +xaaaal +xaaaam +1aaaan +b11 aaaao + +#4000 +b100 aaaaa +0aaaab +0aaaac +0aaaad +0aaaae +0aaaaf +0aaaag +0aaaah +0aaaai +b100 aaaaj +0aaaak +0aaaal +0aaaam +0aaaan +b100 aaaao + +#5000 +b101 aaaaa +1aaaab +1aaaac +1aaaad +1aaaae +1aaaaf +1aaaag +1aaaah +1aaaai +b101 aaaaj +1aaaak +1aaaal +1aaaam +1aaaan +b101 aaaao + +#6000 +b110 aaaaa +0aaaab +zaaaac +zaaaad +Zaaaae +Zaaaaf +zaaaag +zaaaah +0aaaai +b110 aaaaj +Zaaaak +zaaaal +zaaaam +0aaaan +b110 aaaao + +#7000 +b111 aaaaa +1aaaab +xaaaac +xaaaad +Xaaaae +Xaaaaf +xaaaag +xaaaah +1aaaai +b111 aaaaj +Xaaaak +xaaaal +xaaaam +1aaaan +b111 aaaao + +#8000 +b1000 aaaaa +0aaaab +0aaaac +0aaaad +0aaaae +0aaaaf +0aaaag +0aaaah +0aaaai +b1000 aaaaj +0aaaak +0aaaal +0aaaam +0aaaan +b1000 aaaao + +#9000 +b1001 aaaaa +1aaaab +1aaaac +1aaaad +1aaaae +1aaaaf +1aaaag +1aaaah +1aaaai +b1001 aaaaj +1aaaak +1aaaal +1aaaam +1aaaan +b1001 aaaao + +#10000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/sc_signal_ports/test.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/sc_signal_ports/test.cpp new file mode 100644 index 000000000..276941ca0 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/sc_signal_ports/test.cpp @@ -0,0 +1,144 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +// test of signal port tracing. + +#include "systemc.h" + +SC_MODULE( mod_a ) +{ + sc_in_clk clk; + + sc_in<int> in_int; + sc_in<bool> in_bool; + sc_in<sc_logic> in_logic; + sc_in_resolved in_resolved; + sc_in_rv<1> in_rv1; + + sc_out<int> out_int; + sc_out<bool> out_bool; + sc_out<sc_logic> out_logic; + sc_out_resolved out_resolved; + sc_out_rv<1> out_rv1; + + void main_action() + { + int a_int = 0; + bool a_bool = false; + sc_logic a_logic = SC_LOGIC_X; + sc_logic a_resolved = SC_LOGIC_X; + sc_lv<1> a_rv1 = sc_lv<1>( SC_LOGIC_X ); + + wait(); + + while( true ) { + out_int = a_int; + out_bool = a_bool; + out_logic = a_logic; + out_resolved = a_resolved; + out_rv1 = a_rv1; + + a_int ++; + a_bool = ! a_bool; + a_logic = sc_dt::sc_logic_value_t( a_int % 4 ); + a_resolved = a_logic; + a_rv1 = sc_lv<1>( a_logic ); + + wait(); + } + } + + SC_CTOR( mod_a ) + { + SC_THREAD( main_action ); + sensitive << clk.pos(); + } +}; + +int +sc_main( int, char*[] ) +{ + sc_clock clk; + + sc_signal<int> sig_int; + sc_signal<bool> sig_bool; + sc_signal<sc_logic> sig_logic; + sc_signal_resolved sig_resolved; + sc_signal_rv<1> sig_rv1; + + mod_a a( "a" ); + + a.clk( clk ); + + a.in_int( sig_int ); + a.in_bool( sig_bool ); + a.in_logic( sig_logic ); + a.in_resolved( sig_resolved ); + a.in_rv1( sig_rv1 ); + + a.out_int( sig_int ); + a.out_bool( sig_bool ); + a.out_logic( sig_logic ); + a.out_resolved( sig_resolved ); + a.out_rv1( sig_rv1 ); + + sc_trace_file* tf = sc_create_vcd_trace_file( "test" ); + + sc_trace( tf, sig_int, "sig_int" ); + sc_trace( tf, sig_bool, "sig_bool" ); + sc_trace( tf, sig_logic, "sig_logic" ); + sc_trace( tf, sig_resolved, "sig_resolved" ); + sc_trace( tf, sig_rv1, "sig_rv1" ); + + sc_trace( tf, a.in_int, "a.in_int" ); + sc_trace( tf, a.in_bool, "a.in_bool" ); + sc_trace( tf, a.in_logic, "a.in_logic" ); + sc_trace( tf, a.in_resolved, "a.in_resolved" ); + sc_trace( tf, a.in_rv1, "a.in_rv1" ); + + sc_trace( tf, a.out_int, "a.out_int" ); + sc_trace( tf, a.out_bool, "a.out_bool" ); + sc_trace( tf, a.out_logic, "a.out_logic" ); + sc_trace( tf, a.out_resolved, "a.out_resolved" ); + sc_trace( tf, a.out_rv1, "a.out_rv1" ); + + sc_start( 10, SC_NS ); + + sc_close_vcd_trace_file( tf ); + + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test01/golden/test01.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test01/golden/test01.vcd new file mode 100644 index 000000000..2c425a471 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test01/golden/test01.vcd @@ -0,0 +1,126 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 1 aaaaa Bool $end +$var wire 1 aaaab SC_Logic $end +$var wire 4 aaaac SC_BV [3:0] $end +$var wire 4 aaaad SC_LV [3:0] $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +0aaaaa +1aaaab +b0 aaaac +b1111 aaaad +$end + +#10000 +1aaaaa +0aaaab +b1010 aaaac +b1011 aaaad + +#20000 +b101 aaaac +b101 aaaad + +#30000 +0aaaaa +1aaaab +b0 aaaac +b1111 aaaad + +#40000 +1aaaaa +0aaaab +b1010 aaaac +b1011 aaaad + +#50000 +b110 aaaac +b110 aaaad + +#60000 +0aaaaa +1aaaab +b0 aaaac +b1111 aaaad + +#70000 +1aaaaa +0aaaab +b1010 aaaac +b1011 aaaad + +#80000 +b111 aaaac +b111 aaaad + +#90000 +0aaaaa +1aaaab +b0 aaaac +b1111 aaaad + +#100000 +1aaaaa +0aaaab +b1010 aaaac +b1011 aaaad + +#110000 +b1000 aaaac +b1000 aaaad + +#120000 +0aaaaa +1aaaab +b0 aaaac +b1111 aaaad + +#130000 +1aaaaa +0aaaab +b1010 aaaac +b1011 aaaad + +#140000 +b1001 aaaac +b1001 aaaad + +#150000 +0aaaaa +1aaaab +b0 aaaac +b1111 aaaad + +#160000 +1aaaaa +0aaaab +b1010 aaaac +b1011 aaaad + +#170000 +b1010 aaaad + +#180000 +0aaaaa +1aaaab +b0 aaaac +b1111 aaaad + +#190000 +1aaaaa +0aaaab +b1010 aaaac +b1011 aaaad + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test01/test01.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test01/test01.cpp new file mode 100644 index 000000000..39e0fded1 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test01/test01.cpp @@ -0,0 +1,117 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test01.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + bool obj1; + sc_logic obj2; + sc_bv<4> obj3; + sc_lv<4> obj4; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = "0000"; + obj4 = "0000"; + } + + void entry(); +}; + +void proc1::entry() +{ + sc_bv<4> bv; + sc_lv<4> sv; + int i = 5; + wait(); + while(true) { + bv = i; + sv = i++; + obj1 = 0; + obj2 = 1; + obj3 = "0000"; + obj4 = "1111"; + wait(); + obj1 = 1; + obj2 = 0; + obj3 = "1010"; + obj4 = "1011"; + wait(); + obj3 = bv; + obj4 = sv; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_vcd_trace_file("test01"); + tf->set_time_unit(1.0, SC_PS); + sc_trace(tf, P1.obj1, "Bool"); + sc_trace(tf, P1.obj2, "SC_Logic"); + sc_trace(tf, P1.obj3, "SC_BV"); + sc_trace(tf, P1.obj4, "SC_LV"); + //sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_vcd_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd new file mode 100644 index 000000000..10a09a376 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd @@ -0,0 +1,160 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 32 aaaad Long [31:0] $end +$var wire 1 aaaae Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae +$end + +#10000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#20000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#30000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#40000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#50000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#60000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#70000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#80000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#90000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#100000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#110000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#120000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#130000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#140000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#150000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#160000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#170000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#180000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#190000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.bsd64 b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.bsd64 new file mode 100644 index 000000000..21100dc36 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.bsd64 @@ -0,0 +1,160 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 1 aaaae Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae +$end + +#10000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#20000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#30000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#40000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#50000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#60000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#70000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#80000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#90000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#100000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#110000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#120000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#130000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#140000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#150000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#160000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#170000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#180000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#190000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.cygwin64 b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.cygwin64 new file mode 100644 index 000000000..21100dc36 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.cygwin64 @@ -0,0 +1,160 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 1 aaaae Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae +$end + +#10000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#20000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#30000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#40000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#50000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#60000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#70000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#80000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#90000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#100000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#110000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#120000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#130000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#140000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#150000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#160000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#170000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#180000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#190000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.linux64 b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.linux64 new file mode 100644 index 000000000..21100dc36 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.linux64 @@ -0,0 +1,160 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 1 aaaae Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae +$end + +#10000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#20000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#30000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#40000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#50000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#60000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#70000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#80000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#90000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#100000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#110000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#120000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#130000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#140000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#150000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#160000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#170000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#180000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#190000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.linuxaarch64 b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.linuxaarch64 new file mode 100644 index 000000000..21100dc36 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.linuxaarch64 @@ -0,0 +1,160 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 1 aaaae Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae +$end + +#10000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#20000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#30000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#40000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#50000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#60000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#70000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#80000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#90000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#100000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#110000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#120000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#130000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#140000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#150000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#160000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#170000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#180000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#190000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.macosx64 b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.macosx64 new file mode 100644 index 000000000..21100dc36 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test02/golden/test02.vcd.macosx64 @@ -0,0 +1,160 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 1 aaaae Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae +$end + +#10000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#20000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#30000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#40000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#50000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#60000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#70000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#80000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#90000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#100000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#110000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#120000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#130000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#140000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#150000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#160000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#170000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#180000 +b111 aaaaa +b11111 aaaab +b1111111111 aaaac +b11111111111 aaaad +1aaaae + +#190000 +b1 aaaaa +b100000 aaaab +b10000000000 aaaac +b100000000000 aaaad +0aaaae + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test02/test02.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test02/test02.cpp new file mode 100644 index 000000000..d69a71802 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test02/test02.cpp @@ -0,0 +1,108 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test02.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + unsigned char obj1; + unsigned short obj2; + unsigned int obj3; + unsigned long obj4; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = 0; + obj4 = 0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 7; + obj2 = 31; + obj3 = 1023; + obj4 = 2047; + wait(); + obj1 = 1; + obj2 = 32; + obj3 = 1024; + obj4 = 2048; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_vcd_trace_file("test02"); + sc_trace(tf, P1.obj1, "Char"); + sc_trace(tf, P1.obj2, "Short"); + sc_trace(tf, P1.obj3, "Int"); + sc_trace(tf, P1.obj4, "Long"); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_vcd_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test03/golden/test03.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test03/golden/test03.vcd new file mode 100644 index 000000000..f1bf6667c --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test03/golden/test03.vcd @@ -0,0 +1,181 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 4 aaaaa Char [3:0] $end +$var wire 4 aaaab Short [3:0] $end +$var wire 12 aaaac Int [11:0] $end +$var wire 10 aaaad Long [9:0] $end +$var wire 43 aaaae Uint64 [42:0] $end +$var wire 1 aaaaf Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf +$end + +#10000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#20000 +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf + +#30000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#40000 +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf + +#50000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#60000 +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf + +#70000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#80000 +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf + +#90000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#100000 +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf + +#110000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#120000 +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf + +#130000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#140000 +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf + +#150000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#160000 +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf + +#170000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#180000 +b111 aaaaa +bx aaaab +b1111111111 aaaac +b111111 aaaad +b1000000000000000000000000000000000000000000 aaaae +1aaaaf + +#190000 +b1 aaaaa +b11 aaaab +b10000000000 aaaac +bx aaaad +bx aaaae +0aaaaf + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test03/test03.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test03/test03.cpp new file mode 100644 index 000000000..3d53b4eb7 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test03/test03.cpp @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test03.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + unsigned char obj1; + unsigned short obj2; + unsigned int obj3; + unsigned long obj4; + uint64 obj5; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = 0; + obj4 = 0; + obj5 = 0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 7; + obj2 = 31; + obj3 = 1023; + obj4 = 63; + obj5 = 1; + obj5 = obj5 << 42; + wait(); + obj1 = 1; + obj2 = 3; + obj3 = 1024; + obj4 = 2048; + obj5 = 3; + obj5 = obj5 << 42; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_vcd_trace_file("test03"); + sc_trace(tf, P1.obj1, "Char", 4); + sc_trace(tf, P1.obj2, "Short", 4); + sc_trace(tf, P1.obj3, "Int", 12); + sc_trace(tf, P1.obj4, "Long", 10); + sc_trace(tf, P1.obj5, "Uint64", 43); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_vcd_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd new file mode 100644 index 000000000..c2129bb0e --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd @@ -0,0 +1,181 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 32 aaaad Long [31:0] $end +$var wire 64 aaaae Int64 [63:0] $end +$var wire 1 aaaaf Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf +$end + +#10000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#20000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#30000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#40000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#50000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#60000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#70000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#80000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#90000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#100000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#110000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#120000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#130000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#140000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#150000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#160000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#170000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#180000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#190000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b11111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.bsd64 b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.bsd64 new file mode 100644 index 000000000..538167b24 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.bsd64 @@ -0,0 +1,181 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 64 aaaae Int64 [63:0] $end +$var wire 1 aaaaf Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf +$end + +#10000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#20000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#30000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#40000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#50000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#60000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#70000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#80000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#90000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#100000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#110000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#120000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#130000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#140000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#150000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#160000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#170000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#180000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#190000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.cygwin64 b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.cygwin64 new file mode 100644 index 000000000..538167b24 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.cygwin64 @@ -0,0 +1,181 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 64 aaaae Int64 [63:0] $end +$var wire 1 aaaaf Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf +$end + +#10000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#20000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#30000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#40000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#50000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#60000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#70000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#80000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#90000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#100000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#110000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#120000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#130000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#140000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#150000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#160000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#170000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#180000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#190000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.linux64 b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.linux64 new file mode 100644 index 000000000..538167b24 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.linux64 @@ -0,0 +1,181 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 64 aaaae Int64 [63:0] $end +$var wire 1 aaaaf Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf +$end + +#10000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#20000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#30000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#40000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#50000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#60000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#70000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#80000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#90000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#100000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#110000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#120000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#130000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#140000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#150000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#160000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#170000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#180000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#190000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.linuxaarch64 b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.linuxaarch64 new file mode 100644 index 000000000..538167b24 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.linuxaarch64 @@ -0,0 +1,181 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 64 aaaae Int64 [63:0] $end +$var wire 1 aaaaf Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf +$end + +#10000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#20000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#30000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#40000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#50000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#60000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#70000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#80000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#90000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#100000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#110000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#120000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#130000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#140000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#150000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#160000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#170000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#180000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#190000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.macosx64 b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.macosx64 new file mode 100644 index 000000000..538167b24 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test04/golden/test04.vcd.macosx64 @@ -0,0 +1,181 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 8 aaaaa Char [7:0] $end +$var wire 16 aaaab Short [15:0] $end +$var wire 32 aaaac Int [31:0] $end +$var wire 64 aaaad Long [63:0] $end +$var wire 64 aaaae Int64 [63:0] $end +$var wire 1 aaaaf Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf +$end + +#10000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#20000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#30000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#40000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#50000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#60000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#70000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#80000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#90000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#100000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#110000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#120000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#130000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#140000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#150000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#160000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#170000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#180000 +b111 aaaaa +b11111 aaaab +b11111111111111111111110000000001 aaaac +b11111111111 aaaad +b1111111111111111111111111111111111111111 aaaae +1aaaaf + +#190000 +b1 aaaaa +b1111111111111110 aaaab +b10000000000 aaaac +b1111111111111111111111111111111111111111111111111111100000000000 aaaad +b1111111111111111111111110000000000000000000000000000000000000000 aaaae +0aaaaf + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test04/test04.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test04/test04.cpp new file mode 100644 index 000000000..546b3ca55 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test04/test04.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test04.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + char obj1; + short obj2; + int obj3; + long obj4; + int64 obj5; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = 0; + obj4 = 0; + obj5 = 0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 7; + obj2 = 31; + obj3 = -1023; + obj4 = 2047; + obj5 = -1; + obj5 = ~(obj5 << 40); + wait(); + obj1 = 1; + obj2 = -2; + obj3 = 1024; + obj4 = -2048; + obj5 = -(obj5+1); + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_vcd_trace_file("test04"); + sc_trace(tf, P1.obj1, "Char"); + sc_trace(tf, P1.obj2, "Short"); + sc_trace(tf, P1.obj3, "Int"); + sc_trace(tf, P1.obj4, "Long"); + sc_trace(tf, P1.obj5, "Int64"); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_vcd_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test05/golden/test05.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test05/golden/test05.vcd new file mode 100644 index 000000000..4e8be3b3b --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test05/golden/test05.vcd @@ -0,0 +1,181 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 4 aaaaa Char [3:0] $end +$var wire 12 aaaab Short [11:0] $end +$var wire 14 aaaac Int [13:0] $end +$var wire 14 aaaad Long [13:0] $end +$var wire 44 aaaae Int64 [43:0] $end +$var wire 1 aaaaf Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf +$end + +#10000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#20000 +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf + +#30000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#40000 +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf + +#50000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#60000 +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf + +#70000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#80000 +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf + +#90000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#100000 +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf + +#110000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#120000 +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf + +#130000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#140000 +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf + +#150000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#160000 +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf + +#170000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#180000 +b111 aaaaa +b11111 aaaab +bx aaaac +b11111111111 aaaad +bx aaaae +1aaaaf + +#190000 +b1 aaaaa +bx aaaab +b10000000000 aaaac +bx aaaad +b1110000000000000000000000000000000000000000 aaaae +0aaaaf + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test05/test05.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test05/test05.cpp new file mode 100644 index 000000000..b0880c4c6 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test05/test05.cpp @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test05.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + char obj1; + short obj2; + int obj3; + long obj4; + int64 obj5; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = 0; + obj4 = 0; + obj5 = 0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 7; + obj2 = 31; + obj3 = -1023; + obj4 = 2047; + obj5 = -1; + obj5 = obj5 << 40; + wait(); + obj1 = 1; + obj2 = -2; + obj3 = 1024; + obj4 = -2048; + obj5 = 7; + obj5 = obj5 << 40; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_vcd_trace_file("test05"); + sc_trace(tf, P1.obj1, "Char", 4); + sc_trace(tf, P1.obj2, "Short", 12); + sc_trace(tf, P1.obj3, "Int", 14); + sc_trace(tf, P1.obj4, "Long", 14); + sc_trace(tf, P1.obj5, "Int64", 44); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_vcd_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test06/golden/test06.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test06/golden/test06.vcd new file mode 100644 index 000000000..f46546373 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test06/golden/test06.vcd @@ -0,0 +1,97 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var real 1 aaaaa Float $end +$var real 1 aaaab Double $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +r12.34500026702881 aaaaa +r-13.5678923 aaaab +$end + +#10000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#20000 +r12.34500026702881 aaaaa +r-13.5678923 aaaab + +#30000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#40000 +r12.34500026702881 aaaaa +r-13.5678923 aaaab + +#50000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#60000 +r12.34500026702881 aaaaa +r-13.5678923 aaaab + +#70000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#80000 +r12.34500026702881 aaaaa +r-13.5678923 aaaab + +#90000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#100000 +r12.34500026702881 aaaaa +r-13.5678923 aaaab + +#110000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#120000 +r12.34500026702881 aaaaa +r-13.5678923 aaaab + +#130000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#140000 +r12.34500026702881 aaaaa +r-13.5678923 aaaab + +#150000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#160000 +r12.34500026702881 aaaaa +r-13.5678923 aaaab + +#170000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#180000 +r12.34500026702881 aaaaa +r-13.5678923 aaaab + +#190000 +r-182634880 aaaaa +r1672357.298346 aaaab + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test06/test06.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test06/test06.cpp new file mode 100644 index 000000000..a24951485 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test06/test06.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test06.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + float obj1; + double obj2; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0.0; + obj2 = 0.0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 12.345; + obj2 = -13.5678923; + wait(); + obj1 = -182634876.5659374; + obj2 = 1672357.298346; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_vcd_trace_file("test06"); + sc_trace(tf, P1.obj1, "Float"); + sc_trace(tf, P1.obj2, "Double"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_vcd_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test07/golden/test07.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test07/golden/test07.vcd new file mode 100644 index 000000000..0c2a3a022 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test07/golden/test07.vcd @@ -0,0 +1,139 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 4 aaaaa Signed [3:0] $end +$var wire 4 aaaab Unsigned [3:0] $end +$var wire 4 aaaac BV [3:0] $end +$var wire 4 aaaad SV [3:0] $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad +$end + +#10000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#20000 +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad + +#30000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#40000 +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad + +#50000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#60000 +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad + +#70000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#80000 +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad + +#90000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#100000 +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad + +#110000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#120000 +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad + +#130000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#140000 +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad + +#150000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#160000 +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad + +#170000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#180000 +b11 aaaaa +b111 aaaab +b11 aaaac +b1100 aaaad + +#190000 +b1101 aaaaa +b101 aaaab +b1111 aaaac +b1110 aaaad + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test07/test07.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test07/test07.cpp new file mode 100644 index 000000000..b0a73c6c4 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test07/test07.cpp @@ -0,0 +1,112 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test07.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + sc_signal<sc_bv<4> >& bv; + sc_signal<sc_lv<4> >& sv; + + sc_signed obj1; + sc_unsigned obj2; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK, + sc_signal<sc_bv<4> >& BV, + sc_signal<sc_lv<4> >& SV ) + : bv(BV), sv(SV), obj1(4), obj2(4) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + bv = "0000"; + sv = "0000"; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 3; + obj2 = 7; + bv = "0011"; + sv = "1100"; + wait(); + obj1 = -3; + obj2 = 5; + bv = "1111"; + sv = "1110"; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + sc_signal<sc_bv<4> > bv; + sc_signal<sc_lv<4> > sv; + + proc1 P1("P1", clock, bv, sv); + + tf = sc_create_vcd_trace_file("test07"); + sc_trace(tf, P1.obj1, "Signed"); + sc_trace(tf, P1.obj2, "Unsigned"); + sc_trace(tf, bv, "BV"); + sc_trace(tf, sv, "SV"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_vcd_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test08/golden/test08.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test08/golden/test08.vcd new file mode 100644 index 000000000..89c44a8e3 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test08/golden/test08.vcd @@ -0,0 +1,160 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 1 aaaaa Clock $end +$var wire 32 aaaab Int [31:0] $end +$var wire 8 aaaac Char [7:0] $end +$var real 1 aaaad Float $end +$var wire 1 aaaae Logic $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae +$end + +#10000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#20000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#30000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#40000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#50000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#60000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#70000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#80000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#90000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#100000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#110000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#120000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#130000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#140000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#150000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#160000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#170000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#180000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#190000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test08/test08.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test08/test08.cpp new file mode 100644 index 000000000..5ca91070c --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test08/test08.cpp @@ -0,0 +1,116 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test08.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + sc_signal<int>& Isig; + sc_signal<char>& Csig; + sc_signal<float>& Fsig; + sc_signal<sc_logic>& Lsig; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK, + sc_signal<int>& ISIG, + sc_signal<char>& CSIG, + sc_signal<float>& FSIG, + sc_signal<sc_logic>& LSIG ) + : Isig(ISIG), Csig(CSIG), Fsig(FSIG), Lsig(LSIG) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + Isig = 0; + Csig = 0; + Fsig = 0.0; + Lsig = SC_LOGIC_0;//'0'; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + Isig = 1023; + Csig = 15; + Fsig = -4; + Lsig = SC_LOGIC_X;//'x'; + wait(); + Isig = 10; + Csig = 8; + Fsig = 1000.23456; + Lsig = SC_LOGIC_Z;//'z'; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + sc_signal<int> I; + sc_signal<char> C; + sc_signal<float> F; + sc_signal<sc_logic> L; + + proc1 P1("P1", clock, I, C, F, L); + + tf = sc_create_vcd_trace_file("test08"); + sc_trace(tf, clock, "Clock"); + sc_trace(tf, I, "Int", 32); + sc_trace(tf, C, "Char", 8); + sc_trace(tf, F, "Float"); + sc_trace(tf, L, "Logic"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_vcd_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test09/golden/test09.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test09/golden/test09.vcd new file mode 100644 index 000000000..89c44a8e3 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test09/golden/test09.vcd @@ -0,0 +1,160 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 1 aaaaa Clock $end +$var wire 32 aaaab Int [31:0] $end +$var wire 8 aaaac Char [7:0] $end +$var real 1 aaaad Float $end +$var wire 1 aaaae Logic $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae +$end + +#10000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#20000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#30000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#40000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#50000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#60000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#70000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#80000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#90000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#100000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#110000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#120000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#130000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#140000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#150000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#160000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#170000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#180000 +1aaaaa +b1111111111 aaaab +b1111 aaaac +r-4 aaaad +xaaaae + +#190000 +0aaaaa +b1010 aaaab +b1000 aaaac +r1000.234558105469 aaaad +zaaaae + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test09/test09.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test09/test09.cpp new file mode 100644 index 000000000..2cf32898d --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test09/test09.cpp @@ -0,0 +1,118 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test09.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + sc_signal<int>& Isig; + sc_signal<char>& Csig; + sc_signal<float>& Fsig; + sc_signal<sc_logic>& Lsig; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK, + sc_signal<int>& ISIG, + sc_signal<char>& CSIG, + sc_signal<float>& FSIG, + sc_signal<sc_logic>& LSIG ) + : Isig(ISIG), Csig(CSIG), Fsig(FSIG), Lsig(LSIG) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + Isig = 0; + Csig = 0; + Fsig = 0.0; + Lsig = SC_LOGIC_0;//'0'; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + Isig = 1023; + Csig = 15; + Fsig = -4; + Lsig = SC_LOGIC_X;//'x'; + wait(); + Isig = 10; + Csig = 8; + Fsig = 1000.23456; + Lsig = SC_LOGIC_Z;//'z'; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + sc_signal<int> I; + sc_signal<char> C; + sc_signal<float> F; + sc_signal<sc_logic> L; + + proc1 P1("P1", clock, I, C, F, L); + + tf = sc_create_vcd_trace_file("test09"); + sc_trace(tf, clock, "Clock"); + sc_trace(tf, I, "Int"); + sc_trace(tf, C, "Char"); + sc_trace(tf, F, "Float"); + sc_trace(tf, L, "Logic"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + + sc_close_vcd_trace_file( tf ); + + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test10/golden/test10.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test10/golden/test10.vcd new file mode 100644 index 000000000..ade576b74 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test10/golden/test10.vcd @@ -0,0 +1,97 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 2 aaaaa Enum [1:0] $end +$var wire 1 aaaab Clock $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b0 aaaaa +1aaaab +$end + +#10000 +b1 aaaaa +0aaaab + +#20000 +b10 aaaaa +1aaaab + +#30000 +b0 aaaaa +0aaaab + +#40000 +b1 aaaaa +1aaaab + +#50000 +b10 aaaaa +0aaaab + +#60000 +b0 aaaaa +1aaaab + +#70000 +b1 aaaaa +0aaaab + +#80000 +b10 aaaaa +1aaaab + +#90000 +b0 aaaaa +0aaaab + +#100000 +b1 aaaaa +1aaaab + +#110000 +b10 aaaaa +0aaaab + +#120000 +b0 aaaaa +1aaaab + +#130000 +b1 aaaaa +0aaaab + +#140000 +b10 aaaaa +1aaaab + +#150000 +b0 aaaaa +0aaaab + +#160000 +b1 aaaaa +1aaaab + +#170000 +b10 aaaaa +0aaaab + +#180000 +b0 aaaaa +1aaaab + +#190000 +b1 aaaaa +0aaaab + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test10/test10.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test10/test10.cpp new file mode 100644 index 000000000..2d2688a34 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test10/test10.cpp @@ -0,0 +1,107 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test10.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + enum Ttype { + OK, + NOTOK, + SOSO + }; + + unsigned obj1; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = OK; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = OK; + wait(); + obj1 = NOTOK; + wait(); + obj1 = SOSO; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + char *enum_literals[4]; + enum_literals[0] = "OK"; + enum_literals[1] = "NOTOK"; + enum_literals[2] = "SOSO"; + enum_literals[3] = 0; + + proc1 P1("P1", clock); + + tf = sc_create_vcd_trace_file("test10"); + sc_trace(tf, P1.obj1, "Enum", (const char **) enum_literals); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_vcd_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test12/golden/test12.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test12/golden/test12.vcd new file mode 100644 index 000000000..00ddc9460 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test12/golden/test12.vcd @@ -0,0 +1,139 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 10 aaaaa Signed [9:0] $end +$var wire 10 aaaab Unsigned [9:0] $end +$var wire 10 aaaac BV [9:0] $end +$var wire 10 aaaad SV [9:0] $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad +$end + +#10000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#20000 +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad + +#30000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#40000 +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad + +#50000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#60000 +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad + +#70000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#80000 +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad + +#90000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#100000 +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad + +#110000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#120000 +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad + +#130000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#140000 +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad + +#150000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#160000 +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad + +#170000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#180000 +b11 aaaaa +b111 aaaab +b11 aaaac +b111 aaaad + +#190000 +b1111111101 aaaaa +b101 aaaab +b1111111101 aaaac +b101 aaaad + +#200000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test12/test12.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test12/test12.cpp new file mode 100644 index 000000000..d4f19a26e --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test12/test12.cpp @@ -0,0 +1,117 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test12.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + sc_signal<sc_int<10> >& bv; + sc_signal<sc_uint<10> >& sv; + + sc_int<10> obj1; + sc_uint<10> obj2; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK, + sc_signal<sc_int<10> >& BV, + sc_signal<sc_uint<10> >& SV ) + : bv(BV), sv(SV) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + bv.write(0); + sv.write(0); + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 3; + obj2 = 7; + bv = obj1; + sv = obj2; + wait(); + obj1 = -3; + obj2 = 5; + bv = obj1; + sv = obj2; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + sc_signal<sc_int<10> > bv; + sc_signal<sc_uint<10> > sv; + + proc1 P1("P1", clock, bv, sv); + + tf = sc_create_vcd_trace_file("test12"); + sc_trace(tf, P1.obj1, "Signed"); + sc_trace(tf, P1.obj2, "Unsigned"); + sc_trace(tf, bv, "BV"); + sc_trace(tf, sv, "SV"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { +cerr << sc_time_stamp() << endl; + clock.write(1); + sc_start(10, SC_NS); +cerr << sc_time_stamp() << endl; + clock.write(0); + sc_start(10, SC_NS); +cerr << sc_time_stamp() << endl; + } + + sc_close_vcd_trace_file( tf ); + + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test13/golden/test13.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test13/golden/test13.vcd new file mode 100644 index 000000000..f1b55ff3a --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test13/golden/test13.vcd @@ -0,0 +1,32 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 1 aaaaa clk $end +$scope module mod $end +$var wire 37 aaaab a [36:0] $end +$upscope $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +1aaaaa +b0 aaaab +$end + +#25000 +0aaaaa + +#50000 +1aaaaa +b1100 aaaab + +#75000 +0aaaaa + diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test13/test13.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test13/test13.cpp new file mode 100644 index 000000000..1c3333c78 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test13/test13.cpp @@ -0,0 +1,53 @@ +#include <systemc.h> +sc_trace_file* sc_tf; + +class Mod : public sc_module +{ + public: + sc_in_clk clk; + sc_in<sc_uint<37> > a; + + SC_HAS_PROCESS(Mod); + void foo() + { + cout << sc_time_stamp() << "\n"; + cout << " a = " << a << "\n"; + cout << "\n"; + + return; + + } // foo() + + Mod(const sc_module_name& name) : sc_module(name), a("a") + { + SC_METHOD(foo); + sensitive << clk.pos(); + dont_initialize(); + + sc_trace(sc_tf, a, a.name()); + } + +}; // class Mod + + +int sc_main(int argc, char* argv[]) +{ + sc_clock clk("clk", 50, SC_NS, 0.5, 0, SC_NS); + sc_signal<sc_uint<37> > a; + + sc_tf = sc_create_vcd_trace_file("test13"); + + Mod mod("mod"); + + mod.clk(clk); + mod.a(a); + + sc_trace(sc_tf, clk, clk.name()); + + sc_start(50, SC_NS); + a = 12; + sc_start(50, SC_NS); + + return 0; + +} // sc_main() diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test14/golden/test14.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test14/golden/test14.vcd new file mode 100644 index 000000000..78a2f6ebb --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test14/golden/test14.vcd @@ -0,0 +1,35 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var wire 1 aaaaa clk $end +$scope module mod $end +$var wire 37 aaaab a [36:0] $end +$var wire 1 aaaac port_1 $end +$upscope $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +1aaaaa +b0 aaaab +0aaaac +$end + +#25000 +0aaaaa + +#50000 +1aaaaa +b1100 aaaab +1aaaac + +#75000 +0aaaaa + diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test14/test14.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test14/test14.cpp new file mode 100644 index 000000000..a53fdc6e8 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test14/test14.cpp @@ -0,0 +1,65 @@ + +#include <systemc.h> + +sc_trace_file* sc_tf; + +class Mod : public sc_module +{ + public: + + sc_in_clk clk; + + sc_in<sc_uint<37> > a; + sc_inout<bool > b; + + + + SC_HAS_PROCESS(Mod); + + void foo() + { + cout << sc_time_stamp() << "\n"; + cout << " a = " << a << " b = " << b << "\n"; + cout << "\n"; + return; + } // foo() + + Mod(const sc_module_name& name) : sc_module(name), a("a") + { + SC_METHOD(foo); + sensitive << clk.pos(); + dont_initialize(); + } + + void start_of_simulation() { + + sc_trace(sc_tf, a, a.name()); + sc_trace(sc_tf, b, b.name()); + } + +}; // class Mod + + + + + +int sc_main(int argc, char* argv[]) + +{ + sc_clock clk("clk", 50, SC_NS, 0.5, 0, SC_NS); + sc_signal<sc_uint<37> > a; + sc_signal<bool> b; + sc_tf = sc_create_vcd_trace_file("test14"); + Mod mod("mod"); + mod.clk(clk); + mod.a(a); + mod.b(b); + sc_trace(sc_tf, clk, clk.name()); + sc_start(50, SC_NS); + a = 12; + b = true; + sc_start(50, SC_NS); + return 0; +} // sc_main() + + diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test15/golden/test15.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test15/golden/test15.vcd new file mode 100644 index 000000000..c6c94f7b7 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test15/golden/test15.vcd @@ -0,0 +1,44 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$scope module test_top $end +$var wire 32 aaaaa sig [31:0] $end +$upscope $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars +b10 aaaaa +$end + +#1 +b11 aaaaa + +#2 +b100 aaaaa + +#1002 +b111 aaaaa + +#2002 +b1000 aaaaa + +#3002 +b1001 aaaaa + +#3003 +b1010 aaaaa + +#3005 +b1011 aaaaa + +#4005 +b1100 aaaaa + diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test15/test15.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test15/test15.cpp new file mode 100644 index 000000000..979572423 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test15/test15.cpp @@ -0,0 +1,92 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test15.cpp -- test delta cycle tracing + + Original Author: Romain I Popov, Intel Corporation, 2017-05-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include <systemc.h> + +SC_MODULE(trace_delta_test) +{ + sc_signal <int> sig; + sc_inout<int > iport; + + SC_CTOR(trace_delta_test) + : sig("sig",0) + { + iport.bind(sig); + iport.initialize(1); + SC_THREAD(test_thread); + } + + void test_thread() { + cout << "initial sig value is " << sig.read() << endl; + sig = 2; + wait(SC_ZERO_TIME); + sig = 3; + wait(SC_ZERO_TIME); + sig = 4; + wait(1, SC_PS); + sig = 5; // This won't be shown on delta-cycle enabled trace + wait(1, SC_PS); + sig = 6; // This won't be shown on delta-cycle enabled trace + wait(1, SC_NS); + sig = 7; + wait(1, SC_NS); + sig = 8; + wait(1, SC_NS); + sig = 9; + wait(SC_ZERO_TIME); + sig = 10; + wait(3, SC_PS); + sig = 11; // Ok: 3ps > 2ps delta cycle shift + wait(1, SC_NS); + sig = 12; + + cout << "stop at " << sc_time_stamp() << endl; + sc_stop(); + } + +}; + + +int sc_main(int argc, char **argv) +{ + trace_delta_test test_top("test_top"); + sc_trace_file* tf = sc_create_vcd_trace_file("test15"); + sc_trace_delta_cycles(tf,true); + sc_trace(tf, test_top.sig, test_top.sig.name()); + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test16/golden/test16.vcd b/src/systemc/tests/systemc/tracing/vcd_trace/test16/golden/test16.vcd new file mode 100644 index 000000000..9e5cd34d7 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test16/golden/test16.vcd @@ -0,0 +1,51 @@ + +$timescale + 1 ps +$end + +$scope module SystemC $end +$var event 1 aaaaa event $end +$var time 64 aaaab time [63:0] $end +$upscope $end +$enddefinitions $end + +$comment +All initial values are dumped below at time 0 sec = 0 timescale units. +$end + +$dumpvars + +b0 aaaab +$end + +#1000 +1aaaaa +b1111101000 aaaab + +#2000 +1aaaaa +b11111010000 aaaab + +#3000 +b101110111000 aaaab + +#4000 +1aaaaa +b111110100000 aaaab + +#5000 +1aaaaa +b1001110001000 aaaab + +#6000 +1aaaaa +b1011101110000 aaaab + +#7000 +b1101101011000 aaaab + +#8000 +1aaaaa +b1111101000000 aaaab + +#9000 diff --git a/src/systemc/tests/systemc/tracing/vcd_trace/test16/test16.cpp b/src/systemc/tests/systemc/tracing/vcd_trace/test16/test16.cpp new file mode 100644 index 000000000..40ee45d20 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/vcd_trace/test16/test16.cpp @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test15.cpp -- test event/time tracing + + Original Author: Philipp A Hartmann, Intel Corporation, 2017-08-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include <systemc> +using namespace sc_core; + +SC_MODULE(module) +{ + SC_CTOR(module) + { + SC_THREAD(driver); + SC_METHOD(consumer); + sensitive << event; + dont_initialize(); + } + + void driver() + { + wait(1, SC_NS); + event.notify(); // t == 1ns + + wait(1, SC_NS); + event.notify(SC_ZERO_TIME); // t == 2ns + + wait(1, SC_NS); + event.notify(1, SC_NS); // t == 4ns + time = sc_time_stamp(); + + wait(2, SC_NS); + event.notify(); // t == 5ns + + wait(1, SC_NS); + event.notify(SC_ZERO_TIME); // t == 6ns + + wait(1, SC_NS); + event.notify(1, SC_NS); // t == 8ns + time = sc_time_stamp(); + + wait(2, SC_NS); + } + + void consumer() + { + time = sc_time_stamp(); + } + + sc_event event; + sc_time time; +}; + +int sc_main(int argc, char* argv[]) +{ + sc_trace_file* tf = sc_create_vcd_trace_file("test16"); + + module m("m"); + + sc_trace(tf, m.event, "event"); + sc_trace(tf, m.time, "time"); + + sc_start(); + sc_stop(); + + sc_close_vcd_trace_file(tf); + return 0; +} + + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/mixed/golden/mixed.awif b/src/systemc/tests/systemc/tracing/wif_trace/mixed/golden/mixed.awif new file mode 100644 index 000000000..2444304f7 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/mixed/golden/mixed.awif @@ -0,0 +1,462 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "a" BIT 0 31 variable ; +start_trace O0 ; +declare O1 "b" BIT 0 31 variable ; +start_trace O1 ; +declare O2 "sum" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "clk" BIT variable ; +start_trace O3 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000000000000000000000011110011" ; +assign O1 "00000000000000000100101010001101" ; +assign O2 "00000000000000000000000000000000" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000110011000100010" ; +assign O1 "00000000000000000100110100100001" ; +assign O2 "00000000000000000100101110000000" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000101011001111001" ; +assign O1 "00000000000000000000011011101001" ; +assign O2 "00000000000000001011001101000011" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000010100010110101" ; +assign O1 "00000000000000000001110000100100" ; +assign O2 "00000000000000000101110101100010" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000001111110101111" ; +assign O1 "00000000000000000001110111101111" ; +assign O2 "00000000000000000100010011011001" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000100000111000010" ; +assign O1 "00000000000000000001101011111011" ; +assign O2 "00000000000000000011110110011110" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000011111101110100" ; +assign O1 "00000000000000000011011100011101" ; +assign O2 "00000000000000000101110010111101" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000000111110111101" ; +assign O1 "00000000000000000111010101111010" ; +assign O2 "00000000000000000111011010010001" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000001111000011000" ; +assign O1 "00000000000000000111101000101001" ; +assign O2 "00000000000000001000010100110111" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000110111111111010" ; +assign O1 "00000000000000000111000110111101" ; +assign O2 "00000000000000001001100001000001" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000101111000100100" ; +assign O1 "00000000000000000110101010111001" ; +assign O2 "00000000000000001110000110110111" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000000101110001111" ; +assign O1 "00000000000000000100111110100100" ; +assign O2 "00000000000000001100100011011101" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000110100001101111" ; +assign O1 "00000000000000000100110100001101" ; +assign O2 "00000000000000000101101100110011" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000000101100010111" ; +assign O1 "00000000000000000100111111001110" ; +assign O2 "00000000000000001011010101111100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000111111101111001" ; +assign O1 "00000000000000000101001000001111" ; +assign O2 "00000000000000000101101011100101" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000101100110010100" ; +assign O1 "00000000000000000011000111000100" ; +assign O2 "00000000000000001101000110001000" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000010100100000000" ; +assign O1 "00000000000000000101101000001101" ; +assign O2 "00000000000000001000101101011000" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000100110001111011" ; +assign O1 "00000000000000000000111010011001" ; +assign O2 "00000000000000001000001100001101" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000111101101101111" ; +assign O1 "00000000000000000111011000100111" ; +assign O2 "00000000000000000101101100010100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000001111010101110" ; +assign O1 "00000000000000000001110011010111" ; +assign O2 "00000000000000001111000110010110" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000110101110010100" ; +assign O1 "00000000000000000010000101011000" ; +assign O2 "00000000000000000011101110000101" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000100111010000001" ; +assign O1 "00000000000000000010010011011110" ; +assign O2 "00000000000000001000110011101100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000111011101001101" ; +assign O1 "00000000000000000001001100001010" ; +assign O2 "00000000000000000111001101011111" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000101010001110110" ; +assign O1 "00000000000000000111101010111110" ; +assign O2 "00000000000000001000101001010111" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000100100010101110" ; +assign O1 "00000000000000000101001001010100" ; +assign O2 "00000000000000001100111100110100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000000000011101010" ; +assign O1 "00000000000000000101111010101101" ; +assign O2 "00000000000000001001101100000010" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000001100000010000" ; +assign O1 "00000000000000000011111011101010" ; +assign O2 "00000000000000000101111110010111" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000111011001111011" ; +assign O1 "00000000000000000001011000111011" ; +assign O2 "00000000000000000101011011111010" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000000000101101101" ; +assign O1 "00000000000000000111111010111111" ; +assign O2 "00000000000000001000110010110110" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000110111001010110" ; +assign O1 "00000000000000000011110111110001" ; +assign O2 "00000000000000001000000000101100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000000111000000100" ; +assign O1 "00000000000000000011010001111101" ; +assign O2 "00000000000000001010110001000111" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000101100010101011" ; +assign O1 "00000000000000000011111110001011" ; +assign O2 "00000000000000000100001010000001" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000001101000111001" ; +assign O1 "00000000000000000000001001011111" ; +assign O2 "00000000000000001001100000110110" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000101100101111110" ; +assign O1 "00000000000000000010010100010110" ; +assign O2 "00000000000000000001110010011000" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000111010000001100" ; +assign O1 "00000000000000000110100111100100" ; +assign O2 "00000000000000000111111010010100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000010100111101101" ; +assign O1 "00000000000000000000101001001111" ; +assign O2 "00000000000000001101110111110000" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000001111111010000" ; +assign O1 "00000000000000000110010110110100" ; +assign O2 "00000000000000000011010000111100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000100000001101101" ; +assign O1 "00000000000000000010000011011011" ; +assign O2 "00000000000000001000010110000100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000001100000110010" ; +assign O1 "00000000000000000000001011010101" ; +assign O2 "00000000000000000110000101001000" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000111111100000010" ; +assign O1 "00000000000000000010110101101110" ; +assign O2 "00000000000000000001101100000111" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000100100110110010" ; +assign O1 "00000000000000000101110100101001" ; +assign O2 "00000000000000001010110001110000" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000001010010111110" ; +assign O1 "00000000000000000000010101000110" ; +assign O2 "00000000000000001010011011011011" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000010001000111100" ; +assign O1 "00000000000000000001110010011010" ; +assign O2 "00000000000000000001101000000100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000011101011110001" ; +assign O1 "00000000000000000100001100100011" ; +assign O2 "00000000000000000011111011010110" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000010110100010100" ; +assign O1 "00000000000000000011000100000001" ; +assign O2 "00000000000000000111111000010100" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000011000110011011" ; +assign O1 "00000000000000000110110101010100" ; +assign O2 "00000000000000000101111000010101" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000000000100100100" ; +assign O1 "00000000000000000000110110111010" ; +assign O2 "00000000000000001001111011101111" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000101100111010101" ; +assign O1 "00000000000000000110110001001001" ; +assign O2 "00000000000000000000111011011110" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000000011011000110" ; +assign O1 "00000000000000000110001010101100" ; +assign O2 "00000000000000001100011000011110" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + +delta_time 10000 ; +assign O0 "00000000000000000001100101110001" ; +assign O1 "00000000000000000111101111001100" ; +assign O2 "00000000000000000110100101110010" ; +assign O3 '1' ; + +delta_time 10000 ; +assign O3 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/mixed/isaac.h b/src/systemc/tests/systemc/tracing/wif_trace/mixed/isaac.h new file mode 100644 index 000000000..9625be2ac --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/mixed/isaac.h @@ -0,0 +1,272 @@ +#ifndef __ISAAC_HPP +#define __ISAAC_HPP + + +/* + + C++ TEMPLATE VERSION OF Robert J. Jenkins Jr.'s + ISAAC Random Number Generator. + + Ported from vanilla C to to template C++ class + by Quinn Tyler Jackson on 16-23 July 1998. + + quinn@qtj.net + + The function for the expected period of this + random number generator, according to Jenkins is: + + f(a,b) = 2**((a+b*(3+2^^a)-1) + + (where a is ALPHA and b is bitwidth) + + So, for a bitwidth of 32 and an ALPHA of 8, + the expected period of ISAAC is: + + 2^^(8+32*(3+2^^8)-1) = 2^^8295 + + Jackson has been able to run implementations + with an ALPHA as high as 16, or + + 2^^2097263 + +*/ + + +typedef unsigned int UINT32; +const UINT32 GOLDEN_RATIO = UINT32(0x9e3779b9); + + +template <UINT32 ALPHA = (8)> +class QTIsaac +{ + public: + + typedef unsigned char byte; + + struct randctx + { + randctx(void) + { + randrsl = new UINT32[N]; + randmem = new UINT32[N]; + } + + ~randctx(void) + { + delete [] randrsl; + delete [] randmem; + } + + UINT32 randcnt; + UINT32* randrsl; + UINT32* randmem; + UINT32 randa; + UINT32 randb; + UINT32 randc; + }; + + QTIsaac(UINT32 a = 0, UINT32 b = 0, UINT32 c = 0); + virtual ~QTIsaac(void); + + UINT32 rand(void); + virtual void randinit(randctx* ctx, bool bUseSeed); + virtual void srand( + UINT32 a = 0, UINT32 b = 0, UINT32 c = 0, UINT32* s = NULL); + + enum {N = (1<<ALPHA)}; + + protected: + + virtual void isaac(randctx* ctx); + + UINT32 ind(UINT32* mm, UINT32 x); + void rngstep( + UINT32 mix, UINT32& a, UINT32& b, UINT32*& mm, UINT32*& m, + UINT32*& m2, UINT32*& r, UINT32& x, UINT32& y); + virtual void shuffle( + UINT32& a, UINT32& b, UINT32& c, UINT32& d, UINT32& e, UINT32& f, + UINT32& g, UINT32& h); + + private: + randctx m_rc; +}; + + +template<UINT32 ALPHA> +QTIsaac<ALPHA>::QTIsaac(UINT32 a, UINT32 b, UINT32 c) : m_rc() +{ + srand(a, b, c); +} + + +template<UINT32 ALPHA> +QTIsaac<ALPHA>::~QTIsaac(void) +{ + // DO NOTHING +} + + +template<UINT32 ALPHA> +void QTIsaac<ALPHA>::srand(UINT32 a, UINT32 b, UINT32 c, UINT32* s) +{ + for(int i = 0; i < N; i++) + { + m_rc.randrsl[i] = s != NULL ? s[i] : 0; + } + + m_rc.randa = a; + m_rc.randb = b; + m_rc.randc = c; + + randinit(&m_rc, true); +} + + +template<UINT32 ALPHA> +inline UINT32 QTIsaac<ALPHA>::rand(void) +{ + return 0x7fffffff & (!m_rc.randcnt-- ? + (isaac(&m_rc), m_rc.randcnt=(N-1), m_rc.randrsl[m_rc.randcnt]) : + m_rc.randrsl[m_rc.randcnt]); +} + + +template<UINT32 ALPHA> +inline void QTIsaac<ALPHA>::randinit(randctx* ctx, bool bUseSeed) +{ + UINT32 a,b,c,d,e,f,g,h; + int i; + + a = b = c = d = e = f = g = h = GOLDEN_RATIO; + + UINT32* m = (ctx->randmem); + UINT32* r = (ctx->randrsl); + + if(!bUseSeed) + { + ctx->randa = 0; + ctx->randb = 0; + ctx->randc = 0; + } + + // scramble it + for(i=0; i < 4; ++i) + { + shuffle(a,b,c,d,e,f,g,h); + } + + if(bUseSeed) + { + // initialize using the contents of r[] as the seed + + for(i=0; i < N; i+=8) + { + a+=r[i ]; b+=r[i+1]; c+=r[i+2]; d+=r[i+3]; + e+=r[i+4]; f+=r[i+5]; g+=r[i+6]; h+=r[i+7]; + + shuffle(a,b,c,d,e,f,g,h); + + m[i ]=a; m[i+1]=b; m[i+2]=c; m[i+3]=d; + m[i+4]=e; m[i+5]=f; m[i+6]=g; m[i+7]=h; + } + + //do a second pass to make all of the seed affect all of m + + for(i=0; i < N; i += 8) + { + a+=m[i ]; b+=m[i+1]; c+=m[i+2]; d+=m[i+3]; + e+=m[i+4]; f+=m[i+5]; g+=m[i+6]; h+=m[i+7]; + + shuffle(a,b,c,d,e,f,g,h); + + m[i ]=a; m[i+1]=b; m[i+2]=c; m[i+3]=d; + m[i+4]=e; m[i+5]=f; m[i+6]=g; m[i+7]=h; + } + } + else + { + // fill in mm[] with messy stuff + + shuffle(a,b,c,d,e,f,g,h); + + m[i ]=a; m[i+1]=b; m[i+2]=c; m[i+3]=d; + m[i+4]=e; m[i+5]=f; m[i+6]=g; m[i+7]=h; + + } + + isaac(ctx); // fill in the first set of results + ctx->randcnt = N; // prepare to use the first set of results +} + + +template<UINT32 ALPHA> +inline UINT32 QTIsaac<ALPHA>::ind(UINT32* mm, UINT32 x) +{ + return (*(UINT32*)((byte*)(mm) + ((x) & ((N-1)<<2)))); +} + + +template<UINT32 ALPHA> +inline void QTIsaac<ALPHA>::rngstep(UINT32 mix, UINT32& a, UINT32& b, UINT32*& mm, UINT32*& m, UINT32*& m2, UINT32*& r, UINT32& x, UINT32& y) +{ + x = *m; + a = (a^(mix)) + *(m2++); + *(m++) = y = ind(mm,x) + a + b; + *(r++) = b = ind(mm,y>>ALPHA) + x; +} + + +template<UINT32 ALPHA> +inline void QTIsaac<ALPHA>::shuffle(UINT32& a, UINT32& b, UINT32& c, UINT32& d, UINT32& e, UINT32& f, UINT32& g, UINT32& h) +{ + a^=b<<11; d+=a; b+=c; + b^=c>>2; e+=b; c+=d; + c^=d<<8; f+=c; d+=e; + d^=e>>16; g+=d; e+=f; + e^=f<<10; h+=e; f+=g; + f^=g>>4; a+=f; g+=h; + g^=h<<8; b+=g; h+=a; + h^=a>>9; c+=h; a+=b; +} + + +template<UINT32 ALPHA> +inline void QTIsaac<ALPHA>::isaac(randctx* ctx) +{ + UINT32 x,y; + + UINT32* mm = ctx->randmem; + UINT32* r = ctx->randrsl; + + UINT32 a = (ctx->randa); + UINT32 b = (ctx->randb + (++ctx->randc)); + + UINT32* m = mm; + UINT32* m2 = (m+(N/2)); + UINT32* mend = m2; + + for(; m<mend; ) + { + rngstep((a<<13), a, b, mm, m, m2, r, x, y); + rngstep((a>>6) , a, b, mm, m, m2, r, x, y); + rngstep((a<<2) , a, b, mm, m, m2, r, x, y); + rngstep((a>>16), a, b, mm, m, m2, r, x, y); + } + + m2 = mm; + + for(; m2<mend; ) + { + rngstep((a<<13), a, b, mm, m, m2, r, x, y); + rngstep((a>>6) , a, b, mm, m, m2, r, x, y); + rngstep((a<<2) , a, b, mm, m, m2, r, x, y); + rngstep((a>>16), a, b, mm, m, m2, r, x, y); + } + + ctx->randb = b; + ctx->randa = a; +} + + +#endif // __ISAAC_HPP + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/mixed/mixed.cpp b/src/systemc/tests/systemc/tracing/wif_trace/mixed/mixed.cpp new file mode 100644 index 000000000..bb52e29d9 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/mixed/mixed.cpp @@ -0,0 +1,129 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + mixed.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "isaac.h" + +QTIsaac<8> rng; + +SC_MODULE( adder ) +{ + SC_HAS_PROCESS( adder ); + + sc_in<bool> clk; + sc_in<int> a; + sc_in<int> b; + sc_out<int> sum; + + adder( sc_module_name NAME, + sc_clock& CLK, + sc_signal<int>& A, + sc_signal<int>& B, + sc_signal<int>& SUM ) + : a(A), b(B), sum(SUM) + { + clk(CLK); + SC_METHOD( entry ); + sensitive << clk; + sensitive << a; + sensitive << b; + } + void entry(); +}; + +void +adder::entry() +{ + if (clk.posedge()) { + sum = a + b; + } +} + +SC_MODULE( stim ) +{ + SC_HAS_PROCESS( stim ); + + sc_in_clk clk; + sc_out<int> a; + sc_out<int> b; + + stim( sc_module_name NAME, + sc_clock& CLK, + sc_signal<int>& A, + sc_signal<int>& B ) + : a(A), b(B) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + void entry(); +}; + +void +stim::entry() +{ + while (true) { + a = rng.rand() % 32768; + b = rng.rand() % 32768; + wait(); + } +} + +int +sc_main( int argc, char* argv[] ) +{ + sc_signal<int> a("a"); + sc_signal<int> b("b"); + sc_signal<int> sum("sum"); + sc_clock clk("clk", 20, SC_NS); + + a = 0; + b = 0; + sum = 0; + + adder add("add", clk, a, b, sum); + stim sti("sti", clk, a, b); + + sc_trace_file* tf = sc_create_wif_trace_file("mixed"); + sc_trace(tf, a, "a"); + sc_trace(tf, b, "b"); + sc_trace(tf, sum, "sum"); + sc_trace(tf, clk, "clk"); + sc_start(1000, SC_NS); + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/pct1/golden/pct1.awif b/src/systemc/tests/systemc/tracing/wif_trace/pct1/golden/pct1.awif new file mode 100644 index 000000000..354800e3d --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/pct1/golden/pct1.awif @@ -0,0 +1,81 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Tx" BIT variable ; +start_trace O0 ; +declare O1 "dout" BIT 0 31 variable ; +start_trace O1 ; +declare O2 "wr" BIT variable ; +start_trace O2 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 '1' ; +assign O1 "00000000000000000000000000000000" ; +assign O2 '1' ; + +delta_time 50000 ; +assign O0 '0' ; + +delta_time 20000 ; +assign O0 '1' ; + +delta_time 10000 ; +assign O0 '0' ; + +delta_time 10000 ; +assign O0 '1' ; + +delta_time 20000 ; +assign O0 '0' ; + +delta_time 10000 ; +assign O0 '1' ; + +delta_time 10000 ; +assign O0 '0' ; + +delta_time 20000 ; +assign O0 '1' ; + +delta_time 20000 ; +assign O0 '0' ; + +delta_time 10000 ; +assign O0 '1' ; + +delta_time 80000 ; +assign O0 '0' ; + +delta_time 10000 ; +assign O0 '1' ; + +delta_time 30000 ; +assign O0 '0' ; + +delta_time 10000 ; +assign O0 '1' ; + +delta_time 20000 ; +assign O0 '0' ; + +delta_time 10000 ; +assign O0 '1' ; + +delta_time 10000 ; +assign O0 '0' ; + +delta_time 10000 ; +assign O0 '1' ; + +delta_time 10000 ; +assign O0 '0' ; + +delta_time 10000 ; +assign O0 '1' ; + +delta_time 90000 ; +assign O0 '0' ; + +delta_time 20000 ; +assign O0 '1' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/pct1/main.cpp b/src/systemc/tests/systemc/tracing/wif_trace/pct1/main.cpp new file mode 100644 index 000000000..bb8807add --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/pct1/main.cpp @@ -0,0 +1,69 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + main.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Main routine for tri-state simulation */ + +#include "tx.h" +#include "monitor.h" + +int sc_main(int ac, char *av[]) +{ + sc_signal<bool> tx; + sc_signal<bool> wr; + sc_signal<int> dout; + sc_signal<bool> two_stop_bits; + sc_clock clock("CLK", 10.0, SC_NS, 0.5, 0.0, SC_NS); + sc_trace_file *tf = sc_create_wif_trace_file("pct1"); + + tx = true; + wr = true; + dout = 0; + + two_stop_bits = true; + sio_tx TX("Transmitter", clock, two_stop_bits, tx); + monitor MON("Monitor", clock, tx, dout, wr); + + // sc_trace(tf, clock.signal(), "Clock"); + sc_trace(tf, tx, "Tx"); + sc_trace(tf, dout, "dout"); + sc_trace(tf, wr, "wr"); + + sc_start(500, SC_NS); + sc_close_wif_trace_file( tf ); + return 0; +} + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/pct1/monitor.cpp b/src/systemc/tests/systemc/tracing/wif_trace/pct1/monitor.cpp new file mode 100644 index 000000000..9e8f68c6e --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/pct1/monitor.cpp @@ -0,0 +1,49 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "monitor.h" + +void monitor::entry() +{ + int n=0; + + while(1) { + printf("%x", tx.read()); + wait(); + } +} // end of entry function + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/pct1/monitor.h b/src/systemc/tests/systemc/tracing/wif_trace/pct1/monitor.h new file mode 100644 index 000000000..1c37a3b28 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/pct1/monitor.h @@ -0,0 +1,63 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + monitor.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( monitor ) +{ + SC_HAS_PROCESS( monitor ); + + sc_in_clk clk; + sc_in<bool> tx; + sc_in<int> dout; + sc_in<bool> wr; + + // Constructor + monitor( sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& TX, + sc_signal<int>& DOUT, + sc_signal<bool>& WR ) + : tx(TX), dout(DOUT), wr(WR) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + // Process functionality in member function below + void entry(); +}; diff --git a/src/systemc/tests/systemc/tracing/wif_trace/pct1/pct1.f b/src/systemc/tests/systemc/tracing/wif_trace/pct1/pct1.f new file mode 100644 index 000000000..4c3ccdbdb --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/pct1/pct1.f @@ -0,0 +1,3 @@ +pct1/main.cpp +pct1/monitor.cpp +pct1/tx.cpp diff --git a/src/systemc/tests/systemc/tracing/wif_trace/pct1/tx.cpp b/src/systemc/tests/systemc/tracing/wif_trace/pct1/tx.cpp new file mode 100644 index 000000000..d868d2402 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/pct1/tx.cpp @@ -0,0 +1,98 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tx.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename driver.cc */ +/* This is a SIO transmitter */ + +#include "tx.h" + +void sio_tx::byte (char c) +{ + bool parity = false; + int n; + + // Start bit + tx.write(false); + wait(); + + // 8 data bits + for (n=0; n<8; n++) { + if (c & 0x1) parity=!parity; + tx.write (c & 0x1); + c = c >>1; + wait(); + } + + // parity bit + tx.write(parity); + wait(); + + // stop bits; + if (two_stop_bits) { + tx.write(true); + wait(); + tx.write(true); + wait(); + } else { + tx.write(true); + wait(); + } +} // end of entry function + + +void sio_tx::mark (int cycles) +{ + int n; + + for (n=0; n<cycles; n++) { + tx.write(true); + wait(); + } +} + + +void sio_tx::entry() +{ + while (1) { + mark(5); + byte((char)0x5a); + byte((char)0xff); + mark(1); + byte((char)0xab); + } +} // end of entry function + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/pct1/tx.h b/src/systemc/tests/systemc/tracing/wif_trace/pct1/tx.h new file mode 100644 index 000000000..de1e11469 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/pct1/tx.h @@ -0,0 +1,66 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + tx.h -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +/* Filename tx.h */ +/* This is a SIO transmitter */ + +#include "systemc.h" + +SC_MODULE( sio_tx ) +{ + SC_HAS_PROCESS( sio_tx ); + + sc_in_clk clk; + sc_in<bool> two_stop_bits; + sc_out<bool> tx; + + // Constructor + sio_tx( sc_module_name NAME, + sc_clock& CLK, + sc_signal<bool>& TWO_STOP_BITS, + sc_signal<bool>& TX ) + : two_stop_bits(TWO_STOP_BITS), tx(TX) + { + clk(CLK); + SC_CTHREAD( entry, clk.pos() ); + } + + // Process functionality in member function below + void entry(); + void byte (char byte); + void mark(int cycles); +}; diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test01/golden/test01.awif b/src/systemc/tests/systemc/tracing/wif_trace/test01/golden/test01.awif new file mode 100644 index 000000000..0b2dc346c --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test01/golden/test01.awif @@ -0,0 +1,141 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Bool" BIT variable ; +start_trace O0 ; +declare O1 "SC_Logic" MVL variable ; +start_trace O1 ; +declare O2 "SC_BV" BIT 0 3 variable ; +start_trace O2 ; +declare O3 "SC_LV" MVL 0 3 variable ; +start_trace O3 ; +declare O4 "Clock" BIT variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 '0' ; +assign O1 '1' ; +assign O2 "0000" ; +assign O3 "1111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 '0' ; +assign O2 "1010" ; +assign O3 "1011" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "0101" ; +assign O3 "0101" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 '1' ; +assign O2 "0000" ; +assign O3 "1111" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 '0' ; +assign O2 "1010" ; +assign O3 "1011" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "0110" ; +assign O3 "0110" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 '1' ; +assign O2 "0000" ; +assign O3 "1111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 '0' ; +assign O2 "1010" ; +assign O3 "1011" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "0111" ; +assign O3 "0111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 '1' ; +assign O2 "0000" ; +assign O3 "1111" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 '0' ; +assign O2 "1010" ; +assign O3 "1011" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "1000" ; +assign O3 "1000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 '1' ; +assign O2 "0000" ; +assign O3 "1111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 '0' ; +assign O2 "1010" ; +assign O3 "1011" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "1001" ; +assign O3 "1001" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 '1' ; +assign O2 "0000" ; +assign O3 "1111" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 '0' ; +assign O2 "1010" ; +assign O3 "1011" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O3 "1010" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 '1' ; +assign O2 "0000" ; +assign O3 "1111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 '0' ; +assign O2 "1010" ; +assign O3 "1011" ; +assign O4 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test01/test01.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test01/test01.cpp new file mode 100644 index 000000000..0ad3a2913 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test01/test01.cpp @@ -0,0 +1,118 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test01.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + bool obj1; + sc_logic obj2; + sc_bv<4> obj3; + sc_lv<4> obj4; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = "0000"; + obj4 = "0000"; + } + + void entry(); +}; + +void proc1::entry() +{ + sc_bv<4> bv; + sc_lv<4> sv; + int i = 5; + wait(); + while(true) { + bv = i; + sv = i++; + obj1 = 0; + obj2 = 1; + obj3 = "0000"; + obj4 = "1111"; + wait(); + obj1 = 1; + obj2 = 0; + obj3 = "1010"; + obj4 = "1011"; + wait(); + obj3 = bv; + obj4 = sv; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_wif_trace_file("test01"); + tf->set_time_unit( 1, SC_PS ); + // @@@@ ((wif_trace_file *) tf)->sc_set_wif_time_unit(-12); + sc_trace(tf, P1.obj1, "Bool"); + sc_trace(tf, P1.obj2, "SC_Logic"); + sc_trace(tf, P1.obj3, "SC_BV"); + sc_trace(tf, P1.obj4, "SC_LV"); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif new file mode 100644 index 000000000..3d1de26fd --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif @@ -0,0 +1,154 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 31 variable ; +start_trace O3 ; +declare O4 "Clock" BIT variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "00000000000000000000100000000000" ; +assign O4 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.bsd64 b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.bsd64 new file mode 100644 index 000000000..e6673ef1e --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.bsd64 @@ -0,0 +1,154 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Clock" BIT variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.cygwin64 b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.cygwin64 new file mode 100644 index 000000000..e6673ef1e --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.cygwin64 @@ -0,0 +1,154 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Clock" BIT variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.linux64 b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.linux64 new file mode 100644 index 000000000..e6673ef1e --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.linux64 @@ -0,0 +1,154 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Clock" BIT variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.linuxaarch64 b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.linuxaarch64 new file mode 100644 index 000000000..e6673ef1e --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.linuxaarch64 @@ -0,0 +1,154 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Clock" BIT variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.macosx64 b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.macosx64 new file mode 100644 index 000000000..e6673ef1e --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test02/golden/test02.awif.macosx64 @@ -0,0 +1,154 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Clock" BIT variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "00000000000000000000001111111111" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "0000000000100000" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000100000000000" ; +assign O4 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test02/test02.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test02/test02.cpp new file mode 100644 index 000000000..ed861481a --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test02/test02.cpp @@ -0,0 +1,108 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test02.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + unsigned char obj1; + unsigned short obj2; + unsigned int obj3; + unsigned long obj4; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = 0; + obj4 = 0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 7; + obj2 = 31; + obj3 = 1023; + obj4 = 2047; + wait(); + obj1 = 1; + obj2 = 32; + obj3 = 1024; + obj4 = 2048; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_wif_trace_file("test02"); + sc_trace(tf, P1.obj1, "Char"); + sc_trace(tf, P1.obj2, "Short"); + sc_trace(tf, P1.obj3, "Int"); + sc_trace(tf, P1.obj4, "Long"); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test03/golden/test03.awif b/src/systemc/tests/systemc/tracing/wif_trace/test03/golden/test03.awif new file mode 100644 index 000000000..749f0e6ce --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test03/golden/test03.awif @@ -0,0 +1,176 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 3 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 3 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 11 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 9 variable ; +start_trace O3 ; +declare O4 "Uint64" BIT 0 42 variable ; +start_trace O4 ; +declare O5 "Clock" BIT variable ; +start_trace O5 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "0000" ; +assign O2 "001111111111" ; +assign O3 "0000111111" ; +assign O4 "1000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "0011" ; +assign O2 "010000000000" ; +assign O3 "0000000000" ; +assign O4 "0000000000000000000000000000000000000000000" ; +assign O5 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test03/test03.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test03/test03.cpp new file mode 100644 index 000000000..9d58baffe --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test03/test03.cpp @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test03.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + unsigned char obj1; + unsigned short obj2; + unsigned int obj3; + unsigned long obj4; + uint64 obj5; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = 0; + obj4 = 0; + obj5 = 0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 7; + obj2 = 31; + obj3 = 1023; + obj4 = 63; + obj5 = 1; + obj5 = obj5 << 42; + wait(); + obj1 = 1; + obj2 = 3; + obj3 = 1024; + obj4 = 2048; + obj5 = 3; + obj5 = obj5 << 42; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_wif_trace_file("test03"); + sc_trace(tf, P1.obj1, "Char", 4); + sc_trace(tf, P1.obj2, "Short", 4); + sc_trace(tf, P1.obj3, "Int", 12); + sc_trace(tf, P1.obj4, "Long", 10); + sc_trace(tf, P1.obj5, "Uint64", 43); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif new file mode 100644 index 000000000..a236147e6 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif @@ -0,0 +1,176 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 31 variable ; +start_trace O3 ; +declare O4 "Int64" BIT 0 63 variable ; +start_trace O4 ; +declare O5 "Clock" BIT variable ; +start_trace O5 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "00000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "11111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.bsd64 b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.bsd64 new file mode 100644 index 000000000..41866c731 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.bsd64 @@ -0,0 +1,183 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Int64" BIT 0 63 variable ; +start_trace O4 ; +declare O5 "Clock" BIT variable ; +start_trace O5 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000000" ; +assign O1 "0000000000000000" ; +assign O2 "00000000000000000000000000000000" ; +assign O3 "0000000000000000000000000000000000000000000000000000000000000000" ; +assign O4 "0000000000000000000000000000000000000000000000000000000000000000" ; +assign O5 '0' ; +delta_time 0 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.cygwin64 b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.cygwin64 new file mode 100644 index 000000000..d113ab0bc --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.cygwin64 @@ -0,0 +1,176 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Int64" BIT 0 63 variable ; +start_trace O4 ; +declare O5 "Clock" BIT variable ; +start_trace O5 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.linux64 b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.linux64 new file mode 100644 index 000000000..d113ab0bc --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.linux64 @@ -0,0 +1,176 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Int64" BIT 0 63 variable ; +start_trace O4 ; +declare O5 "Clock" BIT variable ; +start_trace O5 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.linuxaarch64 b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.linuxaarch64 new file mode 100644 index 000000000..d113ab0bc --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.linuxaarch64 @@ -0,0 +1,176 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Int64" BIT 0 63 variable ; +start_trace O4 ; +declare O5 "Clock" BIT variable ; +start_trace O5 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.macosx64 b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.macosx64 new file mode 100644 index 000000000..d113ab0bc --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test04/golden/test04.awif.macosx64 @@ -0,0 +1,176 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 7 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 15 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 31 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 63 variable ; +start_trace O3 ; +declare O4 "Int64" BIT 0 63 variable ; +start_trace O4 ; +declare O5 "Clock" BIT variable ; +start_trace O5 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "00000111" ; +assign O1 "0000000000011111" ; +assign O2 "11111111111111111111110000000001" ; +assign O3 "0000000000000000000000000000000000000000000000000000011111111111" ; +assign O4 "0000000000000000000000001111111111111111111111111111111111111111" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "00000001" ; +assign O1 "1111111111111110" ; +assign O2 "00000000000000000000010000000000" ; +assign O3 "1111111111111111111111111111111111111111111111111111100000000000" ; +assign O4 "1111111111111111111111110000000000000000000000000000000000000000" ; +assign O5 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test04/test04.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test04/test04.cpp new file mode 100644 index 000000000..3cab6fddb --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test04/test04.cpp @@ -0,0 +1,114 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test04.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + char obj1; + short obj2; + int obj3; + long obj4; + int64 obj5; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = 0; + obj4 = 0; + obj5 = 0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 7; + obj2 = 31; + obj3 = -1023; + obj4 = 2047; + obj5 = -1; + obj5 = ~(obj5 << 40); + wait(); + obj1 = 1; + obj2 = -2; + obj3 = 1024; + obj4 = -2048; + obj5 = -(obj5+1); + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_wif_trace_file("test04"); + sc_trace(tf, P1.obj1, "Char"); + sc_trace(tf, P1.obj2, "Short"); + sc_trace(tf, P1.obj3, "Int"); + sc_trace(tf, P1.obj4, "Long"); + sc_trace(tf, P1.obj5, "Int64"); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test05/golden/test05.awif b/src/systemc/tests/systemc/tracing/wif_trace/test05/golden/test05.awif new file mode 100644 index 000000000..38b76b2c1 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test05/golden/test05.awif @@ -0,0 +1,176 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Char" BIT 0 3 variable ; +start_trace O0 ; +declare O1 "Short" BIT 0 11 variable ; +start_trace O1 ; +declare O2 "Int" BIT 0 13 variable ; +start_trace O2 ; +declare O3 "Long" BIT 0 13 variable ; +start_trace O3 ; +declare O4 "Int64" BIT 0 43 variable ; +start_trace O4 ; +declare O5 "Clock" BIT variable ; +start_trace O5 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + +delta_time 10000 ; +assign O0 "0111" ; +assign O1 "000000011111" ; +assign O2 "00000000000000" ; +assign O3 "00011111111111" ; +assign O4 "00000000000000000000000000000000000000000000" ; +assign O5 '1' ; + +delta_time 10000 ; +assign O0 "0001" ; +assign O1 "000000000000" ; +assign O2 "00010000000000" ; +assign O3 "00000000000000" ; +assign O4 "01110000000000000000000000000000000000000000" ; +assign O5 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test05/test05.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test05/test05.cpp new file mode 100644 index 000000000..c84d0fd42 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test05/test05.cpp @@ -0,0 +1,115 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test05.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + char obj1; + short obj2; + int obj3; + long obj4; + int64 obj5; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = 0; + obj4 = 0; + obj5 = 0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 7; + obj2 = 31; + obj3 = -1023; + obj4 = 2047; + obj5 = -1; + obj5 = obj5 << 40; + wait(); + obj1 = 1; + obj2 = -2; + obj3 = 1024; + obj4 = -2048; + obj5 = 7; + obj5 = obj5 << 40; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_wif_trace_file("test05"); + sc_trace(tf, P1.obj1, "Char", 4); + sc_trace(tf, P1.obj2, "Short", 12); + sc_trace(tf, P1.obj3, "Int", 14); + sc_trace(tf, P1.obj4, "Long", 14); + sc_trace(tf, P1.obj5, "Int64", 44); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test06/golden/test06.awif b/src/systemc/tests/systemc/tracing/wif_trace/test06/golden/test06.awif new file mode 100644 index 000000000..862c64add --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test06/golden/test06.awif @@ -0,0 +1,88 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Float" real variable ; +start_trace O0 ; +declare O1 "Double" real variable ; +start_trace O1 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + +delta_time 10000 ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + +delta_time 10000 ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + +delta_time 10000 ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + +delta_time 10000 ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + +delta_time 10000 ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + +delta_time 10000 ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + +delta_time 10000 ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + +delta_time 10000 ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + +delta_time 10000 ; +assign O0 12.345000 ; +assign O1 -13.567892 ; + +delta_time 10000 ; +assign O0 -182634880.000000 ; +assign O1 1672357.298346 ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test06/test06.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test06/test06.cpp new file mode 100644 index 000000000..d02147af5 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test06/test06.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test06.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + float obj1; + double obj2; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0.0; + obj2 = 0.0; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 12.345; + obj2 = -13.5678923; + wait(); + obj1 = -182634876.5659374; + obj2 = 1672357.298346; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_wif_trace_file("test06"); + sc_trace(tf, P1.obj1, "Float"); + sc_trace(tf, P1.obj2, "Double"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test07/golden/test07.awif b/src/systemc/tests/systemc/tracing/wif_trace/test07/golden/test07.awif new file mode 100644 index 000000000..585b806b1 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test07/golden/test07.awif @@ -0,0 +1,132 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Signed" BIT 0 3 variable ; +start_trace O0 ; +declare O1 "Unsigned" BIT 0 3 variable ; +start_trace O1 ; +declare O2 "BV" BIT 0 3 variable ; +start_trace O2 ; +declare O3 "SV" MVL 0 3 variable ; +start_trace O3 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + +delta_time 10000 ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + +delta_time 10000 ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + +delta_time 10000 ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + +delta_time 10000 ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + +delta_time 10000 ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + +delta_time 10000 ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + +delta_time 10000 ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + +delta_time 10000 ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + +delta_time 10000 ; +assign O0 "0011" ; +assign O1 "0111" ; +assign O2 "0011" ; +assign O3 "1100" ; + +delta_time 10000 ; +assign O0 "1101" ; +assign O1 "0101" ; +assign O2 "1111" ; +assign O3 "1110" ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test07/test07.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test07/test07.cpp new file mode 100644 index 000000000..61cf796de --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test07/test07.cpp @@ -0,0 +1,112 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test07.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + sc_signal<sc_bv<4> >& bv; + sc_signal<sc_lv<4> >& sv; + + sc_signed obj1; + sc_unsigned obj2; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK, + sc_signal<sc_bv<4> >& BV, + sc_signal<sc_lv<4> >& SV ) + : bv(BV), sv(SV), obj1(4), obj2(4) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + bv = "0000"; + sv = "0000"; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = 3; + obj2 = 7; + bv = "0011"; + sv = "1100"; + wait(); + obj1 = -3; + obj2 = 5; + bv = "1111"; + sv = "1110"; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + sc_signal<sc_bv<4> > bv; + sc_signal<sc_lv<4> > sv; + + proc1 P1("P1", clock, bv, sv); + + tf = sc_create_wif_trace_file("test07"); + sc_trace(tf, P1.obj1, "Signed"); + sc_trace(tf, P1.obj2, "Unsigned"); + sc_trace(tf, bv, "BV"); + sc_trace(tf, sv, "SV"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test08/golden/test08.awif b/src/systemc/tests/systemc/tracing/wif_trace/test08/golden/test08.awif new file mode 100644 index 000000000..73faefe3d --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test08/golden/test08.awif @@ -0,0 +1,154 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Clock" BIT variable ; +start_trace O0 ; +declare O1 "Int" BIT 0 31 variable ; +start_trace O1 ; +declare O2 "Char" BIT 0 7 variable ; +start_trace O2 ; +declare O3 "Float" real variable ; +start_trace O3 ; +declare O4 "Logic" MVL variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test08/test08.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test08/test08.cpp new file mode 100644 index 000000000..23acc6f8b --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test08/test08.cpp @@ -0,0 +1,116 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test08.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + sc_signal<int>& Isig; + sc_signal<char>& Csig; + sc_signal<float>& Fsig; + sc_signal<sc_logic>& Lsig; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK, + sc_signal<int>& ISIG, + sc_signal<char>& CSIG, + sc_signal<float>& FSIG, + sc_signal<sc_logic>& LSIG ) + : Isig(ISIG), Csig(CSIG), Fsig(FSIG), Lsig(LSIG) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + Isig = 0; + Csig = 0; + Fsig = 0.0; + Lsig = SC_LOGIC_0;//'0'; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + Isig = 1023; + Csig = 15; + Fsig = -4; + Lsig = SC_LOGIC_X;//'x'; + wait(); + Isig = 10; + Csig = 8; + Fsig = 1000.23456; + Lsig = SC_LOGIC_Z;//'z'; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + sc_signal<int> I; + sc_signal<char> C; + sc_signal<float> F; + sc_signal<sc_logic> L; + + proc1 P1("P1", clock, I, C, F, L); + + tf = sc_create_wif_trace_file("test08"); + sc_trace(tf, clock, "Clock"); + sc_trace(tf, I, "Int", 32); + sc_trace(tf, C, "Char", 8); + sc_trace(tf, F, "Float"); + sc_trace(tf, L, "Logic"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test09/golden/test09.awif b/src/systemc/tests/systemc/tracing/wif_trace/test09/golden/test09.awif new file mode 100644 index 000000000..73faefe3d --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test09/golden/test09.awif @@ -0,0 +1,154 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Clock" BIT variable ; +start_trace O0 ; +declare O1 "Int" BIT 0 31 variable ; +start_trace O1 ; +declare O2 "Char" BIT 0 7 variable ; +start_trace O2 ; +declare O3 "Float" real variable ; +start_trace O3 ; +declare O4 "Logic" MVL variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + +delta_time 10000 ; +assign O0 '1' ; +assign O1 "00000000000000000000001111111111" ; +assign O2 "00001111" ; +assign O3 -4.000000 ; +assign O4 'X' ; + +delta_time 10000 ; +assign O0 '0' ; +assign O1 "00000000000000000000000000001010" ; +assign O2 "00001000" ; +assign O3 1000.234558 ; +assign O4 'Z' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test09/test09.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test09/test09.cpp new file mode 100644 index 000000000..a5372a9dd --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test09/test09.cpp @@ -0,0 +1,116 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test09.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + sc_signal<int>& Isig; + sc_signal<char>& Csig; + sc_signal<float>& Fsig; + sc_signal<sc_logic>& Lsig; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK, + sc_signal<int>& ISIG, + sc_signal<char>& CSIG, + sc_signal<float>& FSIG, + sc_signal<sc_logic>& LSIG ) + : Isig(ISIG), Csig(CSIG), Fsig(FSIG), Lsig(LSIG) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + Isig = 0; + Csig = 0; + Fsig = 0.0; + Lsig = SC_LOGIC_0;//'0'; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + Isig = 1023; + Csig = 15; + Fsig = -4; + Lsig = SC_LOGIC_X;//'x'; + wait(); + Isig = 10; + Csig = 8; + Fsig = 1000.23456; + Lsig = SC_LOGIC_Z;//'z'; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + sc_signal<int> I; + sc_signal<char> C; + sc_signal<float> F; + sc_signal<sc_logic> L; + + proc1 P1("P1", clock, I, C, F, L); + + tf = sc_create_wif_trace_file("test09"); + sc_trace(tf, clock, "Clock"); + sc_trace(tf, I, "Int"); + sc_trace(tf, C, "Char"); + sc_trace(tf, F, "Float"); + sc_trace(tf, L, "Logic"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test10/golden/test10.awif b/src/systemc/tests/systemc/tracing/wif_trace/test10/golden/test10.awif new file mode 100644 index 000000000..1768dbc9c --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test10/golden/test10.awif @@ -0,0 +1,89 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +type scalar "Enum__type__" enum "OK", "NOTOK", "SOSO", "SC_WIF_UNDEF" ; +declare O0 "Enum" "Enum__type__" variable ; +start_trace O0 ; +declare O1 "Clock" BIT variable ; +start_trace O1 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "OK" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "NOTOK" ; +assign O1 '0' ; + +delta_time 10000 ; +assign O0 "SOSO" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "SC_WIF_UNDEF" ; +assign O1 '0' ; + +delta_time 10000 ; +assign O0 "OK" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "NOTOK" ; +assign O1 '0' ; + +delta_time 10000 ; +assign O0 "SOSO" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "SC_WIF_UNDEF" ; +assign O1 '0' ; + +delta_time 10000 ; +assign O0 "OK" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "NOTOK" ; +assign O1 '0' ; + +delta_time 10000 ; +assign O0 "SOSO" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "SC_WIF_UNDEF" ; +assign O1 '0' ; + +delta_time 10000 ; +assign O0 "OK" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "NOTOK" ; +assign O1 '0' ; + +delta_time 10000 ; +assign O0 "SOSO" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "SC_WIF_UNDEF" ; +assign O1 '0' ; + +delta_time 10000 ; +assign O0 "OK" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "NOTOK" ; +assign O1 '0' ; + +delta_time 10000 ; +assign O0 "SOSO" ; +assign O1 '1' ; + +delta_time 10000 ; +assign O0 "SC_WIF_UNDEF" ; +assign O1 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test10/test10.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test10/test10.cpp new file mode 100644 index 000000000..5ffd2707e --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test10/test10.cpp @@ -0,0 +1,109 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test10.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + enum Ttype { + OK, + NOTOK, + SOSO + }; + + unsigned obj1; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = OK; + } + + void entry(); +}; + +void proc1::entry() +{ + wait(); + while(true) { + obj1 = OK; + wait(); + obj1 = NOTOK; + wait(); + obj1 = SOSO; + wait(); + obj1 = 5; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + char *enum_literals[4]; + enum_literals[0] = "OK"; + enum_literals[1] = "NOTOK"; + enum_literals[2] = "SOSO"; + enum_literals[3] = 0; + + proc1 P1("P1", clock); + + tf = sc_create_wif_trace_file("test10"); + sc_trace(tf, P1.obj1, "Enum", (const char **) enum_literals); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test11/golden/test11.awif b/src/systemc/tests/systemc/tracing/wif_trace/test11/golden/test11.awif new file mode 100644 index 000000000..cef27ab08 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test11/golden/test11.awif @@ -0,0 +1,116 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Bool" BIT variable ; +start_trace O0 ; +declare O1 "SC_Logic" MVL variable ; +start_trace O1 ; +declare O2 "SC_BV" BIT 0 3 variable ; +start_trace O2 ; +declare O3 "SC_LV" MVL 0 3 variable ; +start_trace O3 ; +declare O4 "Clock" BIT variable ; +start_trace O4 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 '0' ; +assign O1 '0' ; +assign O2 "0001" ; +assign O3 "0001" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "0011" ; +assign O3 "0011" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "0111" ; +assign O3 "0111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "1111" ; +assign O3 "1111" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "1110" ; +assign O3 "1110" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "1100" ; +assign O3 "1100" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "1000" ; +assign O3 "1000" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "0000" ; +assign O3 "0000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "0001" ; +assign O3 "0001" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "0011" ; +assign O3 "0011" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "0111" ; +assign O3 "0111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "1111" ; +assign O3 "1111" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "1110" ; +assign O3 "1110" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "1100" ; +assign O3 "1100" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "1000" ; +assign O3 "1000" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "0000" ; +assign O3 "0000" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "0001" ; +assign O3 "0001" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "0011" ; +assign O3 "0011" ; +assign O4 '0' ; + +delta_time 10000 ; +assign O2 "0111" ; +assign O3 "0111" ; +assign O4 '1' ; + +delta_time 10000 ; +assign O2 "1111" ; +assign O3 "1111" ; +assign O4 '0' ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test11/test11.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test11/test11.cpp new file mode 100644 index 000000000..05042cea8 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test11/test11.cpp @@ -0,0 +1,110 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test11.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + + bool obj1; + sc_logic obj2; + sc_bv<4> obj3; + sc_lv<4> obj4; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK ) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + obj3 = "0000"; + obj4 = "0000"; + } + + void entry(); +}; + +void proc1::entry() +{ + sc_bv<4> bv; + sc_lv<4> sv; + int i = 0; + bv = 0; + sv = 0; + wait(); + while(true) { + bv[i] = bv[i] ^ 1; + sv[i] ^= SC_LOGIC_1; + i = (i + 1) % 4; + obj3 = bv; + obj4 = sv; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + + proc1 P1("P1", clock); + + tf = sc_create_wif_trace_file("test11"); + tf->set_time_unit(1, SC_PS); + sc_trace(tf, P1.obj1, "Bool"); + sc_trace(tf, P1.obj2, "SC_Logic"); + sc_trace(tf, P1.obj3, "SC_BV"); + sc_trace(tf, P1.obj4, "SC_LV"); + sc_trace(tf, clock, "Clock"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test12/golden/test12.awif b/src/systemc/tests/systemc/tracing/wif_trace/test12/golden/test12.awif new file mode 100644 index 000000000..aadce2805 --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test12/golden/test12.awif @@ -0,0 +1,132 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "Signed" BIT 0 9 variable ; +start_trace O0 ; +declare O1 "Unsigned" BIT 0 9 variable ; +start_trace O1 ; +declare O2 "BV" BIT 0 9 variable ; +start_trace O2 ; +declare O3 "SV" BIT 0 9 variable ; +start_trace O3 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + +delta_time 10000 ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + +delta_time 10000 ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + +delta_time 10000 ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + +delta_time 10000 ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + +delta_time 10000 ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + +delta_time 10000 ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + +delta_time 10000 ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + +delta_time 10000 ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + +delta_time 10000 ; +assign O0 "0000000011" ; +assign O1 "0000000111" ; +assign O2 "0000000011" ; +assign O3 "0000000111" ; + +delta_time 10000 ; +assign O0 "1111111101" ; +assign O1 "0000000101" ; +assign O2 "1111111101" ; +assign O3 "0000000101" ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test12/test12.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test12/test12.cpp new file mode 100644 index 000000000..550b693fb --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test12/test12.cpp @@ -0,0 +1,112 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test12.cpp -- + + Original Author: Martin Janssen, Synopsys, Inc., 2002-02-15 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( proc1 ) +{ + SC_HAS_PROCESS( proc1 ); + + sc_in<bool> clk; + sc_out<sc_int<10> > bv; + sc_out<sc_uint<10> > sv; + + sc_int<10> obj1; + sc_uint<10> obj2; + + proc1( sc_module_name NAME, + sc_signal<bool>& CLK, + sc_signal<sc_int<10> >& BV, + sc_signal<sc_uint<10> >& SV ) + : bv(BV), sv(SV) + { + clk(CLK); + SC_THREAD( entry ); + sensitive << clk; + obj1 = 0; + obj2 = 0; + } + + void entry(); +}; + +void proc1::entry() +{ + bv = obj1; + sv = obj2; + wait(); + while(true) { + obj1 = 3; + obj2 = 7; + bv = obj1; + sv = obj2; + wait(); + obj1 = -3; + obj2 = 5; + bv = obj1; + sv = obj2; + wait(); + } +} + + +int sc_main(int ac, char *av[]) +{ + sc_trace_file *tf; + sc_signal<bool> clock; + sc_signal<sc_int<10> > bv; + sc_signal<sc_uint<10> > sv; + + proc1 P1("P1", clock, bv, sv); + + tf = sc_create_wif_trace_file("test12"); + sc_trace(tf, P1.obj1, "Signed"); + sc_trace(tf, P1.obj2, "Unsigned"); + sc_trace(tf, bv, "BV"); + sc_trace(tf, sv, "SV"); + + clock.write(0); + sc_start(0, SC_NS); + for (int i = 0; i< 10; i++) { + clock.write(1); + sc_start(10, SC_NS); + clock.write(0); + sc_start(10, SC_NS); + } + sc_close_wif_trace_file( tf ); + return 0; +} diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test15/golden/test15.awif b/src/systemc/tests/systemc/tracing/wif_trace/test15/golden/test15.awif new file mode 100644 index 000000000..49d173e5c --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test15/golden/test15.awif @@ -0,0 +1,33 @@ + +type scalar "BIT" enum '0', '1' ; +type scalar "MVL" enum '0', '1', 'X', 'Z', '?' ; + +declare O0 "test_top.sig" BIT 0 31 variable ; +start_trace O0 ; +comment "All initial values are dumped below at time 0 sec = 0 timescale units." ; +assign O0 "00000000000000000000000000000010" ; + +delta_time 1 ; +assign O0 "00000000000000000000000000000011" ; + +delta_time 1 ; +assign O0 "00000000000000000000000000000100" ; + +delta_time 1000 ; +assign O0 "00000000000000000000000000000111" ; + +delta_time 1000 ; +assign O0 "00000000000000000000000000001000" ; + +delta_time 1000 ; +assign O0 "00000000000000000000000000001001" ; + +delta_time 1 ; +assign O0 "00000000000000000000000000001010" ; + +delta_time 2 ; +assign O0 "00000000000000000000000000001011" ; + +delta_time 1000 ; +assign O0 "00000000000000000000000000001100" ; + diff --git a/src/systemc/tests/systemc/tracing/wif_trace/test15/test15.cpp b/src/systemc/tests/systemc/tracing/wif_trace/test15/test15.cpp new file mode 100644 index 000000000..a6ef6a07d --- /dev/null +++ b/src/systemc/tests/systemc/tracing/wif_trace/test15/test15.cpp @@ -0,0 +1,92 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test15.cpp -- test delta cycle tracing + + Original Author: Romain I Popov, Intel Corporation, 2017-05-29 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include <systemc.h> + +SC_MODULE(trace_delta_test) +{ + sc_signal <int> sig; + sc_inout<int > iport; + + SC_CTOR(trace_delta_test) + : sig("sig",0) + { + iport.bind(sig); + iport.initialize(1); + SC_THREAD(test_thread); + } + + void test_thread() { + cout << "initial sig value is " << sig.read() << endl; + sig = 2; + wait(SC_ZERO_TIME); + sig = 3; + wait(SC_ZERO_TIME); + sig = 4; + wait(1, SC_PS); + sig = 5; // This won't be shown on delta-cycle enabled trace + wait(1, SC_PS); + sig = 6; // This won't be shown on delta-cycle enabled trace + wait(1, SC_NS); + sig = 7; + wait(1, SC_NS); + sig = 8; + wait(1, SC_NS); + sig = 9; + wait(SC_ZERO_TIME); + sig = 10; + wait(3, SC_PS); + sig = 11; // Ok: 3ps > 2ps delta cycle shift + wait(1, SC_NS); + sig = 12; + + cout << "stop at " << sc_time_stamp() << endl; + sc_stop(); + } + +}; + + +int sc_main(int argc, char **argv) +{ + trace_delta_test test_top("test_top"); + sc_trace_file* tf = sc_create_wif_trace_file("test15"); + sc_trace_delta_cycles(tf,true); + sc_trace(tf, test_top.sig, test_top.sig.name()); + sc_start(); + return 0; +} |