diff options
Diffstat (limited to 'src/systemc/tests/systemc/utils/sc_vector')
18 files changed, 1096 insertions, 0 deletions
diff --git a/src/systemc/tests/systemc/utils/sc_vector/test01/golden/test01.log b/src/systemc/tests/systemc/utils/sc_vector/test01/golden/test01.log new file mode 100644 index 000000000..c05a2fb7c --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test01/golden/test01.log @@ -0,0 +1,12 @@ +SystemC Simulation +dut.sub_modules - sc_vector +dut.sub_modules_0 - sc_module +dut.sub_modules_1 - sc_module +dut.sub_modules_2 - sc_module +dut.sub_modules_3 - sc_module +dut.vector_0 - sc_vector +dut.vector_0_0 - sc_in +dut.vector_0_1 - sc_in +dut.vector_0_2 - sc_in +dut.vector_0_3 - sc_in +Program completed diff --git a/src/systemc/tests/systemc/utils/sc_vector/test01/test01.cpp b/src/systemc/tests/systemc/utils/sc_vector/test01/test01.cpp new file mode 100644 index 000000000..47cc9d45a --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test01/test01.cpp @@ -0,0 +1,84 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test01.cpp -- Test sc_vector + + Original Author: Philipp A. Hartmann, OFFIS, 2010-01-10 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +#include "sysc/utils/sc_vector.h" +using sc_core::sc_vector; + +SC_MODULE( sub_module ) +{ + sc_in<bool> in; + SC_CTOR(sub_module) {} +}; + +SC_MODULE( module ) +{ + // vector of sub-modules + sc_vector< sub_module > m_sub_vec; + + // vector of ports + sc_vector< sc_in<bool> > in_vec; + + module( sc_core::sc_module_name, unsigned n_sub ) + : m_sub_vec( "sub_modules", n_sub ) // set name prefix, and create sub-modules + // , in_vec() // use default constructor + // , in_vec( "in_vec" ) // set name prefix + { + // delayed initialisation of port vector + // here with default prefix sc_core::sc_gen_unique_name("vector") + in_vec.init( n_sub ); + + // bind ports of sub-modules -- sc_assemble_vector + sc_assemble_vector( m_sub_vec, &sub_module::in ).bind( in_vec ); + } +}; + +int sc_main(int , char* []) +{ + module m("dut", 4); + + std::vector<sc_object*> children = m.get_child_objects(); + + for (size_t i=0; i<children.size(); ++i ) + cout << children[i]->name() << " - " + << children[i]->kind() + << endl; + + cout << "Program completed" << endl; + return 0; +} diff --git a/src/systemc/tests/systemc/utils/sc_vector/test02/golden/test02.log b/src/systemc/tests/systemc/utils/sc_vector/test02/golden/test02.log new file mode 100644 index 000000000..6140c1e6a --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test02/golden/test02.log @@ -0,0 +1,18 @@ +SystemC Simulation +dut.array - sc_vector +dut.inps - sc_vector +dut.inps_0 - sc_in +dut.inps_1 - sc_in +dut.inps_2 - sc_in +dut.inps_3 - sc_in +dut.inps_4 - sc_in +dut.sigs - sc_vector +dut.array_0 - derived_0 +dut.array_1 - derived_1 +dut.array_2 - derived_0 +dut.sigs_0 - sc_signal +dut.sigs_1 - sc_signal +dut.sigs_2 - sc_signal +dut.sigs_3 - sc_signal +dut.sigs_4 - sc_signal +Program completed diff --git a/src/systemc/tests/systemc/utils/sc_vector/test02/test02.cpp b/src/systemc/tests/systemc/utils/sc_vector/test02/test02.cpp new file mode 100644 index 000000000..7b827dd3a --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test02/test02.cpp @@ -0,0 +1,127 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test02.cpp -- Test sc_vector + + Original Author: Philipp A. Hartmann, OFFIS, 2010-01-10 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +//#define USE_BOOST + +#ifndef USE_BOOST +# define SC_INCLUDE_DYNAMIC_PROCESSES +#endif + +#include "systemc.h" + +#include "sysc/utils/sc_vector.h" +using sc_core::sc_vector; + +#ifdef USE_BOOST +#include <boost/bind.hpp> +#include <boost/bind/placeholders.hpp> +#endif + +// ---- some classes +// +struct base : sc_object +{ + base( const char* n ) : sc_object(n) {} +}; + +struct derived_0 : base +{ + derived_0(const char* name) : base(name) {} + const char* kind() const { return "derived_0"; } +}; + +struct derived_1 : public base +{ + derived_1(const char* name) : base(name) {} + const char* kind() const { return "derived_1"; } +}; + +// plain function pointer +base* fill_array( const char* n, size_t i ) +{ + if( i%2 ) return new derived_1( n ); + return new derived_0( n ); +} + +SC_MODULE(DUT) +{ + sc_vector< base > arr; + sc_vector< sc_in<bool> > inps; + sc_vector< sc_signal<bool> > sigs; + + SC_CTOR(DUT); + + // member function as creator (use with sc_bind()) + sc_signal<bool>* init_sig_bind( const char* n, unsigned i ) + { + sc_signal<bool>* sig = new sc_signal<bool>(n); + inps[i]( *sig ); + return sig; + } +}; + + +DUT::DUT( sc_module_name ) + : arr("array") + , inps("inps", 5) + , sigs("sigs") +{ + arr.init( 3, fill_array ); + + sigs.init( inps.size() +#if defined( SC_INCLUDE_DYNAMIC_PROCESSES ) + , sc_bind( &DUT::init_sig_bind, this, sc_unnamed::_1, sc_unnamed::_2 ) +#elif defined( USE_BOOST ) + , boost::bind( &DUT::init_sig_bind, this, _1, _2 ) +#endif + ); +} + +int sc_main(int , char* []) +{ + DUT dut("dut"); + + std::vector<sc_object*> children = dut.get_child_objects(); + + for (size_t i=0; i<children.size(); ++i ) + cout << children[i]->name() << " - " + << children[i]->kind() + << endl; + + cout << "Program completed" << endl; + return 0; +} diff --git a/src/systemc/tests/systemc/utils/sc_vector/test03/golden/test03.log b/src/systemc/tests/systemc/utils/sc_vector/test03/golden/test03.log new file mode 100644 index 000000000..a982c7ab8 --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test03/golden/test03.log @@ -0,0 +1,12 @@ +SystemC Simulation +dut.sub_modules_0 - sc_module +dut.sub_modules_1 - sc_module +dut.sub_modules_2 - sc_module +dut.sub_modules_3 - sc_module +dut.sub_modules_4 - sc_module +sub_modules_0 - dut +sub_modules_1 - dut +sub_modules_2 - dut +sub_modules_3 - dut +sub_modules_4 - dut +Program completed diff --git a/src/systemc/tests/systemc/utils/sc_vector/test03/test03.cpp b/src/systemc/tests/systemc/utils/sc_vector/test03/test03.cpp new file mode 100644 index 000000000..9feebdc64 --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test03/test03.cpp @@ -0,0 +1,101 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test03.cpp -- Test sc_vector + + Original Author: Philipp A. Hartmann, OFFIS, 2010-03-05 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +#include "sysc/utils/sc_vector.h" +using sc_core::sc_vector; + +SC_MODULE( sub_module ) +{ + // constructor with additional parameters + sub_module( sc_core::sc_module_name, int param ); + // ... +}; + +SC_MODULE( module ) +{ + sc_core::sc_vector< sub_module > m_sub_vec; // vector of sub-modules + + module( sc_core::sc_module_name, unsigned n_sub ); // constructor + + struct mod_creator // Creator struct + { + mod_creator( int p ) : param(p) {} // store parameter to forward + + sub_module* operator()( const char* name, size_t ) // actual creator function + { + return new sub_module( name, param ); // forward param to sub-module + } + int param; + }; + +}; + +sub_module::sub_module( sc_core::sc_module_name, int ) + { /* empty */ } + +module::module( sc_core::sc_module_name, unsigned n_sub ) + : m_sub_vec( "sub_modules" ) // set name prefix +{ + m_sub_vec.init( n_sub, mod_creator(42) ); // init with custom creator + // ... +} + +int sc_main(int , char* []) +{ + module dut( "dut", 5 ); + + typedef sc_core::sc_vector<sub_module> vec_type; + vec_type const & children = dut.m_sub_vec; + + for( vec_type::const_iterator it = children.begin(); + it != children.end(); ++it ) + { + cout << it->name() << " - " + << (*it).kind() + << endl; + } + + for (size_t i=0; i < children.size(); ++i ) + cout << children[i].basename() << " - " + << children[i].get_parent_object()->name() + << endl; + + cout << "Program completed" << endl; + return 0; +} diff --git a/src/systemc/tests/systemc/utils/sc_vector/test04/golden/test04.log b/src/systemc/tests/systemc/utils/sc_vector/test04/golden/test04.log new file mode 100644 index 000000000..a7dfafcea --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test04/golden/test04.log @@ -0,0 +1,42 @@ +SystemC Simulation +dut.nodes_0_0 created @ 0x0 +dut.nodes_0_1 created @ 0x1 +dut.nodes_0_2 created @ 0x2 +dut.nodes_0_3 created @ 0x3 +dut.nodes_0_4 created @ 0x4 +dut.nodes_1_0 created @ 1x0 +dut.nodes_1_1 created @ 1x1 +dut.nodes_1_2 created @ 1x2 +dut.nodes_1_3 created @ 1x3 +dut.nodes_1_4 created @ 1x4 +dut.nodes_2_0 created @ 2x0 +dut.nodes_2_1 created @ 2x1 +dut.nodes_2_2 created @ 2x2 +dut.nodes_2_3 created @ 2x3 +dut.nodes_2_4 created @ 2x4 +dut.nodes_3_0 created @ 3x0 +dut.nodes_3_1 created @ 3x1 +dut.nodes_3_2 created @ 3x2 +dut.nodes_3_3 created @ 3x3 +dut.nodes_3_4 created @ 3x4 +dut.nodes_0_0 - sc_module +dut.nodes_1_0 - sc_module +dut.nodes_2_0 - sc_module +dut.nodes_3_0 - sc_module +dut.nodes_0_1 - sc_module +dut.nodes_1_1 - sc_module +dut.nodes_2_1 - sc_module +dut.nodes_3_1 - sc_module +dut.nodes_0_2 - sc_module +dut.nodes_1_2 - sc_module +dut.nodes_2_2 - sc_module +dut.nodes_3_2 - sc_module +dut.nodes_0_3 - sc_module +dut.nodes_1_3 - sc_module +dut.nodes_2_3 - sc_module +dut.nodes_3_3 - sc_module +dut.nodes_0_4 - sc_module +dut.nodes_1_4 - sc_module +dut.nodes_2_4 - sc_module +dut.nodes_3_4 - sc_module +Program completed diff --git a/src/systemc/tests/systemc/utils/sc_vector/test04/test04.cpp b/src/systemc/tests/systemc/utils/sc_vector/test04/test04.cpp new file mode 100644 index 000000000..e8aa4df8b --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test04/test04.cpp @@ -0,0 +1,110 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test04.cpp -- Test sc_vector -- build a two dimensional mesh + + Original Author: Philipp A. Hartmann, OFFIS, 2010-03-01 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" +#include "sysc/utils/sc_vector.h" + + +SC_MODULE( mesh_node ) +{ + // constructor with additional parameters + mesh_node( sc_core::sc_module_name, int x, int y ); +}; + +typedef sc_vector< mesh_node > row_type; +typedef sc_vector< row_type > mesh_type; + +SC_MODULE(mesh) +{ + mesh_type nodes; + + mesh( sc_module_name, int n, int m ); + + struct node_creator + { + node_creator( int row ) : x(row) {} + + mesh_node* operator()(const char * name, size_t idx ) + { + return new mesh_node( name, x, idx ); + } + int x; + }; + + struct row_creator + { + row_creator( int n_cols ) : cols_( n_cols ) {} + + row_type* operator()( const char* name, size_t idx ) + { + return new row_type( name, cols_, node_creator(idx) ); + } + int cols_; + }; + + const unsigned rows; + const unsigned cols; + +}; + +mesh_node::mesh_node( sc_module_name, int x, int y ) +{ + std::cout << name() << " created @ " + << x << "x" << y << std::endl; +} + +mesh::mesh( sc_module_name, int n, int m ) + : nodes("nodes") + , rows( n ) + , cols( m ) +{ + nodes.init( n, row_creator(m) ); +} + +int sc_main(int argc, char* argv[]) +{ + mesh dut("dut", 4, 5); + + for (size_t j=0; j<dut.cols; ++j ) + for (size_t i=0; i<dut.rows; ++i ) + cout << dut.nodes[i][j].name() << " - " + << dut.nodes[i][j].kind() + << endl; + + cout << "Program completed" << endl; + return 0; +} diff --git a/src/systemc/tests/systemc/utils/sc_vector/test05/golden/test05.log b/src/systemc/tests/systemc/utils/sc_vector/test05/golden/test05.log new file mode 100644 index 000000000..17786de25 --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test05/golden/test05.log @@ -0,0 +1,25 @@ +SystemC Simulation + +module::before_end_of_elaboration + top.in_0.size() == 1 - src_1_0 @ 0 + top.in_1.size() == 1 - src_1_1 @ 0 + top.in_2.size() == 1 - src_2_0 @ 0 + top.in_3.size() == 1 - src_2_1 @ 0 + +sub_module::before_end_of_elaboration + top.sub.in_0.size() == 0 + top.sub.in_1.size() == 0 + top.sub.in_2.size() == 0 + top.sub.in_3.size() == 0 + +module::end_of_elaboration + top.in_0.size() == 1 - src_1_0 @ 0 + top.in_1.size() == 1 - src_1_1 @ 0 + top.in_2.size() == 1 - src_2_0 @ 0 + top.in_3.size() == 1 - src_2_1 @ 0 + +sub_module::end_of_elaboration + top.sub.in_0.size() == 2 - src_1_0 @ 0 - fifo_0 @ 1 + top.sub.in_1.size() == 2 - src_1_1 @ 0 - fifo_1 @ 1 + top.sub.in_2.size() == 1 - src_2_0 @ 0 + top.sub.in_3.size() == 1 - src_2_1 @ 0 diff --git a/src/systemc/tests/systemc/utils/sc_vector/test05/test05.cpp b/src/systemc/tests/systemc/utils/sc_vector/test05/test05.cpp new file mode 100644 index 000000000..551b4fad1 --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test05/test05.cpp @@ -0,0 +1,127 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test05.cpp -- Test sc_vector (and its binding functions) + + Original Author: Philipp A. Hartmann, OFFIS, 2010-03-05 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include <systemc.h> + +#include "sysc/utils/sc_vector.h" +using sc_core::sc_vector; + +typedef sc_vector< sc_fifo_out<int> > port_vec; + +static void +dump_port_array( const char* from, const port_vec& in ) +{ + std::cout << "\n" << from << "\n"; + for( unsigned i=0; i<in.size(); ++i ) + { + std::cout + << " " + << in[i].name() + << ".size() == " << in[i].size(); + + for( int j=0; j<in[i].size(); ++j) + { + std::cout + << " - " + << dynamic_cast<const sc_core::sc_object*>(in[i][j])->name() + << " @ " << j; + } + std::cout << std::endl; + } +} + +SC_MODULE(sub_module) +{ + port_vec in; + + sub_module( sc_core::sc_module_name, unsigned n_sub ) + : in("in", n_sub ) {} + + void before_end_of_elaboration() + { dump_port_array( "sub_module::before_end_of_elaboration", in ); } + void end_of_elaboration() + { dump_port_array( "sub_module::end_of_elaboration", in ); } +}; + + +SC_MODULE(module) +{ + sub_module sub; + port_vec in; + + SC_CTOR(module) + : sub("sub", 4), in("in",4) + { + // vector to vector binding + sub.in( in ); + } + + void before_end_of_elaboration() + { dump_port_array( "module::before_end_of_elaboration", in ); } + void end_of_elaboration() + { dump_port_array( "module::end_of_elaboration", in ); } +}; + +int sc_main( int, char*[] ) +{ + + module top("top"); + + const unsigned size = 4; + const unsigned half = 2; + + sc_assert( top.in.size() == size ); + + sc_vector< sc_fifo<int> > + fifo_1( "src_1", half ), + fifo_2( "src_2", size ); + + // bind full vector (smaller than target) + port_vec::iterator mid = top.in( fifo_1 ); + sc_assert( ( mid - top.in.begin() ) - half == 0 ); + + // bind range, starting from last position + mid = top.in.bind( fifo_2.begin(), fifo_2.end(), mid ); + sc_assert( mid == top.in.end() ); + + // bind a plain C array of channels + sc_fifo<int> fifo_a[ half ]; + top.sub.in( fifo_a, fifo_a + half ); + + sc_start(); + return 0; +} diff --git a/src/systemc/tests/systemc/utils/sc_vector/test06/golden/test06.log b/src/systemc/tests/systemc/utils/sc_vector/test06/golden/test06.log new file mode 100644 index 000000000..d46c54a94 --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test06/golden/test06.log @@ -0,0 +1,37 @@ +SystemC Simulation + +-->-- m.get_child_objects() -->-- + - size: 10 + - dut.sub_modules - sc_vector + - dut.in_vec - sc_vector + - dut.sub_modules_0 - sc_module + - dut.sub_modules_1 - sc_module + - dut.sub_modules_2 - sc_module + - dut.sub_modules_3 - sc_module + - dut.in_vec_0 - sc_in + - dut.in_vec_1 - sc_in + - dut.in_vec_2 - sc_in + - dut.in_vec_3 - sc_in +--<-- m.get_child_objects() --<-- + +-->-- m.sub_vec.get_child_objects() -->-- + - size: 0 +--<-- m.sub_vec.get_child_objects() --<-- + +-->-- m.sub_vec.get_elements() -->-- + - size: 4 + - dut.sub_modules_0 - sc_module + - dut.sub_modules_1 - sc_module + - dut.sub_modules_2 - sc_module + - dut.sub_modules_3 - sc_module +--<-- m.sub_vec.get_elements() --<-- + +-->-- sc_assemble_vector( m.sub_vec, &sub_module::in ).get_elements() -->-- + - size: 4 + - dut.sub_modules_0.port_0 - sc_in + - dut.sub_modules_1.port_0 - sc_in + - dut.sub_modules_2.port_0 - sc_in + - dut.sub_modules_3.port_0 - sc_in +--<-- sc_assemble_vector( m.sub_vec, &sub_module::in ).get_elements() --<-- + +Program completed diff --git a/src/systemc/tests/systemc/utils/sc_vector/test06/test06.cpp b/src/systemc/tests/systemc/utils/sc_vector/test06/test06.cpp new file mode 100644 index 000000000..051d49c31 --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test06/test06.cpp @@ -0,0 +1,113 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test06.cpp -- Test sc_vector::get_elements + + Original Author: Philipp A. Hartmann, OFFIS, 2010-11-04 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc" + +#include "sysc/utils/sc_vector.h" + +using sc_core::sc_object; +using sc_core::sc_vector; +using sc_core::sc_mutex; +using sc_core::sc_in; + +void print_vector( const char * header, + const std::vector<sc_object*> & vec ) +{ + std::cout << "\n-->-- " << header << " -->--\n"; + + std::cout << " - size: " << vec.size() << "\n"; + + for (size_t i=0; i<vec.size(); ++i ) + std::cout << " - " + << vec[i]->name() << " - " + << vec[i]->kind() << "\n"; + + std::cout << "--<-- " << header << " --<--" + << std::endl; +} + +#define PRINT_VECTOR( Vector ) \ + print_vector( #Vector, Vector ) + +SC_MODULE( sub_module ) +{ + sc_in<bool> in; + SC_CTOR(sub_module) {} +}; + + +SC_MODULE( module ) +{ + // vector of sub-modules + sc_vector< sub_module > sub_vec; + + // vector of ports + sc_vector< sc_in<bool> > in_vec; + + SC_CTOR(module) + : sub_vec( "sub_modules" ) + , in_vec( "in_vec" ) + {} + + void init( unsigned n_sub ) + { + sub_vec.init(n_sub); + in_vec.init(n_sub); + // in_vec.init(n_sub); // second call fails + + // bind ports of sub-modules -- no dereference + sc_assemble_vector( sub_vec, &sub_module::in ).bind( in_vec ); + } + +}; + +int sc_main(int, char* []) +{ + module m("dut"); + m.init(4); // calls from external context + + PRINT_VECTOR( m.get_child_objects() ); + + PRINT_VECTOR( m.sub_vec.get_child_objects() ); + + PRINT_VECTOR( m.sub_vec.get_elements() ); + + PRINT_VECTOR( sc_assemble_vector( m.sub_vec, &sub_module::in ).get_elements() ); + + std::cout << "\nProgram completed" << std::endl; + return 0; +} diff --git a/src/systemc/tests/systemc/utils/sc_vector/test07/golden/test07.log b/src/systemc/tests/systemc/utils/sc_vector/test07/golden/test07.log new file mode 100644 index 000000000..da00cd389 --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test07/golden/test07.log @@ -0,0 +1,14 @@ +SystemC Simulation + +Warning: (W807) sc_vector::bind called with empty range: target `dut.sub_modules' (sc_vector_assembly) not initialised yet +In file: <removed by verify.pl> + +Warning: (W807) sc_vector::bind called with empty range: target `dut.sub_modules' (sc_vector_assembly) empty destination range given +In file: <removed by verify.pl> + +Warning: (W807) sc_vector::bind called with empty range: target `dut.in_vec' (sc_vector) empty destination range given +In file: <removed by verify.pl> + +Warning: (W807) sc_vector::bind called with empty range: target `dut.in_vec' (sc_vector) empty destination range given +In file: <removed by verify.pl> +Success diff --git a/src/systemc/tests/systemc/utils/sc_vector/test07/test07.cpp b/src/systemc/tests/systemc/utils/sc_vector/test07/test07.cpp new file mode 100644 index 000000000..beed04b1f --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test07/test07.cpp @@ -0,0 +1,105 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test01.cpp -- Test sc_vector -- empty bindings + + Original Author: Philipp A. Hartmann, OFFIS, 2011-02-14 + + *****************************************************************************/ + +/***************************************************************************** + + MODIFICATION LOG - modifiers, enter your name, affiliation, date and + changes you are making here. + + Name, Affiliation, Date: + Description of Modification: + + *****************************************************************************/ + +#include "systemc.h" + +SC_MODULE( sub_module ) +{ + sc_in<bool> in; + SC_CTOR(sub_module) {} +}; + +SC_MODULE( module ) +{ + // vector of sub-modules + sc_vector< sub_module > m_sub_vec; + + // vector of ports + sc_vector< sc_in<bool> > in_vec; + + module( sc_core::sc_module_name, unsigned n_sub ) + : m_sub_vec( "sub_modules" ) + , in_vec( "in_vec" ) + { + // bind ports of submodules (before initialisation of module vector) + do_bind(); + + // initialise module vector + m_sub_vec.init( n_sub ); + + // bind ports of submodules (before initialisation of port vector) + do_bind(); + + // delayed initialisation of port vector + in_vec.init( n_sub ); + + // bind ports of submodules (should be fine now) + do_bind(); + } + + void do_bind() + { + try { + // bind ports of sub-modules -- sc_assemble_vector + sc_assemble_vector( m_sub_vec, &sub_module::in ).bind( in_vec ); + } catch( sc_report const & rpt ) { + std::cout << rpt.what() << std::endl; + } + } +}; + +int sc_main(int , char* []) +{ + module m("dut", 4); + sc_vector< sc_signal<bool> > s("sig"); + + // bind ports to signals -- before initialisation of signal vector + m.in_vec( s ); + + s.init(4); + + // bind empty range + m.in_vec( s.begin(), s.begin() ); + + // bind with full range + m.in_vec( s ); + + sc_start( SC_ZERO_TIME ); + + cout << "Success" << endl; + return 0; +} diff --git a/src/systemc/tests/systemc/utils/sc_vector/test08/golden/test08.log b/src/systemc/tests/systemc/utils/sc_vector/test08/golden/test08.log new file mode 100644 index 000000000..4e18b8169 --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test08/golden/test08.log @@ -0,0 +1,9 @@ +SystemC Simulation + +Error: (E808) sc_vector::get_elements called for element type not derived from sc_object: evs +In file: <removed by verify.pl> + +Error: (E808) sc_vector::get_elements called for element type not derived from sc_object: foo +In file: <removed by verify.pl> + +Success diff --git a/src/systemc/tests/systemc/utils/sc_vector/test08/test08.cpp b/src/systemc/tests/systemc/utils/sc_vector/test08/test08.cpp new file mode 100644 index 000000000..d08a0d7fb --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test08/test08.cpp @@ -0,0 +1,60 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + test08.cpp -- sc_vector of objects not derived from sc_object + (OSCI extension to IEEE 1666-2011) + + Original Author: Philipp A. Hartmann, OFFIS, 2011-10-01 + + *****************************************************************************/ + +#include "systemc.h" + +struct foo +{ + explicit + foo( const char* nm ) + : name(nm) + {} + std::string name; +}; + +int sc_main( int, char*[] ) +{ + sc_report_handler::set_actions( SC_ERROR, SC_DISPLAY ); + + sc_vector< sc_event > ev_vec ( "evs", 1 ); + + sc_assert( ev_vec.size() == 1 ); + // should print an error + sc_assert( ev_vec.get_elements().size() == 0 ); + + sc_vector< foo > foo_vec( "foo", 1 ); + + sc_assert( foo_vec.size() == 1 ); + sc_assert( sc_assemble_vector( foo_vec, &foo::name ).size() == 1 ); + // should print an error + sc_assert( sc_assemble_vector( foo_vec, &foo::name ) + .get_elements().size() == 0 ); + + cout << "\nSuccess" << endl; + return 0; +} diff --git a/src/systemc/tests/systemc/utils/sc_vector/test09/golden/iter_test.log b/src/systemc/tests/systemc/utils/sc_vector/test09/golden/iter_test.log new file mode 100644 index 000000000..7ced375b0 --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test09/golden/iter_test.log @@ -0,0 +1,3 @@ +SystemC Simulation + +Success diff --git a/src/systemc/tests/systemc/utils/sc_vector/test09/iter_test.cpp b/src/systemc/tests/systemc/utils/sc_vector/test09/iter_test.cpp new file mode 100644 index 000000000..4a4599afa --- /dev/null +++ b/src/systemc/tests/systemc/utils/sc_vector/test09/iter_test.cpp @@ -0,0 +1,97 @@ +/***************************************************************************** + + Licensed to Accellera Systems Initiative Inc. (Accellera) under one or + more contributor license agreements. See the NOTICE file distributed + with this work for additional information regarding copyright ownership. + Accellera licenses this file to you under the Apache License, Version 2.0 + (the "License"); you may not use this file except in compliance with the + License. You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or + implied. See the License for the specific language governing + permissions and limitations under the License. + + *****************************************************************************/ + +/***************************************************************************** + + iter_test.cpp -- sc_vector iterator comparisons + + Original Author: Philipp A. Hartmann, OFFIS, 2014-08-21 + + *****************************************************************************/ +#include <systemc.h> + +SC_MODULE(mod) +{ + sc_in<bool> p; + SC_CTOR(mod){} +}; + +int sc_main(int,char*[]) +{ + typedef sc_vector<mod> module_vec; + typedef sc_vector_assembly<mod,sc_in<bool> > module_port_vec; + + module_vec mv("sigs",5); + module_vec::const_iterator citr = mv.begin(); + module_vec::iterator itr = mv.begin(); + + module_port_vec mpv = sc_assemble_vector(mv, &mod::p); + module_port_vec::const_iterator cpitr = mpv.cbegin(); + module_port_vec::iterator pitr = mpv.begin(); + + sc_assert(itr == citr); + sc_assert(citr == itr); + sc_assert(!(itr != citr)); + sc_assert(!(citr != itr)); + + sc_assert(itr == cpitr); + sc_assert(citr == pitr); + sc_assert(cpitr == itr); + sc_assert(pitr == citr); + sc_assert(!(itr != cpitr)); + sc_assert(!(citr != pitr)); + sc_assert(!(cpitr != pitr)); + sc_assert(!(pitr != itr)); + + sc_assert(itr < mv.end()); + sc_assert(!(itr > mv.cend())); + sc_assert(citr < mv.end()); + sc_assert(!(citr > mv.cend())); + + ++citr; + sc_assert(itr != citr); + sc_assert(citr != itr); + sc_assert(!(itr == citr)); + sc_assert(!(citr == itr)); + + sc_assert(!(itr < itr)); + sc_assert(!(itr > itr)); + sc_assert(itr < citr); + sc_assert(citr > itr); + + sc_assert(1 == citr - mv.begin()); + sc_assert(0 == pitr - mv.cbegin()); + itr += citr - mpv.begin(); + sc_assert(1 == itr - mpv.cbegin()); + + sc_assert(citr == itr); + sc_assert(itr <= citr); + sc_assert(citr <= itr); + sc_assert(cpitr <= itr); + sc_assert(!(itr <= cpitr)); + + itr++; + cpitr = pitr += itr - mv.begin(); + sc_assert(itr == pitr); + sc_assert(itr >= citr); + sc_assert(!(citr >= pitr)); + + cout << "\nSuccess" << endl; + return 0; +} |