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-rw-r--r--src/cpu/o3/lsq_impl.hh2
-rw-r--r--src/mem/cache/cache_impl.hh2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 337ee0372..317e23b14 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -68,7 +68,7 @@ LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
}
else {
//else it is a coherence request, maybe you need to do something
- warn("Recieved a coherence request (Invalidate??), 03CPU doesn't"
+ warn("Recieved a coherence request (Invalidate?), 03CPU doesn't"
"update LSQ for these\n");
}
return true;
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 18f56b1ba..c4acc03e7 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -720,7 +720,7 @@ Tick
Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
{
//Send a atomic (false) invalidate up if the protocol calls for it
- coherence->propogateInvalidate(pkt, true);
+ coherence->propogateInvalidate(pkt, false);
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt);