6 files changed, 73 insertions, 1 deletions
diff --git a/src/mem/protocol/RubySlicc_ComponentMapping.sm b/src/mem/protocol/RubySlicc_ComponentMapping.sm
index 559e54a8c..2a027554e 100644
--- a/src/mem/protocol/RubySlicc_ComponentMapping.sm
+++ b/src/mem/protocol/RubySlicc_ComponentMapping.sm
@@ -29,6 +29,8 @@
 
 // Mapping functions
 
+int getNumberOfLastLevelCaches();
+
 // NodeID map_address_to_node(Address addr);
 MachineID mapAddressToRange(Address addr, MachineType type, int low, int high);
 MachineID map_Address_to_DMA(Address addr);
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
new file mode 100644
index 000000000..4d37b0007
--- /dev/null
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.cc
@@ -0,0 +1,38 @@
+
+/*
+ * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
+#include "mem/ruby/system/CacheMemory.hh"
+
+int getNumberOfLastLevelCaches()
+{
+  return CacheMemory::numberOfLastLevelCaches();
+}
+
diff --git a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
index 96405c8dd..222ff86f8 100644
--- a/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
+++ b/src/mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh
@@ -61,6 +61,15 @@
 #define MACHINETYPE_L3CACHE_ENUM MachineType_NUM
 #endif
 
+#ifdef MACHINETYPE_DMA
+#define MACHINETYPE_DMA_ENUM MachineType_DMA
+#else
+#define MACHINETYPE_DMA_ENUM MachineType_NUM
+#endif
+
+// used to determine the number of acks to wait for
+int getNumberOfLastLevelCaches();
+
 // used to determine the home directory
 // returns a value between 0 and total_directories_within_the_system
 inline
@@ -81,7 +90,7 @@ MachineID map_Address_to_Directory(const Address &addr)
 inline
 MachineID map_Address_to_DMA(const Address & addr)
 {
-  MachineID dma = {MachineType_DMA, 0};
+  MachineID dma = {MACHINETYPE_DMA_ENUM, 0};
   return dma;
 }
 
diff --git a/src/mem/ruby/slicc_interface/SConscript b/src/mem/ruby/slicc_interface/SConscript
index 2b20892ba..6ba614fa9 100644
--- a/src/mem/ruby/slicc_interface/SConscript
+++ b/src/mem/ruby/slicc_interface/SConscript
@@ -35,3 +35,4 @@ if not env['RUBY']:
 
 Source('AbstractCacheEntry.cc')
 Source('RubySlicc_Profiler_interface.cc')
+Source('RubySlicc_ComponentMapping.cc')
diff --git a/src/mem/ruby/system/CacheMemory.cc b/src/mem/ruby/system/CacheMemory.cc
index a5c881a61..630b94542 100644
--- a/src/mem/ruby/system/CacheMemory.cc
+++ b/src/mem/ruby/system/CacheMemory.cc
@@ -28,6 +28,9 @@
 
 #include "mem/ruby/system/CacheMemory.hh"
 
+int CacheMemory::m_num_last_level_caches = 0;
+MachineType CacheMemory::m_last_level_machine_type = MachineType_FIRST;
+
 // Output operator declaration
 //ostream& operator<<(ostream& out, const CacheMemory<ENTRY>& obj);
 
@@ -55,6 +58,8 @@ void CacheMemory::init(const vector<string> & argv)
   int cache_size = -1;
   string policy;
 
+  m_num_last_level_caches = 
+    MachineType_base_count(MachineType_FIRST);
   m_controller = NULL;
   for (uint32 i=0; i<argv.size(); i+=2) {
     if (argv[i] == "size") {
@@ -67,6 +72,12 @@ void CacheMemory::init(const vector<string> & argv)
       policy = argv[i+1];
     } else if (argv[i] == "controller") {
       m_controller = RubySystem::getController(argv[i+1]);
+      if (m_last_level_machine_type < m_controller->getMachineType()) {
+        m_num_last_level_caches = 
+          MachineType_base_count(m_controller->getMachineType());
+        m_last_level_machine_type = 
+          m_controller->getMachineType();
+      } 
     } else {
       cerr << "WARNING: CacheMemory: Unknown configuration parameter: " << argv[i] << endl;
     }
@@ -110,6 +121,13 @@ CacheMemory::~CacheMemory()
   }
 }
 
+int
+CacheMemory::numberOfLastLevelCaches() 
+{ 
+  return m_num_last_level_caches; 
+}
+
+
 void CacheMemory::printConfig(ostream& out)
 {
   out << "Cache config: " << m_cache_name << endl;
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 00cd8ae35..856b7bcac 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -70,6 +70,8 @@ public:
   //  static CacheMemory* createCache(int level, int num, char split_type, AbstractCacheEntry* (*entry_factory)());
   //  static CacheMemory* getCache(int cache_id);
 
+  static int numberOfLastLevelCaches();
+  
   // Public Methods
   void printConfig(ostream& out);
 
@@ -167,6 +169,8 @@ private:
   int m_cache_num_set_bits;
   int m_cache_assoc;
 
+  static int m_num_last_level_caches;
+  static MachineType m_last_level_machine_type;
   static Vector< CacheMemory* > m_all_caches;
 };