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-rw-r--r--src/mem/DRAMCtrl.py18
-rw-r--r--src/mem/dram_ctrl.cc11
-rw-r--r--src/mem/dram_ctrl.hh1
3 files changed, 30 insertions, 0 deletions
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index f5b405d09..642e9d525 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -96,6 +96,9 @@ class DRAMCtrl(AbstractMemory):
max_accesses_per_row = Param.Unsigned(16, "Max accesses per row before "
"closing");
+ # size of DRAM Chip in Bytes
+ device_size = Param.MemorySize("Size of DRAM chip")
+
# pipeline latency of the controller and PHY, split into a
# frontend part and a backend part, with reads and writes serviced
# by the queues only seeing the frontend contribution, and reads
@@ -305,6 +308,9 @@ class DRAMCtrl(AbstractMemory):
# timings based on a DDR3-1600 4 Gbit datasheet (Micron MT41J512M8) in
# an 8x8 configuration.
class DDR3_1600_x64(DRAMCtrl):
+ # size of device in bytes
+ device_size = '512MB'
+
# 8x8 configuration, 8 devices each with an 8-bit interface
device_bus_width = 8
@@ -397,6 +403,9 @@ class DDR3_2133_x64(DDR3_1600_x64):
# timings based on a DDR4-2400 4 Gbit datasheet (Micron MT40A512M8)
# in an 8x8 configuration.
class DDR4_2400_x64(DRAMCtrl):
+ # size of device
+ device_size = '512MB'
+
# 8x8 configuration, 8 devices each with an 8-bit interface
device_bus_width = 8
@@ -488,6 +497,9 @@ class LPDDR2_S4_1066_x32(DRAMCtrl):
# No DLL in LPDDR2
dll = False
+ # size of device
+ device_size = '512MB'
+
# 1x32 configuration, 1 device with a 32-bit interface
device_bus_width = 32
@@ -572,6 +584,9 @@ class WideIO_200_x128(DRAMCtrl):
# No DLL for WideIO
dll = False
+ # size of device
+ device_size = '1024MB'
+
# 1x128 configuration, 1 device with a 128-bit interface
device_bus_width = 128
@@ -638,6 +653,9 @@ class LPDDR3_1600_x32(DRAMCtrl):
# No DLL for LPDDR3
dll = False
+ # size of device
+ device_size = '512MB'
+
# 1x32 configuration, 1 device with a 32-bit interface
device_bus_width = 32
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index ac78a3d1e..c9d944faa 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -62,6 +62,7 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
nextReqEvent(this), respondEvent(this), activateEvent(this),
prechargeEvent(this), refreshEvent(this), powerEvent(this),
drainManager(NULL),
+ deviceSize(p->device_size),
deviceBusWidth(p->device_bus_width), burstLength(p->burst_length),
deviceRowBufferSize(p->device_rowbuffer_size),
devicesPerRank(p->devices_per_rank),
@@ -139,6 +140,16 @@ DRAMCtrl::DRAMCtrl(const DRAMCtrlParams* p) :
// determine the rows per bank by looking at the total capacity
uint64_t capacity = ULL(1) << ceilLog2(AbstractMemory::size());
+ // determine the dram actual capacity from the DRAM config in Mbytes
+ uint64_t deviceCapacity = deviceSize / (1024 * 1024) * devicesPerRank *
+ ranksPerChannel;
+
+ // if actual DRAM size does not match memory capacity in system warn!
+ if (deviceCapacity != capacity / (1024 * 1024))
+ warn("DRAM device capacity (%d Mbytes) does not match the "
+ "address range assigned (%d Mbytes)\n", deviceCapacity,
+ capacity / (1024 * 1024));
+
DPRINTF(DRAM, "Memory capacity %lld (%lld) bytes\n", capacity,
AbstractMemory::size());
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
index cb2197841..0c4e53ca1 100644
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -463,6 +463,7 @@ class DRAMCtrl : public AbstractMemory
* The rowsPerBank is determined based on the capacity, number of
* ranks and banks, the burst size, and the row buffer size.
*/
+ const uint32_t deviceSize;
const uint32_t deviceBusWidth;
const uint32_t burstLength;
const uint32_t deviceRowBufferSize;