diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/cpu/BaseCPU.py | 7 | ||||
| -rw-r--r-- | src/mem/XBar.py | 51 |
2 files changed, 48 insertions, 10 deletions
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index ee6c05f46..9aa24c97b 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -47,7 +47,7 @@ from m5.defines import buildEnv from m5.params import * from m5.proxy import * -from XBar import CoherentXBar +from XBar import L2XBar from InstTracer import InstTracer from CPUTracers import ExeTracer from MemObject import MemObject @@ -285,10 +285,7 @@ class BaseCPU(MemObject): def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None): self.addPrivateSplitL1Caches(ic, dc, iwc, dwc) - # Set a width of 32 bytes (256-bits), which is four times that - # of the default bus. The clock of the CPU is inherited by - # default. - self.toL2Bus = CoherentXBar(width = 32) + self.toL2Bus = L2XBar() self.connectCachedPorts(self.toL2Bus) self.l2cache = l2c self.toL2Bus.master = self.l2cache.cpu_side diff --git a/src/mem/XBar.py b/src/mem/XBar.py index 64910ed72..a445b5e37 100644 --- a/src/mem/XBar.py +++ b/src/mem/XBar.py @@ -66,12 +66,12 @@ class BaseXBar(MemObject): # is the latency involved once a decision is made to forward the # request. The response latency, is similar to the forward # latency, but for responses rather than requests. - frontend_latency = Param.Cycles(3, "Frontend latency") - forward_latency = Param.Cycles(4, "Forward latency") - response_latency = Param.Cycles(2, "Response latency") + frontend_latency = Param.Cycles("Frontend latency") + forward_latency = Param.Cycles("Forward latency") + response_latency = Param.Cycles("Response latency") # Width governing the throughput of the crossbar - width = Param.Unsigned(8, "Datapath width per port (bytes)") + width = Param.Unsigned("Datapath width per port (bytes)") # The default port can be left unconnected, or be used to connect # a default slave port @@ -95,7 +95,7 @@ class CoherentXBar(BaseXBar): # The coherent crossbar additionally has snoop responses that are # forwarded after a specific latency. - snoop_response_latency = Param.Cycles(4, "Snoop response latency") + snoop_response_latency = Param.Cycles("Snoop response latency") # An optional snoop filter snoop_filter = Param.SnoopFilter(NULL, "Selected snoop filter") @@ -111,3 +111,44 @@ class SnoopFilter(SimObject): lookup_latency = Param.Cycles(1, "Lookup latency") system = Param.System(Parent.any, "System that the crossbar belongs to.") + +# We use a coherent crossbar to connect multiple masters to the L2 +# caches. Normally this crossbar would be part of the cache itself. +class L2XBar(CoherentXBar): + # 256-bit crossbar by default + width = 32 + + # Assume that most of this is covered by the cache latencies, with + # no more than a single pipeline stage for any packet. + frontend_latency = 1 + forward_latency = 0 + response_latency = 1 + snoop_response_latency = 1 + +# One of the key coherent crossbar instances is the system +# interconnect, tying together the CPU clusters, GPUs, and any I/O +# coherent masters, and DRAM controllers. +class SystemXBar(CoherentXBar): + # 128-bit crossbar by default + width = 16 + + # A handful pipeline stages for each portion of the latency + # contributions. + frontend_latency = 3 + forward_latency = 4 + response_latency = 2 + snoop_response_latency = 4 + +# In addition to the system interconnect, we typically also have one +# or more on-chip I/O crossbars. Note that at some point we might want +# to also define an off-chip I/O crossbar such as PCIe. +class IOXBar(NoncoherentXBar): + # 128-bit crossbar by default + width = 16 + + # Assume a simpler datapath than a coherent crossbar, incuring + # less pipeline stages for decision making and forwarding of + # requests. + frontend_latency = 2 + forward_latency = 1 + response_latency = 2 |