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-rw-r--r--src/arch/alpha/isa/decoder.isa2
-rw-r--r--src/arch/sparc/system.cc12
-rw-r--r--src/cpu/base.cc11
-rw-r--r--src/cpu/simple/atomic.cc7
-rw-r--r--src/cpu/simple/timing.cc3
-rw-r--r--src/mem/bus.cc1
-rw-r--r--src/mem/cache/base_cache.cc22
-rw-r--r--src/mem/cache/base_cache.hh64
-rw-r--r--src/mem/cache/cache.hh4
-rw-r--r--src/mem/cache/cache_impl.hh89
-rw-r--r--src/mem/cache/miss/blocking_buffer.cc6
-rw-r--r--src/mem/cache/miss/miss_queue.cc18
-rw-r--r--src/mem/cache/miss/mshr.cc2
-rw-r--r--src/mem/cache/miss/mshr_queue.cc3
-rw-r--r--src/mem/packet.hh14
-rw-r--r--src/python/m5/main.py1
-rw-r--r--src/sim/main.cc17
-rw-r--r--src/sim/pseudo_inst.cc10
-rw-r--r--src/sim/root.cc2
-rw-r--r--src/sim/sim_events.cc17
-rw-r--r--src/sim/sim_events.hh18
-rw-r--r--src/sim/sim_exit.hh8
-rw-r--r--src/sim/stat_control.cc2
23 files changed, 218 insertions, 115 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 4fc9da3f3..5bd19b677 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -701,7 +701,7 @@ decode OPCODE default Unknown::unknown() {
0x00: decode PALFUNC {
format EmulatedCallPal {
0x00: halt ({{
- exitSimLoop(curTick, "halt instruction encountered");
+ exitSimLoop("halt instruction encountered");
}}, IsNonSpeculative);
0x83: callsys({{
xc->syscall(R0);
diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc
index 63cbbe057..ef6443d17 100644
--- a/src/arch/sparc/system.cc
+++ b/src/arch/sparc/system.cc
@@ -152,10 +152,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
Param<std::string> readfile;
Param<unsigned int> init_param;
- Param<bool> bin;
- VectorParam<std::string> binned_fns;
- Param<bool> bin_int;
-
END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
@@ -173,10 +169,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
- INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10),
- INIT_PARAM_DFLT(bin, "is this system to be binned", false),
- INIT_PARAM(binned_fns, "functions to be broken down and binned"),
- INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true)
+ INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
END_INIT_SIM_OBJECT_PARAMS(SparcSystem)
@@ -196,9 +189,6 @@ CREATE_SIM_OBJECT(SparcSystem)
p->readfile = readfile;
p->system_type = system_type;
p->system_rev = system_rev;
- p->bin = bin;
- p->binned_fns = binned_fns;
- p->bin_int = bin_int;
return new SparcSystem(p);
}
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 513dd7c55..ea4b03bf2 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -41,6 +41,7 @@
#include "cpu/cpuevent.hh"
#include "cpu/thread_context.hh"
#include "cpu/profile.hh"
+#include "sim/sim_exit.hh"
#include "sim/param.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
@@ -125,8 +126,9 @@ BaseCPU::BaseCPU(Params *p)
//
if (p->max_insts_any_thread != 0)
for (int i = 0; i < number_of_threads; ++i)
- new SimLoopExitEvent(comInstEventQueue[i], p->max_insts_any_thread,
- "a thread reached the max instruction count");
+ schedExitSimLoop("a thread reached the max instruction count",
+ p->max_insts_any_thread, 0,
+ comInstEventQueue[i]);
if (p->max_insts_all_threads != 0) {
// allocate & initialize shared downcounter: each event will
@@ -150,8 +152,9 @@ BaseCPU::BaseCPU(Params *p)
//
if (p->max_loads_any_thread != 0)
for (int i = 0; i < number_of_threads; ++i)
- new SimLoopExitEvent(comLoadEventQueue[i], p->max_loads_any_thread,
- "a thread reached the max load count");
+ schedExitSimLoop("a thread reached the max load count",
+ p->max_loads_any_thread, 0,
+ comLoadEventQueue[i]);
if (p->max_loads_all_threads != 0) {
// allocate & initialize shared downcounter: each event will
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index c396f5033..88698bfee 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -161,9 +161,9 @@ AtomicSimpleCPU::serialize(ostream &os)
{
SimObject::State so_state = SimObject::getState();
SERIALIZE_ENUM(so_state);
+ BaseSimpleCPU::serialize(os);
nameOut(os, csprintf("%s.tickEvent", name()));
tickEvent.serialize(os);
- BaseSimpleCPU::serialize(os);
}
void
@@ -171,8 +171,8 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
{
SimObject::State so_state;
UNSERIALIZE_ENUM(so_state);
- tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
BaseSimpleCPU::unserialize(cp, section);
+ tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
}
void
@@ -464,6 +464,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
+ Param<Tick> progress_interval;
SimObjectParam<MemObject *> mem;
SimObjectParam<System *> system;
@@ -496,6 +497,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
+ INIT_PARAM(progress_interval, "Progress interval"),
INIT_PARAM(mem, "memory"),
INIT_PARAM(system, "system object"),
@@ -527,6 +529,7 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
params->max_insts_all_threads = max_insts_all_threads;
params->max_loads_any_thread = max_loads_any_thread;
params->max_loads_all_threads = max_loads_all_threads;
+ params->progress_interval = progress_interval;
params->deferRegistration = defer_registration;
params->clock = clock;
params->functionTrace = function_trace;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 5c1654f7e..03ee27e04 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -589,6 +589,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
+ Param<Tick> progress_interval;
SimObjectParam<MemObject *> mem;
SimObjectParam<System *> system;
@@ -621,6 +622,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
+ INIT_PARAM(progress_interval, "Progress interval"),
INIT_PARAM(mem, "memory"),
INIT_PARAM(system, "system object"),
@@ -652,6 +654,7 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
params->max_insts_all_threads = max_insts_all_threads;
params->max_loads_any_thread = max_loads_any_thread;
params->max_loads_all_threads = max_loads_all_threads;
+ params->progress_interval = progress_interval;
params->deferRegistration = defer_registration;
params->clock = clock;
params->functionTrace = function_trace;
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index cf9e54e62..3c5283a77 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -252,6 +252,7 @@ Bus::recvFunctional(Packet *pkt)
DPRINTF(Bus, "recvFunctional: packet src %d dest %d addr 0x%x cmd %s\n",
pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString());
assert(pkt->getDest() == Packet::Broadcast);
+ atomicSnoop(pkt);
findPort(pkt->getAddr(), pkt->getSrc())->sendFunctional(pkt);
}
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index a172847df..d7ccca8c0 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -96,6 +96,15 @@ void
BaseCache::CachePort::recvRetry()
{
Packet *pkt;
+ if (!drainList.empty()) {
+ //We have some responses to drain first
+ bool result = true;
+ while (result && !drainList.empty()) {
+ result = sendTiming(drainList.front());
+ if (result)
+ drainList.pop_front();
+ }
+ }
if (!isCpuSide)
{
@@ -199,8 +208,17 @@ BaseCache::CacheEvent::process()
return;
}
//Response
- //Know the packet to send, no need to mark in service (must succed)
- assert(cachePort->sendTiming(pkt));
+ //Know the packet to send
+ pkt->result = Packet::Success;
+ pkt->makeTimingResponse();
+ if (!cachePort->drainList.empty()) {
+ //Already blocked waiting for bus, just append
+ cachePort->drainList.push_back(pkt);
+ }
+ else if (!cachePort->sendTiming(pkt)) {
+ //It failed, save it to list of drain events
+ cachePort->drainList.push_back(pkt);
+ }
}
const char *
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 069dbab58..c69fb7fd5 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -110,6 +110,8 @@ class BaseCache : public MemObject
bool mustSendRetry;
bool isCpuSide;
+
+ std::list<Packet *> drainList;
};
struct CacheEvent : public Event
@@ -127,6 +129,8 @@ class BaseCache : public MemObject
CachePort *cpuSidePort;
CachePort *memSidePort;
+ bool snoopRangesSent;
+
public:
virtual Port *getPort(const std::string &if_name, int idx = -1);
@@ -149,17 +153,22 @@ class BaseCache : public MemObject
void recvStatusChange(Port::Status status, bool isCpuSide)
{
- if (status == Port::RangeChange)
- {
- if (!isCpuSide)
- {
+ if (status == Port::RangeChange){
+ if (!isCpuSide) {
cpuSidePort->sendStatusChange(Port::RangeChange);
+ if (topLevelCache && !snoopRangesSent) {
+ snoopRangesSent = true;
+ memSidePort->sendStatusChange(Port::RangeChange);
+ }
}
- else
- {
+ else {
memSidePort->sendStatusChange(Port::RangeChange);
}
}
+ else if (status == Port::SnoopSquash) {
+ assert(snoopPhase2);
+ snoopPhase2 = false;
+ }
}
virtual Packet *getPacket()
@@ -205,6 +214,10 @@ class BaseCache : public MemObject
/** True if this cache is connected to the CPU. */
bool topLevelCache;
+
+ /** True if we are now in phase 2 of the snoop process. */
+ bool snoopPhase2;
+
/** Stores time the cache blocked for statistics. */
Tick blockedCycle;
@@ -332,6 +345,7 @@ class BaseCache : public MemObject
//Start ports at null if more than one is created we should panic
cpuSidePort = NULL;
memSidePort = NULL;
+ snoopRangesSent = false;
}
virtual void init();
@@ -382,9 +396,12 @@ class BaseCache : public MemObject
blocked_causes[cause]++;
blockedCycle = curTick;
}
- blocked |= flag;
- DPRINTF(Cache,"Blocking for cause %s\n", cause);
- cpuSidePort->setBlocked();
+ if (!(blocked & flag)) {
+ //Wasn't already blocked for this cause
+ blocked |= flag;
+ DPRINTF(Cache,"Blocking for cause %s\n", cause);
+ cpuSidePort->setBlocked();
+ }
}
/**
@@ -395,8 +412,11 @@ class BaseCache : public MemObject
void setBlockedForSnoop(BlockedCause cause)
{
uint8_t flag = 1 << cause;
- blockedSnoop |= flag;
- memSidePort->setBlocked();
+ if (!(blocked & flag)) {
+ //Wasn't already blocked for this cause
+ blockedSnoop |= flag;
+ memSidePort->setBlocked();
+ }
}
/**
@@ -503,8 +523,6 @@ class BaseCache : public MemObject
*/
void respond(Packet *pkt, Tick time)
{
- pkt->makeTimingResponse();
- pkt->result = Packet::Success;
CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
reqCpu->schedule(time);
}
@@ -517,10 +535,8 @@ class BaseCache : public MemObject
void respondToMiss(Packet *pkt, Tick time)
{
if (!pkt->req->isUncacheable()) {
- missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
+ missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
}
- pkt->makeTimingResponse();
- pkt->result = Packet::Success;
CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
reqCpu->schedule(time);
}
@@ -529,10 +545,12 @@ class BaseCache : public MemObject
* Suppliess the data if cache to cache transfers are enabled.
* @param pkt The bus transaction to fulfill.
*/
- void respondToSnoop(Packet *pkt)
+ void respondToSnoop(Packet *pkt, Tick time)
{
- assert("Implement\n" && 0);
+// assert("Implement\n" && 0);
// mi->respond(pkt,curTick + hitLatency);
+ CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
+ reqMem->schedule(time);
}
/**
@@ -551,6 +569,16 @@ class BaseCache : public MemObject
else
{
//This is where snoops get updated
+ AddrRangeList dummy;
+ if (!topLevelCache)
+ {
+ cpuSidePort->getPeerAddressRanges(dummy, snoop);
+ }
+ else
+ {
+ snoop.push_back(RangeSize(0,-1));
+ }
+
return;
}
}
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 989b8743e..4b8870c95 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -251,7 +251,7 @@ class Cache : public BaseCache
* request.
* @return The estimated completion time.
*/
- Tick probe(Packet * &pkt, bool update);
+ Tick probe(Packet * &pkt, bool update, CachePort * otherSidePort);
/**
* Snoop for the provided request in the cache and return the estimated
@@ -262,7 +262,7 @@ class Cache : public BaseCache
* request.
* @return The estimated completion time.
*/
- Tick snoopProbe(Packet * &pkt, bool update);
+ Tick snoopProbe(Packet * &pkt);
};
#endif // __CACHE_HH__
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 11cd84e88..46f4b0ebe 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -51,7 +51,7 @@
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/prefetch/prefetcher.hh"
-#include "sim/sim_events.hh" // for SimExitEvent
+#include "sim/sim_exit.hh" // for SimExitEvent
template<class TagStore, class Buffering, class Coherence>
bool
@@ -63,14 +63,26 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
if (pkt->isWrite() && (pkt->req->getFlags() & LOCKED)) {
pkt->req->setScResult(1);
}
- access(pkt);
+ if (!(pkt->flags & SATISFIED)) {
+ access(pkt);
+ }
}
else
{
if (pkt->isResponse())
handleResponse(pkt);
- else
- snoop(pkt);
+ else {
+ //Check if we are in phase1
+ if (!snoopPhase2) {
+ snoopPhase2 = true;
+ }
+ else {
+ //Check if we should do the snoop
+ if (pkt->flags && SNOOP_COMMIT)
+ snoop(pkt);
+ snoopPhase2 = false;
+ }
+ }
}
return true;
}
@@ -87,7 +99,7 @@ doAtomicAccess(Packet *pkt, bool isCpuSide)
pkt->req->setScResult(1);
}
- probe(pkt, true);
+ probe(pkt, true, NULL);
//TEMP ALWAYS SUCCES FOR NOW
pkt->result = Packet::Success;
}
@@ -96,7 +108,7 @@ doAtomicAccess(Packet *pkt, bool isCpuSide)
if (pkt->isResponse())
handleResponse(pkt);
else
- snoopProbe(pkt, true);
+ snoopProbe(pkt);
}
//Fix this timing info
return hitLatency;
@@ -117,16 +129,13 @@ doFunctionalAccess(Packet *pkt, bool isCpuSide)
assert("Can't handle LL/SC on functional path\n");
}
- probe(pkt, true);
+ probe(pkt, false, memSidePort);
//TEMP ALWAYS SUCCESFUL FOR NOW
pkt->result = Packet::Success;
}
else
{
- if (pkt->isResponse())
- handleResponse(pkt);
- else
- snoopProbe(pkt, true);
+ probe(pkt, false, cpuSidePort);
}
}
@@ -239,7 +248,7 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
pkt->getAddr() & ~((Addr)blkSize - 1), pkt->req->getPC());
if (blk) {
// Hit
- hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+ hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
// clear dirty bit if write through
if (pkt->needsResponse())
respond(pkt, curTick+lat);
@@ -249,12 +258,12 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
// Miss
if (!pkt->req->isUncacheable()) {
- misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
/** @todo Move miss count code into BaseCache */
if (missCount) {
--missCount;
if (missCount == 0)
- new SimLoopExitEvent(curTick, "A cache reached the maximum miss count");
+ exitSimLoop("A cache reached the maximum miss count");
}
}
missQueue->handleMiss(pkt, size, curTick + hitLatency);
@@ -270,7 +279,7 @@ Cache<TagStore,Buffering,Coherence>::getPacket()
Packet * pkt = missQueue->getPacket();
if (pkt) {
if (!pkt->req->isUncacheable()) {
- if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][pkt->req->getThreadNum()]++;
+ if (pkt->cmd == Packet::HardPFReq) misses[Packet::HardPFReq][0/*pkt->req->getThreadNum()*/]++;
BlkType *blk = tags->findBlock(pkt);
Packet::Command cmd = coherence->getBusCmd(pkt->cmd,
(blk)? blk->status : 0);
@@ -314,9 +323,10 @@ Cache<TagStore,Buffering,Coherence>::handleResponse(Packet * &pkt)
PacketList writebacks;
blk = tags->handleFill(blk, (MSHR*)pkt->senderState,
coherence->getNewState(pkt,old_state),
- writebacks);
+ writebacks, pkt);
while (!writebacks.empty()) {
missQueue->doWriteback(writebacks.front());
+ writebacks.pop_front();
}
}
missQueue->handleResponse(pkt, curTick + hitLatency);
@@ -372,7 +382,6 @@ template<class TagStore, class Buffering, class Coherence>
void
Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
{
-
Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
BlkType *blk = tags->findBlock(pkt);
MSHR *mshr = missQueue->findMSHR(blk_addr);
@@ -385,7 +394,10 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
//If the outstanding request was an invalidate (upgrade,readex,..)
//Then we need to ACK the request until we get the data
//Also NACK if the outstanding request is not a cachefill (writeback)
+ pkt->flags |= SATISFIED;
pkt->flags |= NACKED_LINE;
+ assert("Don't detect these on the other side yet\n");
+ respondToSnoop(pkt, curTick + hitLatency);
return;
}
else {
@@ -398,6 +410,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
//@todo Make it so that a read to a pending read can't be exclusive now.
//Set the address so find match works
+ assert("Don't have invalidates yet\n");
invalidatePkt->addrOverride(pkt->getAddr());
//Append the invalidate on
@@ -433,7 +446,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
assert(offset + pkt->getSize() <=blkSize);
memcpy(pkt->getPtr<uint8_t>(), mshr->pkt->getPtr<uint8_t>() + offset, pkt->getSize());
- respondToSnoop(pkt);
+ respondToSnoop(pkt, curTick + hitLatency);
}
if (pkt->isInvalidate()) {
@@ -449,7 +462,7 @@ Cache<TagStore,Buffering,Coherence>::snoop(Packet * &pkt)
bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
if (satisfy) {
tags->handleSnoop(blk, new_state, pkt);
- respondToSnoop(pkt);
+ respondToSnoop(pkt, curTick + hitLatency);
return;
}
tags->handleSnoop(blk, new_state);
@@ -486,7 +499,7 @@ Cache<TagStore,Buffering,Coherence>::invalidateBlk(Addr addr)
*/
template<class TagStore, class Buffering, class Coherence>
Tick
-Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
+Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update, CachePort* otherSidePort)
{
// MemDebug::cacheProbe(pkt);
if (!pkt->req->isUncacheable()) {
@@ -517,7 +530,8 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
missQueue->findWrites(blk_addr, writes);
if (!update) {
- memSidePort->sendFunctional(pkt);
+ otherSidePort->sendFunctional(pkt);
+
// Check for data in MSHR and writebuffer.
if (mshr) {
warn("Found outstanding miss on an non-update probe");
@@ -612,12 +626,15 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
lat = memSidePort->sendAtomic(busPkt);
+ //Be sure to flip the response to a request for coherence
+ busPkt->makeAtomicResponse();
+
/* if (!(busPkt->flags & SATISFIED)) {
// blocked at a higher level, just return
return 0;
}
-*/ misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+*/ misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
CacheBlk::State old_state = (blk) ? blk->status : 0;
tags->handleFill(blk, busPkt,
@@ -642,10 +659,10 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
}
if (update) {
- hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+ hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
} else if (pkt->isWrite()) {
// Still need to change data in all locations.
- return memSidePort->sendAtomic(pkt);
+ return otherSidePort->sendAtomic(pkt);
}
return curTick + lat;
}
@@ -655,18 +672,18 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update)
template<class TagStore, class Buffering, class Coherence>
Tick
-Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt, bool update)
+Cache<TagStore,Buffering,Coherence>::snoopProbe(PacketPtr &pkt)
{
- Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
- BlkType *blk = tags->findBlock(pkt);
- MSHR *mshr = missQueue->findMSHR(blk_addr);
- CacheBlk::State new_state = 0;
- bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
- if (satisfy) {
- tags->handleSnoop(blk, new_state, pkt);
- return hitLatency;
- }
- tags->handleSnoop(blk, new_state);
- return 0;
+ Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
+ BlkType *blk = tags->findBlock(pkt);
+ MSHR *mshr = missQueue->findMSHR(blk_addr);
+ CacheBlk::State new_state = 0;
+ bool satisfy = coherence->handleBusRequest(pkt,blk,mshr, new_state);
+ if (satisfy) {
+ tags->handleSnoop(blk, new_state, pkt);
+ return hitLatency;
+ }
+ tags->handleSnoop(blk, new_state);
+ return 0;
}
diff --git a/src/mem/cache/miss/blocking_buffer.cc b/src/mem/cache/miss/blocking_buffer.cc
index 67fc7ae56..7a6ea9133 100644
--- a/src/mem/cache/miss/blocking_buffer.cc
+++ b/src/mem/cache/miss/blocking_buffer.cc
@@ -189,7 +189,7 @@ BlockingBuffer::squash(int threadNum)
if (miss.threadNum == threadNum) {
Packet * target = miss.getTarget();
miss.popTarget();
- assert(target->req->getThreadNum() == threadNum);
+ assert(0/*target->req->getThreadNum()*/ == threadNum);
target = NULL;
assert(!miss.hasTargets());
miss.ntargets=0;
@@ -218,7 +218,7 @@ BlockingBuffer::doWriteback(Addr addr,
}
///All writebacks charged to same thread @todo figure this out
- writebacks[pkt->req->getThreadNum()]++;
+ writebacks[0/*pkt->req->getThreadNum()*/]++;
wb.allocateAsBuffer(pkt);
cache->setMasterRequest(Request_WB, curTick);
@@ -230,7 +230,7 @@ BlockingBuffer::doWriteback(Addr addr,
void
BlockingBuffer::doWriteback(Packet * &pkt)
{
- writebacks[pkt->req->getThreadNum()]++;
+ writebacks[0/*pkt->req->getThreadNum()*/]++;
wb.allocateAsBuffer(pkt);
diff --git a/src/mem/cache/miss/miss_queue.cc b/src/mem/cache/miss/miss_queue.cc
index 76fb25716..273b6587f 100644
--- a/src/mem/cache/miss/miss_queue.cc
+++ b/src/mem/cache/miss/miss_queue.cc
@@ -413,8 +413,8 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
mshr = mq.findMatch(blkAddr);
if (mshr) {
//@todo remove hw_pf here
- mshr_hits[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
- if (mshr->threadNum != pkt->req->getThreadNum()) {
+ mshr_hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
+ if (mshr->threadNum != 0/*pkt->req->getThreadNum()*/) {
mshr->threadNum = -1;
}
mq.allocateTarget(mshr, pkt);
@@ -434,11 +434,11 @@ MissQueue::handleMiss(Packet * &pkt, int blkSize, Tick time)
mshr_no_allocate_misses++;
}
else {
- mshr_misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+ mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
}
} else {
//Count uncacheable accesses
- mshr_uncacheable[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+ mshr_uncacheable[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
size = pkt->getSize();
}
if (pkt->isWrite() && (pkt->req->isUncacheable() || !writeAllocate ||
@@ -499,7 +499,7 @@ MissQueue::getPacket()
pkt = prefetcher->getPacket();
if (pkt) {
//Update statistic on number of prefetches issued (hwpf_mshr_misses)
- mshr_misses[pkt->cmdToIndex()][pkt->req->getThreadNum()]++;
+ mshr_misses[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
//It will request the bus for the future, but should clear that immedieatley
allocateMiss(pkt, pkt->getSize(), curTick);
pkt = mq.getReq();
@@ -592,7 +592,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
BlockedCause cause = NUM_BLOCKED_CAUSES;
if (pkt->isCacheFill() && !pkt->isNoAllocate()) {
- mshr_miss_latency[mshr->originalCmd][pkt->req->getThreadNum()] +=
+ mshr_miss_latency[mshr->originalCmd][0/*pkt->req->getThreadNum()*/] +=
curTick - pkt->time;
// targets were handled in the cache tags
if (mshr == noTargetMSHR) {
@@ -619,7 +619,7 @@ MissQueue::handleResponse(Packet * &pkt, Tick time)
}
} else {
if (pkt->req->isUncacheable()) {
- mshr_uncacheable_lat[pkt->cmd][pkt->req->getThreadNum()] +=
+ mshr_uncacheable_lat[pkt->cmd][0/*pkt->req->getThreadNum()*/] +=
curTick - pkt->time;
}
if (mshr->hasTargets() && pkt->req->isUncacheable()) {
@@ -725,7 +725,7 @@ MissQueue::doWriteback(Addr addr,
}
///All writebacks charged to same thread @todo figure this out
- writebacks[pkt->req->getThreadNum()]++;
+ writebacks[0/*pkt->req->getThreadNum()*/]++;
allocateWrite(pkt, 0, curTick);
}
@@ -734,7 +734,7 @@ MissQueue::doWriteback(Addr addr,
void
MissQueue::doWriteback(Packet * &pkt)
{
- writebacks[pkt->req->getThreadNum()]++;
+ writebacks[0/*pkt->req->getThreadNum()*/]++;
allocateWrite(pkt, 0, curTick);
}
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 519ec5ebd..f36032672 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -88,7 +88,7 @@ void
MSHR::allocateAsBuffer(Packet * &target)
{
addr = target->getAddr();
- threadNum = target->req->getThreadNum();
+ threadNum = 0/*target->req->getThreadNum()*/;
pkt = new Packet(target->req, target->cmd, -1);
pkt->allocate();
pkt->senderState = (Packet::SenderState*)this;
diff --git a/src/mem/cache/miss/mshr_queue.cc b/src/mem/cache/miss/mshr_queue.cc
index 97a56119f..bd9667529 100644
--- a/src/mem/cache/miss/mshr_queue.cc
+++ b/src/mem/cache/miss/mshr_queue.cc
@@ -128,6 +128,7 @@ MSHR*
MSHRQueue::allocate(Packet * &pkt, int size)
{
Addr aligned_addr = pkt->getAddr() & ~((Addr)size - 1);
+ assert(!freeList.empty());
MSHR *mshr = freeList.front();
assert(mshr->getNumTargets() == 0);
freeList.pop_front();
@@ -251,7 +252,7 @@ MSHRQueue::squash(int threadNum)
Packet * target = mshr->getTarget();
mshr->popTarget();
- assert(target->req->getThreadNum() == threadNum);
+ assert(0/*target->req->getThreadNum()*/ == threadNum);
target = NULL;
}
assert(!mshr->hasTargets());
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index c7d28010c..be9bf5f57 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -312,7 +312,7 @@ class Packet
* for returning as a response to that request. Used for timing
* accesses only. For atomic and functional accesses, the
* request packet is always implicitly passed back *without*
- * modifying the command or destination fields, so this function
+ * modifying the destination fields, so this function
* should not be called. */
void makeTimingResponse() {
assert(needsResponse());
@@ -325,6 +325,18 @@ class Packet
srcValid = false;
}
+ /** Take a request packet and modify it in place to be suitable
+ * for returning as a response to that request.
+ */
+ void makeAtomicResponse() {
+ assert(needsResponse());
+ assert(isRequest());
+ int icmd = (int)cmd;
+ icmd &= ~(IsRequest);
+ icmd |= IsResponse;
+ cmd = (Command)icmd;
+ }
+
/** Take a request packet that has been returned as NACKED and modify it so
* that it can be sent out again. Only packets that need a response can be
* NACKED, so verify that that is true. */
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index e93ef3a36..ccd6c5807 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -278,6 +278,7 @@ def main():
# set tracing options
objects.Trace.flags = options.trace_flags
objects.Trace.start = options.trace_start
+ objects.Trace.cycle = options.trace_cycle
objects.Trace.file = options.trace_file
objects.Trace.bufsize = options.trace_circlebuf
objects.Trace.dump_on_exit = options.trace_dumponexit
diff --git a/src/sim/main.cc b/src/sim/main.cc
index 5725897f8..874d0ac85 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -317,8 +317,8 @@ simulate(Tick num_cycles = -1)
else
num_cycles = curTick + num_cycles;
- Event *limit_event = new SimLoopExitEvent(num_cycles,
- "simulate() limit reached");
+ Event *limit_event = schedExitSimLoop("simulate() limit reached",
+ num_cycles);
while (1) {
// there should always be at least one event (the SimLoopExitEvent
@@ -414,7 +414,12 @@ unserializeAll(const std::string &cpt_dir)
/**
* Queue of C++ callbacks to invoke on simulator exit.
*/
-CallbackQueue exitCallbacks;
+CallbackQueue&
+exitCallbacks()
+{
+ static CallbackQueue theQueue;
+ return theQueue;
+}
/**
* Register an exit callback.
@@ -422,7 +427,7 @@ CallbackQueue exitCallbacks;
void
registerExitCallback(Callback *callback)
{
- exitCallbacks.add(callback);
+ exitCallbacks().add(callback);
}
BaseCPU *
@@ -442,8 +447,8 @@ convertToBaseCPUPtr(SimObject *obj)
void
doExitCleanup()
{
- exitCallbacks.process();
- exitCallbacks.clear();
+ exitCallbacks().process();
+ exitCallbacks().clear();
cout.flush();
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index b66c78b2c..addf897c6 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -138,14 +138,14 @@ namespace AlphaPseudo
void
m5exit_old(ThreadContext *tc)
{
- exitSimLoop(curTick, "m5_exit_old instruction encountered");
+ exitSimLoop("m5_exit_old instruction encountered");
}
void
m5exit(ThreadContext *tc, Tick delay)
{
Tick when = curTick + delay * Clock::Int::ns;
- exitSimLoop(when, "m5_exit instruction encountered");
+ schedExitSimLoop("m5_exit instruction encountered", when);
}
void
@@ -270,7 +270,11 @@ namespace AlphaPseudo
{
if (!doCheckpointInsts)
return;
- exitSimLoop("checkpoint");
+
+ Tick when = curTick + delay * Clock::Int::ns;
+ Tick repeat = period * Clock::Int::ns;
+
+ schedExitSimLoop("checkpoint", when, repeat);
}
uint64_t
diff --git a/src/sim/root.cc b/src/sim/root.cc
index ec5e2f7e2..565b57269 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -100,7 +100,7 @@ void
Root::startup()
{
if (max_tick != 0)
- exitSimLoop(curTick + max_tick, "reached maximum cycle count");
+ schedExitSimLoop("reached maximum cycle count", curTick + max_tick);
if (progress_interval != 0)
new ProgressEvent(&mainEventQueue, progress_interval);
diff --git a/src/sim/sim_events.cc b/src/sim/sim_events.cc
index d9e8bdeaa..2ccc9dad2 100644
--- a/src/sim/sim_events.cc
+++ b/src/sim/sim_events.cc
@@ -57,6 +57,11 @@ SimLoopExitEvent::process()
// otherwise do nothing... the IsExitEvent flag takes care of
// exiting the simulation loop and returning this object to Python
+
+ // but if you are doing this on intervals, don't forget to make another
+ if (repeat) {
+ schedule(curTick + repeat);
+ }
}
@@ -66,16 +71,20 @@ SimLoopExitEvent::description()
return "simulation loop exit";
}
-void
-exitSimLoop(Tick when, const std::string &message, int exit_code)
+SimLoopExitEvent *
+schedExitSimLoop(const std::string &message, Tick when, Tick repeat,
+ EventQueue *q, int exit_code)
{
- new SimLoopExitEvent(when, message, exit_code);
+ if (q == NULL)
+ q = &mainEventQueue;
+
+ return new SimLoopExitEvent(q, when, repeat, message, exit_code);
}
void
exitSimLoop(const std::string &message, int exit_code)
{
- exitSimLoop(curTick, message, exit_code);
+ schedExitSimLoop(message, curTick, 0, NULL, exit_code);
}
void
diff --git a/src/sim/sim_events.hh b/src/sim/sim_events.hh
index 3c4a9dd05..e1576b38c 100644
--- a/src/sim/sim_events.hh
+++ b/src/sim/sim_events.hh
@@ -42,6 +42,7 @@ class SimLoopExitEvent : public Event
// string explaining why we're terminating
std::string cause;
int code;
+ Tick repeat;
public:
// Default constructor. Only really used for derived classes.
@@ -49,16 +50,19 @@ class SimLoopExitEvent : public Event
: Event(&mainEventQueue, Sim_Exit_Pri)
{ }
- SimLoopExitEvent(Tick _when, const std::string &_cause, int c = 0)
- : Event(&mainEventQueue, Sim_Exit_Pri), cause(_cause),
- code(c)
- { setFlags(IsExitEvent); schedule(_when); }
-
SimLoopExitEvent(EventQueue *q,
- Tick _when, const std::string &_cause, int c = 0)
- : Event(q, Sim_Exit_Pri), cause(_cause), code(c)
+ Tick _when, Tick _repeat, const std::string &_cause,
+ int c = 0)
+ : Event(q, Sim_Exit_Pri), cause(_cause),
+ code(c), repeat(_repeat)
{ setFlags(IsExitEvent); schedule(_when); }
+// SimLoopExitEvent(EventQueue *q,
+// Tick _when, const std::string &_cause,
+// Tick _repeat = 0, int c = 0)
+// : Event(q, Sim_Exit_Pri), cause(_cause), code(c), repeat(_repeat)
+// { setFlags(IsExitEvent); schedule(_when); }
+
std::string getCause() { return cause; }
int getCode() { return code; }
diff --git a/src/sim/sim_exit.hh b/src/sim/sim_exit.hh
index 545bf4ae0..d4b31d1ea 100644
--- a/src/sim/sim_exit.hh
+++ b/src/sim/sim_exit.hh
@@ -38,6 +38,8 @@
// forward declaration
class Callback;
+class EventQueue;
+class SimLoopExitEvent;
/// Register a callback to be called when Python exits. Defined in
/// sim/main.cc.
@@ -47,12 +49,14 @@ void registerExitCallback(Callback *);
/// Python) at the indicated tick. The message and exit_code
/// parameters are saved in the SimLoopExitEvent to indicate why the
/// exit occurred.
-void exitSimLoop(Tick when, const std::string &message, int exit_code = 0);
+SimLoopExitEvent *schedExitSimLoop(const std::string &message, Tick when,
+ Tick repeat = 0, EventQueue *q = NULL,
+ int exit_code = 0);
/// Schedule an event to exit the simulation loop (returning to
/// Python) at the end of the current cycle (curTick). The message
/// and exit_code parameters are saved in the SimLoopExitEvent to
/// indicate why the exit occurred.
-void exitSimLoop(const std::string &cause, int exit_code = 0);
+void exitSimLoop(const std::string &message, int exit_code = 0);
#endif // __SIM_EXIT_HH__
diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc
index dfed2a0c8..3fad8beb5 100644
--- a/src/sim/stat_control.cc
+++ b/src/sim/stat_control.cc
@@ -186,7 +186,7 @@ StatEvent::process()
DumpNow();
if (flags & Stats::Reset) {
- cprintf("Resetting stats!\n");
+ cprintf("Resetting stats at cycle %d!\n", curTick);
reset();
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-03-24 15:14:34 +0000