summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/python/m5/objects/Bridge.py7
-rw-r--r--src/python/m5/objects/Device.py6
2 files changed, 11 insertions, 2 deletions
diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py
index e123c2891..33b24ad3c 100644
--- a/src/python/m5/objects/Bridge.py
+++ b/src/python/m5/objects/Bridge.py
@@ -5,9 +5,12 @@ class Bridge(MemObject):
type = 'Bridge'
side_a = Port('Side A port')
side_b = Port('Side B port')
- queue_size_a = Param.Int(16, "The number of requests to buffer")
- queue_size_b = Param.Int(16, "The number of requests to buffer")
+ req_size_a = Param.Int(16, "The number of requests to buffer")
+ req_size_b = Param.Int(16, "The number of requests to buffer")
+ resp_size_a = Param.Int(16, "The number of requests to buffer")
+ resp_size_b = Param.Int(16, "The number of requests to buffer")
delay = Param.Latency('0ns', "The latency of this bridge")
+ nack_delay = Param.Latency('0ns', "The latency of this bridge")
write_ack = Param.Bool(False, "Should this bridge ack writes")
fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py
index f4b873a60..90fbfb552 100644
--- a/src/python/m5/objects/Device.py
+++ b/src/python/m5/objects/Device.py
@@ -19,6 +19,12 @@ class DmaDevice(PioDevice):
type = 'DmaDevice'
abstract = True
dma = Port(Self.pio.peerObj.port, "DMA port")
+ min_backoff_delay = Param.Latency('4ns',
+ "min time between a nack packet being received and the next request made by the device")
+ max_backoff_delay = Param.Latency('10us',
+ "max time between a nack packet being received and the next request made by the device")
+
+
class IsaFake(BasicPioDevice):
type = 'IsaFake'