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-rw-r--r--src/mem/cache/cache_impl.hh11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index cb02f7558..62b65fc42 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -2029,11 +2029,14 @@ Cache<TagStore>::CpuSidePort::recvTimingReq(PacketPtr pkt)
bool success = false;
- // always let inhibited requests through, even if blocked
+ // always let inhibited requests through, even if blocked,
+ // ultimately we should check if this is an express snoop, but at
+ // the moment that flag is only set in the cache itself
if (pkt->memInhibitAsserted()) {
- // this should always succeed
- success = cache->recvTimingReq(pkt);
- assert(success);
+ // do not change the current retry state
+ bool M5_VAR_USED bypass_success = cache->recvTimingReq(pkt);
+ assert(bypass_success);
+ return true;
} else if (blocked || mustSendRetry) {
// either already committed to send a retry, or blocked
success = false;