diff options
Diffstat (limited to 'src')
35 files changed, 407 insertions, 392 deletions
diff --git a/src/SConscript b/src/SConscript index b4bfb61fd..7c6bcd846 100755 --- a/src/SConscript +++ b/src/SConscript @@ -449,7 +449,13 @@ sys.meta_path.remove(importer) sim_objects = m5.SimObject.allClasses all_enums = m5.params.allEnums -all_params = {} +# Find param types that need to be explicitly wrapped with swig. +# These will be recognized because the ParamDesc will have a +# swig_decl() method. Most param types are based on types that don't +# need this, either because they're based on native types (like Int) +# or because they're SimObjects (which get swigged independently). +# For now the only things handled here are VectorParam types. +params_to_swig = {} for name,obj in sorted(sim_objects.iteritems()): for param in obj._params.local.values(): # load the ptype attribute now because it depends on the @@ -461,8 +467,8 @@ for name,obj in sorted(sim_objects.iteritems()): if not hasattr(param, 'swig_decl'): continue pname = param.ptype_str - if pname not in all_params: - all_params[pname] = param + if pname not in params_to_swig: + params_to_swig[pname] = param ######################################################################## # @@ -523,24 +529,23 @@ PySource('m5', 'python/m5/info.py') # Create all of the SimObject param headers and enum headers # -def createSimObjectParam(target, source, env): +def createSimObjectParamStruct(target, source, env): assert len(target) == 1 and len(source) == 1 name = str(source[0].get_contents()) obj = sim_objects[name] code = code_formatter() - obj.cxx_decl(code) + obj.cxx_param_decl(code) code.write(target[0].abspath) -def createSwigParam(target, source, env): +def createParamSwigWrapper(target, source, env): assert len(target) == 1 and len(source) == 1 name = str(source[0].get_contents()) - param = all_params[name] + param = params_to_swig[name] code = code_formatter() - code('%module(package="m5.internal") $0_${name}', param.file_ext) param.swig_decl(code) code.write(target[0].abspath) @@ -554,7 +559,7 @@ def createEnumStrings(target, source, env): obj.cxx_def(code) code.write(target[0].abspath) -def createEnumParam(target, source, env): +def createEnumDecls(target, source, env): assert len(target) == 1 and len(source) == 1 name = str(source[0].get_contents()) @@ -564,25 +569,25 @@ def createEnumParam(target, source, env): obj.cxx_decl(code) code.write(target[0].abspath) -def createEnumSwig(target, source, env): +def createEnumSwigWrapper(target, source, env): assert len(target) == 1 and len(source) == 1 name = str(source[0].get_contents()) obj = all_enums[name] code = code_formatter() - code('''\ -%module(package="m5.internal") enum_$name + obj.swig_decl(code) + code.write(target[0].abspath) -%{ -#include "enums/$name.hh" -%} +def createSimObjectSwigWrapper(target, source, env): + name = source[0].get_contents() + obj = sim_objects[name] -%include "enums/$name.hh" -''') + code = code_formatter() + obj.swig_decl(code) code.write(target[0].abspath) -# Generate all of the SimObject param struct header files +# Generate all of the SimObject param C++ struct header files params_hh_files = [] for name,simobj in sorted(sim_objects.iteritems()): py_source = PySource.modules[simobj.__module__] @@ -591,16 +596,16 @@ for name,simobj in sorted(sim_objects.iteritems()): hh_file = File('params/%s.hh' % name) params_hh_files.append(hh_file) env.Command(hh_file, Value(name), - MakeAction(createSimObjectParam, Transform("SO PARAM"))) + MakeAction(createSimObjectParamStruct, Transform("SO PARAM"))) env.Depends(hh_file, depends + extra_deps) -# Generate any parameter header files needed +# Generate any needed param SWIG wrapper files params_i_files = [] -for name,param in all_params.iteritems(): - i_file = File('python/m5/internal/%s_%s.i' % (param.file_ext, name)) +for name,param in params_to_swig.iteritems(): + i_file = File('python/m5/internal/%s.i' % (param.swig_module_name())) params_i_files.append(i_file) env.Command(i_file, Value(name), - MakeAction(createSwigParam, Transform("SW PARAM"))) + MakeAction(createParamSwigWrapper, Transform("SW PARAM"))) env.Depends(i_file, depends) SwigSource('m5.internal', i_file) @@ -617,54 +622,22 @@ for name,enum in sorted(all_enums.iteritems()): hh_file = File('enums/%s.hh' % name) env.Command(hh_file, Value(name), - MakeAction(createEnumParam, Transform("EN PARAM"))) + MakeAction(createEnumDecls, Transform("ENUMDECL"))) env.Depends(hh_file, depends + extra_deps) i_file = File('python/m5/internal/enum_%s.i' % name) env.Command(i_file, Value(name), - MakeAction(createEnumSwig, Transform("ENUMSWIG"))) + MakeAction(createEnumSwigWrapper, Transform("ENUMSWIG"))) env.Depends(i_file, depends + extra_deps) SwigSource('m5.internal', i_file) -def buildParam(target, source, env): - name = source[0].get_contents() - obj = sim_objects[name] - class_path = obj.cxx_class.split('::') - classname = class_path[-1] - namespaces = class_path[:-1] - params = obj._params.local.values() - - code = code_formatter() - - code('%module(package="m5.internal") param_$name') - code() - code('%{') - code('#include "params/$obj.hh"') - for param in params: - param.cxx_predecls(code) - code('%}') - code() - - for param in params: - param.swig_predecls(code) - - code() - if obj._base: - code('%import "python/m5/internal/param_${{obj._base}}.i"') - code() - obj.swig_objdecls(code) - code() - - code('%include "params/$obj.hh"') - - code.write(target[0].abspath) - +# Generate SimObject SWIG wrapper files for name in sim_objects.iterkeys(): - params_file = File('python/m5/internal/param_%s.i' % name) - env.Command(params_file, Value(name), - MakeAction(buildParam, Transform("BLDPARAM"))) - env.Depends(params_file, depends) - SwigSource('m5.internal', params_file) + i_file = File('python/m5/internal/param_%s.i' % name) + env.Command(i_file, Value(name), + MakeAction(createSimObjectSwigWrapper, Transform("SO SWIG"))) + env.Depends(i_file, depends) + SwigSource('m5.internal', i_file) # Generate the main swig init file def makeEmbeddedSwigInit(target, source, env): @@ -687,7 +660,7 @@ for swig in SwigSource.all: MakeAction('$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} ' '-o ${TARGETS[0]} $SOURCES', Transform("SWIG"))) cc_file = str(swig.tnode) - init_file = '%s/init_%s.cc' % (dirname(cc_file), basename(cc_file)) + init_file = '%s/%s_init.cc' % (dirname(cc_file), basename(cc_file)) env.Command(init_file, Value(swig.module), MakeAction(makeEmbeddedSwigInit, Transform("EMBED SW"))) Source(init_file, **swig.guards) diff --git a/src/arch/alpha/linux/linux.hh b/src/arch/alpha/linux/linux.hh index c728ce1fb..3304816c3 100644 --- a/src/arch/alpha/linux/linux.hh +++ b/src/arch/alpha/linux/linux.hh @@ -69,6 +69,7 @@ class AlphaLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x10; + static const unsigned TGT_MAP_FIXED = 0x100; //@{ /// For getsysinfo(). diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc index 637fbe065..4a3079264 100644 --- a/src/arch/alpha/process.cc +++ b/src/arch/alpha/process.cc @@ -126,7 +126,7 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize) stack_min = roundDown(stack_min, pageSize); stack_size = stack_base - stack_min; // map memory - pTable->allocate(stack_min, roundUp(stack_size, pageSize)); + allocateMem(stack_min, roundUp(stack_size, pageSize)); // map out initial stack contents Addr argv_array_base = stack_min + intSize; // room for argc diff --git a/src/arch/alpha/tru64/tru64.hh b/src/arch/alpha/tru64/tru64.hh index 0ee12973c..f0cad8289 100644 --- a/src/arch/alpha/tru64/tru64.hh +++ b/src/arch/alpha/tru64/tru64.hh @@ -64,6 +64,7 @@ class AlphaTru64 : public Tru64 /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x10; + static const unsigned TGT_MAP_FIXED = 0x100; //@{ /// For getsysinfo(). diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh index 33e48fc93..40d586aaf 100644 --- a/src/arch/arm/linux/linux.hh +++ b/src/arch/arm/linux/linux.hh @@ -91,6 +91,7 @@ class ArmLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// For getrusage(). diff --git a/src/arch/arm/linux/process.cc b/src/arch/arm/linux/process.cc index f17749252..c65962d00 100644 --- a/src/arch/arm/linux/process.cc +++ b/src/arch/arm/linux/process.cc @@ -503,7 +503,7 @@ void ArmLinuxProcess::initState() { ArmLiveProcess::initState(); - pTable->allocate(commPage, PageBytes); + allocateMem(commPage, PageBytes); ThreadContext *tc = system->getThreadContext(contextIds[0]); uint8_t swiNeg1[] = { diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index c3b02744e..aa5d7dfce 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -251,8 +251,7 @@ ArmLiveProcess::argsInit(int intSize, int pageSize) stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents uint32_t sentry_base = stack_base - sentry_size; diff --git a/src/arch/mips/linux/linux.hh b/src/arch/mips/linux/linux.hh index a2418cfb6..949cce8aa 100644 --- a/src/arch/mips/linux/linux.hh +++ b/src/arch/mips/linux/linux.hh @@ -65,6 +65,7 @@ class MipsLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x800; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// For getsysinfo(). diff --git a/src/arch/mips/process.cc b/src/arch/mips/process.cc index c62b60b98..5643ff18a 100644 --- a/src/arch/mips/process.cc +++ b/src/arch/mips/process.cc @@ -136,7 +136,7 @@ MipsLiveProcess::argsInit(int pageSize) stack_min = roundDown(stack_min, pageSize); stack_size = stack_base - stack_min; // map memory - pTable->allocate(stack_min, roundUp(stack_size, pageSize)); + allocateMem(stack_min, roundUp(stack_size, pageSize)); // map out initial stack contents IntType argv_array_base = stack_min + intSize; // room for argc diff --git a/src/arch/power/linux/linux.hh b/src/arch/power/linux/linux.hh index 1bfc9cbd8..45ca048a0 100644 --- a/src/arch/power/linux/linux.hh +++ b/src/arch/power/linux/linux.hh @@ -127,6 +127,7 @@ class PowerLinux : public Linux /// For mmap(). static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; //@{ /// ioctl() command codes. diff --git a/src/arch/power/process.cc b/src/arch/power/process.cc index d12e3eab6..788c7cc0c 100644 --- a/src/arch/power/process.cc +++ b/src/arch/power/process.cc @@ -187,8 +187,7 @@ PowerLiveProcess::argsInit(int intSize, int pageSize) stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents uint32_t sentry_base = stack_base - sentry_size; diff --git a/src/arch/sparc/linux/linux.hh b/src/arch/sparc/linux/linux.hh index 1f7567d43..8ac408812 100644 --- a/src/arch/sparc/linux/linux.hh +++ b/src/arch/sparc/linux/linux.hh @@ -77,6 +77,7 @@ class SparcLinux : public Linux static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; typedef struct { int64_t uptime; /* Seconds since boot */ diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc index 3eee3d137..5c594dcbc 100644 --- a/src/arch/sparc/process.cc +++ b/src/arch/sparc/process.cc @@ -316,8 +316,7 @@ SparcLiveProcess::argsInit(int pageSize) stack_size = stack_base - stack_min; // Allocate space for the stack - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents IntType sentry_base = stack_base - sentry_size; diff --git a/src/arch/sparc/solaris/solaris.hh b/src/arch/sparc/solaris/solaris.hh index df2565027..8222addab 100644 --- a/src/arch/sparc/solaris/solaris.hh +++ b/src/arch/sparc/solaris/solaris.hh @@ -59,6 +59,7 @@ class SparcSolaris : public Solaris static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x100; + static const unsigned TGT_MAP_FIXED = 0x10; }; #endif diff --git a/src/arch/x86/linux/linux.hh b/src/arch/x86/linux/linux.hh index 99b09f405..4e5d43d45 100644 --- a/src/arch/x86/linux/linux.hh +++ b/src/arch/x86/linux/linux.hh @@ -88,6 +88,7 @@ class X86Linux64 : public Linux static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; typedef struct { uint64_t iov_base; // void * @@ -158,6 +159,7 @@ class X86Linux32 : public Linux static const int NUM_OPEN_FLAGS; static const unsigned TGT_MAP_ANONYMOUS = 0x20; + static const unsigned TGT_MAP_FIXED = 0x10; typedef struct { int32_t uptime; /* Seconds since boot */ diff --git a/src/arch/x86/process.cc b/src/arch/x86/process.cc index 79a140776..f5ba787c9 100644 --- a/src/arch/x86/process.cc +++ b/src/arch/x86/process.cc @@ -167,7 +167,7 @@ X86_64LiveProcess::initState() argsInit(sizeof(uint64_t), VMPageSize); // Set up the vsyscall page for this process. - pTable->allocate(vsyscallPage.base, vsyscallPage.size); + allocateMem(vsyscallPage.base, vsyscallPage.size); uint8_t vtimeBlob[] = { 0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00, // mov $0xc9,%rax 0x0f,0x05, // syscall @@ -265,7 +265,7 @@ I386LiveProcess::initState() * Set up a GDT for this process. The whole GDT wouldn't really be for * this process, but the only parts we care about are. */ - pTable->allocate(_gdtStart, _gdtSize); + allocateMem(_gdtStart, _gdtSize); uint64_t zero = 0; assert(_gdtSize % sizeof(zero) == 0); for (Addr gdtCurrent = _gdtStart; @@ -274,7 +274,7 @@ I386LiveProcess::initState() } // Set up the vsyscall page for this process. - pTable->allocate(vsyscallPage.base, vsyscallPage.size); + allocateMem(vsyscallPage.base, vsyscallPage.size); uint8_t vsyscallBlob[] = { 0x51, // push %ecx 0x52, // push %edp @@ -577,8 +577,7 @@ X86LiveProcess::argsInit(int pageSize, stack_size = stack_base - stack_min; // map memory - pTable->allocate(roundDown(stack_min, pageSize), - roundUp(stack_size, pageSize)); + allocateMem(roundDown(stack_min, pageSize), roundUp(stack_size, pageSize)); // map out initial stack contents IntType sentry_base = stack_base - sentry_size; diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index bfdf3d486..5e2395bf9 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -75,6 +75,18 @@ PioDevice::init() pioPort->sendStatusChange(Port::RangeChange); } +Port * +PioDevice::getPort(const std::string &if_name, int idx) +{ + if (if_name == "pio") { + if (pioPort != NULL) + fatal("%s: pio port already connected to %s", + name(), pioPort->getPeer()->name()); + pioPort = new PioPort(this, sys); + return pioPort; + } + return NULL; +} unsigned int PioDevice::drain(Event *de) @@ -349,3 +361,19 @@ DmaDevice::~DmaDevice() if (dmaPort) delete dmaPort; } + + +Port * +DmaDevice::getPort(const std::string &if_name, int idx) +{ + if (if_name == "dma") { + if (dmaPort != NULL) + fatal("%s: dma port already connected to %s", + name(), dmaPort->getPeer()->name()); + dmaPort = new DmaPort(this, sys, params()->min_backoff_delay, + params()->max_backoff_delay); + return dmaPort; + } + return PioDevice::getPort(if_name, idx); +} + diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh index bc6f1d4f7..812c276d6 100644 --- a/src/dev/io_device.hh +++ b/src/dev/io_device.hh @@ -215,17 +215,8 @@ class PioDevice : public MemObject virtual unsigned int drain(Event *de); - virtual Port *getPort(const std::string &if_name, int idx = -1) - { - if (if_name == "pio") { - if (pioPort != NULL) - fatal("%s: pio port already connected to %s", - name(), pioPort->getPeer()->name()); - pioPort = new PioPort(this, sys); - return pioPort; - } else - return NULL; - } + virtual Port *getPort(const std::string &if_name, int idx = -1); + friend class PioPort; }; @@ -291,24 +282,7 @@ class DmaDevice : public PioDevice unsigned cacheBlockSize() const { return dmaPort->cacheBlockSize(); } - virtual Port *getPort(const std::string &if_name, int idx = -1) - { - if (if_name == "pio") { - if (pioPort != NULL) - fatal("%s: pio port already connected to %s", - name(), pioPort->getPeer()->name()); - pioPort = new PioPort(this, sys); - return pioPort; - } else if (if_name == "dma") { - if (dmaPort != NULL) - fatal("%s: dma port already connected to %s", - name(), dmaPort->getPeer()->name()); - dmaPort = new DmaPort(this, sys, params()->min_backoff_delay, - params()->max_backoff_delay); - return dmaPort; - } else - return NULL; - } + virtual Port *getPort(const std::string &if_name, int idx = -1); friend class DmaPort; }; diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh index 09cbb166d..4da4cfe53 100644 --- a/src/kern/tru64/tru64.hh +++ b/src/kern/tru64/tru64.hh @@ -564,7 +564,7 @@ class Tru64 : public OperatingSystem stack_base, stack_size); // map memory - process->pTable->allocate(rounded_stack_base, rounded_stack_size); + process->allocateMem(rounded_stack_base, rounded_stack_size); argp->address = gtoh(rounded_stack_base); argp.copyOut(tc->getMemPort()); @@ -683,7 +683,7 @@ class Tru64 : public OperatingSystem // Register this as a valid address range with the process base_addr = roundDown(base_addr, VMPageSize); int size = cur_addr - base_addr; - process->pTable->allocate(base_addr, roundUp(size, VMPageSize)); + process->allocateMem(base_addr, roundUp(size, VMPageSize)); config.copyOut(tc->getMemPort()); slot_state.copyOut(tc->getMemPort()); diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc index a94d92480..7622c2d48 100644 --- a/src/mem/page_table.cc +++ b/src/mem/page_table.cc @@ -45,16 +45,14 @@ #include "debug/MMU.hh" #include "mem/page_table.hh" #include "sim/faults.hh" -#include "sim/process.hh" #include "sim/sim_object.hh" -#include "sim/system.hh" using namespace std; using namespace TheISA; -PageTable::PageTable(Process *_process, Addr _pageSize) +PageTable::PageTable(const std::string &__name, uint64_t _pid, Addr _pageSize) : pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))), - process(_process) + pid(_pid), _name(__name) { assert(isPowerOf2(pageSize)); pTableCache[0].vaddr = 0; @@ -67,24 +65,20 @@ PageTable::~PageTable() } void -PageTable::allocate(Addr vaddr, int64_t size) +PageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber) { // starting address must be page aligned assert(pageOffset(vaddr) == 0); DPRINTF(MMU, "Allocating Page: %#x-%#x\n", vaddr, vaddr+ size); - for (; size > 0; size -= pageSize, vaddr += pageSize) { - PTableItr iter = pTable.find(vaddr); - - if (iter != pTable.end()) { + for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) { + if (!clobber && (pTable.find(vaddr) != pTable.end())) { // already mapped - fatal("PageTable::allocate: address 0x%x already mapped", - vaddr); + fatal("PageTable::allocate: address 0x%x already mapped", vaddr); } - pTable[vaddr] = TheISA::TlbEntry(process->M5_pid, vaddr, - process->system->new_page()); + pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr); updateCache(vaddr, pTable[vaddr]); } } @@ -111,11 +105,11 @@ PageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr) } void -PageTable::deallocate(Addr vaddr, int64_t size) +PageTable::unmap(Addr vaddr, int64_t size) { assert(pageOffset(vaddr) == 0); - DPRINTF(MMU, "Deallocating page: %#x-%#x\n", vaddr, vaddr+ size); + DPRINTF(MMU, "Unmapping page: %#x-%#x\n", vaddr, vaddr+ size); for (; size > 0; size -= pageSize, vaddr += pageSize) { PTableItr iter = pTable.find(vaddr); @@ -128,6 +122,21 @@ PageTable::deallocate(Addr vaddr, int64_t size) } bool +PageTable::isUnmapped(Addr vaddr, int64_t size) +{ + // starting address must be page aligned + assert(pageOffset(vaddr) == 0); + + for (; size > 0; size -= pageSize, vaddr += pageSize) { + if (pTable.find(vaddr) != pTable.end()) { + return false; + } + } + + return true; +} + +bool PageTable::lookup(Addr vaddr, TheISA::TlbEntry &entry) { Addr page_addr = pageAlign(vaddr); @@ -196,7 +205,7 @@ PageTable::serialize(std::ostream &os) PTableItr iter = pTable.begin(); PTableItr end = pTable.end(); while (iter != end) { - os << "\n[" << csprintf("%s.Entry%d", process->name(), count) << "]\n"; + os << "\n[" << csprintf("%s.Entry%d", name(), count) << "]\n"; paramOut(os, "vaddr", iter->first); iter->second.serialize(os); @@ -218,9 +227,9 @@ PageTable::unserialize(Checkpoint *cp, const std::string §ion) pTable.clear(); while(i < count) { - paramIn(cp, csprintf("%s.Entry%d", process->name(), i), "vaddr", vaddr); + paramIn(cp, csprintf("%s.Entry%d", name(), i), "vaddr", vaddr); entry = new TheISA::TlbEntry(); - entry->unserialize(cp, csprintf("%s.Entry%d", process->name(), i)); + entry->unserialize(cp, csprintf("%s.Entry%d", name(), i)); pTable[vaddr] = *entry; ++i; } diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh index 61da5f322..b1b5227be 100644 --- a/src/mem/page_table.hh +++ b/src/mem/page_table.hh @@ -46,8 +46,6 @@ #include "mem/request.hh" #include "sim/serialize.hh" -class Process; - /** * Page Table Declaration. */ @@ -68,20 +66,33 @@ class PageTable const Addr pageSize; const Addr offsetMask; - Process *process; + const uint64_t pid; + const std::string _name; public: - PageTable(Process *_process, Addr _pageSize = TheISA::VMPageSize); + PageTable(const std::string &__name, uint64_t _pid, + Addr _pageSize = TheISA::VMPageSize); ~PageTable(); + // for DPRINTF compatibility + const std::string name() const { return _name; } + Addr pageAlign(Addr a) { return (a & ~offsetMask); } Addr pageOffset(Addr a) { return (a & offsetMask); } - void allocate(Addr vaddr, int64_t size); + void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false); void remap(Addr vaddr, int64_t size, Addr new_vaddr); - void deallocate(Addr vaddr, int64_t size); + void unmap(Addr vaddr, int64_t size); + + /** + * Check if any pages in a region are already allocated + * @param vaddr The starting virtual address of the region. + * @param size The length of the region. + * @return True if no pages in the region are mapped. + */ + bool isUnmapped(Addr vaddr, int64_t size); /** * Lookup function diff --git a/src/mem/translating_port.cc b/src/mem/translating_port.cc index 80c68c6bd..3ea728349 100644 --- a/src/mem/translating_port.cc +++ b/src/mem/translating_port.cc @@ -86,8 +86,8 @@ TranslatingPort::tryWriteBlob(Addr addr, uint8_t *p, int size) if (!pTable->translate(gen.addr(), paddr)) { if (allocating == Always) { - pTable->allocate(roundDown(gen.addr(), VMPageSize), - VMPageSize); + process->allocateMem(roundDown(gen.addr(), VMPageSize), + VMPageSize); } else if (allocating == NextPage) { // check if we've accessed the next page on the stack if (!process->fixupStackFault(gen.addr())) @@ -123,8 +123,8 @@ TranslatingPort::tryMemsetBlob(Addr addr, uint8_t val, int size) if (!pTable->translate(gen.addr(), paddr)) { if (allocating == Always) { - pTable->allocate(roundDown(gen.addr(), VMPageSize), - VMPageSize); + process->allocateMem(roundDown(gen.addr(), VMPageSize), + VMPageSize); pTable->translate(gen.addr(), paddr); } else { return false; diff --git a/src/python/SConscript b/src/python/SConscript index cbb37d0c5..c20389344 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -66,6 +66,7 @@ PySource('m5.util', 'm5/util/terminal.py') SwigSource('m5.internal', 'swig/core.i') SwigSource('m5.internal', 'swig/debug.i') SwigSource('m5.internal', 'swig/event.i') +SwigSource('m5.internal', 'swig/pyobject.i') SwigSource('m5.internal', 'swig/range.i') SwigSource('m5.internal', 'swig/stats.i') SwigSource('m5.internal', 'swig/trace.i') diff --git a/src/python/m5/SimObject.py b/src/python/m5/SimObject.py index 9729fd30f..60693758c 100644 --- a/src/python/m5/SimObject.py +++ b/src/python/m5/SimObject.py @@ -97,37 +97,6 @@ allClasses = {} # dict to look up SimObjects based on path instanceDict = {} -def default_cxx_predecls(cls, code): - code('#include "params/$cls.hh"') - -def default_swig_predecls(cls, code): - code('%import "python/m5/internal/param_$cls.i"') - -def default_swig_objdecls(cls, code): - class_path = cls.cxx_class.split('::') - classname = class_path[-1] - namespaces = class_path[:-1] - - for ns in namespaces: - code('namespace $ns {') - - if namespaces: - code('// avoid name conflicts') - sep_string = '_COLONS_' - flat_name = sep_string.join(class_path) - code('%rename($flat_name) $classname;') - - code() - code('// stop swig from creating/wrapping default ctor/dtor') - code('%nodefault $classname;') - code('class $classname') - if cls._base: - code(' : public ${{cls._base.cxx_class}}') - code('{};') - - for ns in reversed(namespaces): - code('} // namespace $ns') - def public_value(key, value): return key.startswith('_') or \ isinstance(value, (FunctionType, MethodType, ModuleType, @@ -142,9 +111,6 @@ class MetaSimObject(type): init_keywords = { 'abstract' : bool, 'cxx_class' : str, 'cxx_type' : str, - 'cxx_predecls' : MethodType, - 'swig_objdecls' : MethodType, - 'swig_predecls' : MethodType, 'type' : str } # Attributes that can be set any time keywords = { 'check' : FunctionType } @@ -223,18 +189,20 @@ class MetaSimObject(type): cls._value_dict['cxx_class'] = cls._value_dict['type'] cls._value_dict['cxx_type'] = '%s *' % cls._value_dict['cxx_class'] - - if 'cxx_predecls' not in cls.__dict__: - m = MethodType(default_cxx_predecls, cls, MetaSimObject) - setattr(cls, 'cxx_predecls', m) - - if 'swig_predecls' not in cls.__dict__: - m = MethodType(default_swig_predecls, cls, MetaSimObject) - setattr(cls, 'swig_predecls', m) - if 'swig_objdecls' not in cls.__dict__: - m = MethodType(default_swig_objdecls, cls, MetaSimObject) - setattr(cls, 'swig_objdecls', m) + # Export methods are automatically inherited via C++, so we + # don't want the method declarations to get inherited on the + # python side (and thus end up getting repeated in the wrapped + # versions of derived classes). The code below basicallly + # suppresses inheritance by substituting in the base (null) + # versions of these methods unless a different version is + # explicitly supplied. + for method_name in ('export_methods', 'export_method_cxx_predecls', + 'export_method_swig_predecls'): + if method_name not in cls.__dict__: + base_method = getattr(MetaSimObject, method_name) + m = MethodType(base_method, cls, MetaSimObject) + setattr(cls, method_name, m) # Now process the _value_dict items. They could be defining # new (or overriding existing) parameters or ports, setting @@ -378,8 +346,99 @@ class MetaSimObject(type): def __str__(cls): return cls.__name__ - def cxx_decl(cls, code): - # The 'dict' attribute restricts us to the params declared in + # See ParamValue.cxx_predecls for description. + def cxx_predecls(cls, code): + code('#include "params/$cls.hh"') + + # See ParamValue.swig_predecls for description. + def swig_predecls(cls, code): + code('%import "python/m5/internal/param_$cls.i"') + + # Hook for exporting additional C++ methods to Python via SWIG. + # Default is none, override using @classmethod in class definition. + def export_methods(cls, code): + pass + + # Generate the code needed as a prerequisite for the C++ methods + # exported via export_methods() to be compiled in the _wrap.cc + # file. Typically generates one or more #include statements. If + # any methods are exported, typically at least the C++ header + # declaring the relevant SimObject class must be included. + def export_method_cxx_predecls(cls, code): + pass + + # Generate the code needed as a prerequisite for the C++ methods + # exported via export_methods() to be processed by SWIG. + # Typically generates one or more %include or %import statements. + # If any methods are exported, typically at least the C++ header + # declaring the relevant SimObject class must be included. + def export_method_swig_predecls(cls, code): + pass + + # Generate the declaration for this object for wrapping with SWIG. + # Generates code that goes into a SWIG .i file. Called from + # src/SConscript. + def swig_decl(cls, code): + class_path = cls.cxx_class.split('::') + classname = class_path[-1] + namespaces = class_path[:-1] + + # The 'local' attribute restricts us to the params declared in + # the object itself, not including inherited params (which + # will also be inherited from the base class's param struct + # here). + params = cls._params.local.values() + + code('%module(package="m5.internal") param_$cls') + code() + code('%{') + code('#include "params/$cls.hh"') + for param in params: + param.cxx_predecls(code) + cls.export_method_cxx_predecls(code) + code('%}') + code() + + for param in params: + param.swig_predecls(code) + cls.export_method_swig_predecls(code) + + code() + if cls._base: + code('%import "python/m5/internal/param_${{cls._base}}.i"') + code() + + for ns in namespaces: + code('namespace $ns {') + + if namespaces: + code('// avoid name conflicts') + sep_string = '_COLONS_' + flat_name = sep_string.join(class_path) + code('%rename($flat_name) $classname;') + + code() + code('// stop swig from creating/wrapping default ctor/dtor') + code('%nodefault $classname;') + code('class $classname') + if cls._base: + code(' : public ${{cls._base.cxx_class}}') + code('{') + code(' public:') + cls.export_methods(code) + code('};') + + for ns in reversed(namespaces): + code('} // namespace $ns') + + code() + code('%include "params/$cls.hh"') + + + # Generate the C++ declaration (.hh file) for this SimObject's + # param struct. Called from src/SConscript. + def cxx_param_decl(cls, code): + # The 'local' attribute restricts us to the params declared in # the object itself, not including inherited params (which # will also be inherited from the base class's param struct # here). @@ -408,6 +467,20 @@ class MetaSimObject(type): code('} // namespace $ns') code() + # The base SimObject has a couple of params that get + # automatically set from Python without being declared through + # the normal Param mechanism; we slip them in here (needed + # predecls now, actual declarations below) + if cls == SimObject: + code(''' +#ifndef PY_VERSION +struct PyObject; +#endif + +#include <string> + +struct EventQueue; +''') for param in params: param.cxx_predecls(code) code() @@ -421,65 +494,39 @@ class MetaSimObject(type): code('#include "enums/${{ptype.__name__}}.hh"') code() - cls.cxx_struct(code, cls._base, params) - - code() - code('#endif // __PARAMS__${cls}__') - return code - - def cxx_struct(cls, code, base, params): - if cls == SimObject: - code('#include "sim/sim_object_params.hh"') - return - # now generate the actual param struct code("struct ${cls}Params") - if base: - code(" : public ${{base.type}}Params") + if cls._base: + code(" : public ${{cls._base.type}}Params") code("{") if not hasattr(cls, 'abstract') or not cls.abstract: if 'type' in cls.__dict__: code(" ${{cls.cxx_type}} create();") code.indent() + if cls == SimObject: + code(''' + SimObjectParams() + { + extern EventQueue mainEventQueue; + eventq = &mainEventQueue; + } + virtual ~SimObjectParams() {} + + std::string name; + PyObject *pyobj; + EventQueue *eventq; + ''') for param in params: param.cxx_decl(code) code.dedent() code('};') - def swig_decl(cls, code): - code('''\ -%module $cls - -%{ -#include "params/$cls.hh" -%} - -''') - - # The 'dict' attribute restricts us to the params declared in - # the object itself, not including inherited params (which - # will also be inherited from the base class's param struct - # here). - params = cls._params.local.values() - ptypes = [p.ptype for p in params] - - # get all predeclarations - for param in params: - param.swig_predecls(code) code() + code('#endif // __PARAMS__${cls}__') + return code - if cls._base: - code('%import "python/m5/internal/param_${{cls._base.type}}.i"') - code() - - for ptype in ptypes: - if issubclass(ptype, Enum): - code('%import "enums/${{ptype.__name__}}.hh"') - code() - code('%import "params/${cls}_type.hh"') - code('%include "params/${cls}.hh"') # The SimObject class is the root of the special hierarchy. Most of # the code in this class deals with the configuration hierarchy itself @@ -492,8 +539,42 @@ class SimObject(object): abstract = True @classmethod - def swig_objdecls(cls, code): - code('%include "python/swig/sim_object.i"') + def export_method_cxx_predecls(cls, code): + code(''' +#include <Python.h> + +#include "sim/serialize.hh" +#include "sim/sim_object.hh" +''') + + @classmethod + def export_method_swig_predecls(cls, code): + code(''' +%include <std_string.i> +''') + + @classmethod + def export_methods(cls, code): + code(''' + enum State { + Running, + Draining, + Drained + }; + + void init(); + void loadState(Checkpoint *cp); + void initState(); + void regStats(); + void regFormulas(); + void resetStats(); + void startup(); + + unsigned int drain(Event *drain_event); + void resume(); + void switchOut(); + void takeOverFrom(BaseCPU *cpu); +''') # Initialize new instance. For objects with SimObject-valued # children, we need to recursively clone the classes represented diff --git a/src/python/m5/params.py b/src/python/m5/params.py index ee94ae004..4575e677f 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -81,10 +81,17 @@ class MetaParamValue(type): class ParamValue(object): __metaclass__ = MetaParamValue + + # Generate the code needed as a prerequisite for declaring a C++ + # object of this type. Typically generates one or more #include + # statements. Used when declaring parameters of this type. @classmethod def cxx_predecls(cls, code): pass + # Generate the code needed as a prerequisite for including a + # reference to a C++ object of this type in a SWIG .i file. + # Typically generates one or more %import or %include statements. @classmethod def swig_predecls(cls, code): pass @@ -101,8 +108,6 @@ class ParamValue(object): # Regular parameter description. class ParamDesc(object): - file_ext = 'ptype' - def __init__(self, ptype_str, ptype, *args, **kwargs): self.ptype_str = ptype_str # remember ptype only if it is provided @@ -223,8 +228,6 @@ class SimObjectVector(VectorParamValue): yield obj class VectorParamDesc(ParamDesc): - file_ext = 'vptype' - # Convert assigned value to appropriate type. If the RHS is not a # list or tuple, it generates a single-element list. def convert(self, value): @@ -240,10 +243,14 @@ class VectorParamDesc(ParamDesc): else: return VectorParamValue(tmp_list) + def swig_module_name(self): + return "%s_vector" % self.ptype_str + def swig_predecls(self, code): - code('%import "vptype_${{self.ptype_str}}.i"') + code('%import "${{self.swig_module_name()}}.i"') def swig_decl(self, code): + code('%module(package="m5.internal") ${{self.swig_module_name()}}') code('%{') self.ptype.cxx_predecls(code) code('%}') @@ -1043,6 +1050,19 @@ namespace Enums { } // namespace Enums ''') + def swig_decl(cls, code): + name = cls.__name__ + code('''\ +%module(package="m5.internal") enum_$name + +%{ +#include "enums/$name.hh" +%} + +%include "enums/$name.hh" +''') + + # Base class for enum types. class Enum(ParamValue): __metaclass__ = MetaEnum @@ -1362,7 +1382,7 @@ class PortRef(object): # Call C++ to create corresponding port connection between C++ objects def ccConnect(self): - from m5.internal.params import connectPorts + from m5.internal.pyobject import connectPorts if self.ccConnected: # already done this return diff --git a/src/python/swig/sim_object.i b/src/python/swig/pyobject.i index 06f683aa1..a26f569ce 100644 --- a/src/python/swig/sim_object.i +++ b/src/python/swig/pyobject.i @@ -28,6 +28,8 @@ * Authors: Nathan Binkert */ +%module(package="m5.internal") pyobject + %{ #include "python/swig/pyobject.hh" %} @@ -36,34 +38,6 @@ %include <std_string.i> %include <stdint.i> -%include "base/types.hh" -%include "sim/sim_object_params.hh" - -class BaseCPU; - -class SimObject { - public: - enum State { - Running, - Draining, - Drained - }; - - void init(); - void loadState(Checkpoint *cp); - void initState(); - void regStats(); - void regFormulas(); - void resetStats(); - void startup(); - - unsigned int drain(Event *drain_event); - void resume(); - void switchOut(); - void takeOverFrom(BaseCPU *cpu); - SimObject(const SimObjectParams *p); -}; - int connectPorts(SimObject *o1, const std::string &name1, int i1, SimObject *o2, const std::string &name2, int i2); diff --git a/src/python/swig/system.i b/src/python/swig/system.i deleted file mode 100644 index 1aadcecc6..000000000 --- a/src/python/swig/system.i +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Nathan Binkert - */ - -%{ -#include "sim/system.hh" -%} - -%import "enums/MemoryMode.hh" -%import "python/swig/sim_object.i" - -class System : public SimObject -{ - private: - System(); - public: - Enums::MemoryMode getMemoryMode(); - void setMemoryMode(Enums::MemoryMode mode); -}; - diff --git a/src/sim/System.py b/src/sim/System.py index a6897d834..d9836211f 100644 --- a/src/sim/System.py +++ b/src/sim/System.py @@ -41,8 +41,15 @@ class System(SimObject): type = 'System' @classmethod - def swig_objdecls(cls, code): - code('%include "python/swig/system.i"') + def export_method_cxx_predecls(cls, code): + code('#include "sim/system.hh"') + + @classmethod + def export_methods(cls, code): + code(''' + Enums::MemoryMode getMemoryMode(); + void setMemoryMode(Enums::MemoryMode mode); +''') physmem = Param.PhysicalMemory("Physical Memory") mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in") diff --git a/src/sim/process.cc b/src/sim/process.cc index 62b9b7002..ba106fb63 100644 --- a/src/sim/process.cc +++ b/src/sim/process.cc @@ -169,7 +169,7 @@ Process::Process(ProcessParams * params) mmap_start = mmap_end = 0; nxm_start = nxm_end = 0; - pTable = new PageTable(this); + pTable = new PageTable(name(), M5_pid); // other parameters will be initialized when the program is loaded } @@ -328,13 +328,21 @@ Process::sim_fd_obj(int tgt_fd) return &fd_map[tgt_fd]; } +void +Process::allocateMem(Addr vaddr, int64_t size, bool clobber) +{ + int npages = divCeil(size, (int64_t)VMPageSize); + Addr paddr = system->allocPhysPages(npages); + pTable->map(vaddr, paddr, size, clobber); +} + bool Process::fixupStackFault(Addr vaddr) { // Check if this is already on the stack and there's just no page there // yet. if (vaddr >= stack_min && vaddr < stack_base) { - pTable->allocate(roundDown(vaddr, VMPageSize), VMPageSize); + allocateMem(roundDown(vaddr, VMPageSize), VMPageSize); return true; } @@ -347,7 +355,7 @@ Process::fixupStackFault(Addr vaddr) fatal("Maximum stack size exceeded\n"); if (stack_base - stack_min > 8 * 1024 * 1024) fatal("Over max stack size for one thread\n"); - pTable->allocate(stack_min, TheISA::PageBytes); + allocateMem(stack_min, TheISA::PageBytes); inform("Increasing stack size by one page."); }; return true; diff --git a/src/sim/process.hh b/src/sim/process.hh index d48b1b463..4c31597b4 100644 --- a/src/sim/process.hh +++ b/src/sim/process.hh @@ -212,6 +212,8 @@ class Process : public SimObject virtual void syscall(int64_t callnum, ThreadContext *tc) = 0; + void allocateMem(Addr vaddr, int64_t size, bool clobber = false); + /// Attempt to fix up a fault at vaddr by allocating a page on the stack. /// @return Whether the fault has been fixed. bool fixupStackFault(Addr vaddr); diff --git a/src/sim/sim_object_params.hh b/src/sim/sim_object_params.hh deleted file mode 100644 index 750181135..000000000 --- a/src/sim/sim_object_params.hh +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2001-2005 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Steve Reinhardt - * Nathan Binkert - */ - -#ifndef __SIM_SIM_OBJECT_PARAMS_HH__ -#define __SIM_SIM_OBJECT_PARAMS_HH__ - -#ifndef PY_VERSION -struct PyObject; -#endif - -#include <string> - -struct EventQueue; - -struct SimObjectParams -{ - SimObjectParams() - { - extern EventQueue mainEventQueue; - eventq = &mainEventQueue; - } - virtual ~SimObjectParams() {} - - std::string name; - PyObject *pyobj; - EventQueue *eventq; -}; - - -#endif // __SIM_SIM_OBJECT_PARAMS_HH__ diff --git a/src/sim/syscall_emul.cc b/src/sim/syscall_emul.cc index 6873d4aa4..203eaff2a 100644 --- a/src/sim/syscall_emul.cc +++ b/src/sim/syscall_emul.cc @@ -166,8 +166,7 @@ brkFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc) for (ChunkGenerator gen(p->brk_point, new_brk - p->brk_point, VMPageSize); !gen.done(); gen.next()) { if (!p->pTable->translate(gen.addr())) - p->pTable->allocate(roundDown(gen.addr(), VMPageSize), - VMPageSize); + p->allocateMem(roundDown(gen.addr(), VMPageSize), VMPageSize); // if the address is already there, zero it out else { diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index d119adc24..50bf1a52f 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -677,7 +677,7 @@ mremapFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ThreadContext * if (new_length > old_length) { if ((start + old_length) == process->mmap_end) { uint64_t diff = new_length - old_length; - process->pTable->allocate(process->mmap_end, diff); + process->allocateMem(process->mmap_end, diff); process->mmap_end += diff; return start; } else { @@ -691,15 +691,15 @@ mremapFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ThreadContext * process->mmap_end, process->mmap_end + new_length, new_length); start = process->mmap_end; // add on the remaining unallocated pages - process->pTable->allocate(start + old_length, new_length - old_length); + process->allocateMem(start + old_length, + new_length - old_length); process->mmap_end += new_length; warn("returning %08p as start\n", start); return start; } } } else { - process->pTable->deallocate(start + new_length, old_length - - new_length); + process->pTable->unmap(start + new_length, old_length - new_length); return start; } } @@ -1027,20 +1027,45 @@ mmapFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc) return -EINVAL; } - if (start != 0) { - warn("mmap: ignoring suggested map address 0x%x, using 0x%x", - start, p->mmap_end); + // are we ok with clobbering existing mappings? only set this to + // true if the user has been warned. + bool clobber = false; + + // try to use the caller-provided address if there is one + bool use_provided_address = (start != 0); + + if (use_provided_address) { + // check to see if the desired address is already in use + if (!p->pTable->isUnmapped(start, length)) { + // there are existing mappings in the desired range + // whether we clobber them or not depends on whether the caller + // specified MAP_FIXED + if (flags & OS::TGT_MAP_FIXED) { + // MAP_FIXED specified: clobber existing mappings + warn("mmap: MAP_FIXED at 0x%x overwrites existing mappings\n", + start); + clobber = true; + } else { + // MAP_FIXED not specified: ignore suggested start address + warn("mmap: ignoring suggested map address 0x%x\n", start); + use_provided_address = false; + } + } } - // pick next address from our "mmap region" - if (OS::mmapGrowsDown()) { - start = p->mmap_end - length; - p->mmap_end = start; - } else { - start = p->mmap_end; - p->mmap_end += length; + if (!use_provided_address) { + // no address provided, or provided address unusable: + // pick next address from our "mmap region" + if (OS::mmapGrowsDown()) { + start = p->mmap_end - length; + p->mmap_end = start; + } else { + start = p->mmap_end; + p->mmap_end += length; + } } - p->pTable->allocate(start, length); + + p->allocateMem(start, length, clobber); return start; } diff --git a/src/sim/system.cc b/src/sim/system.cc index 81a8a0574..c58830c10 100644 --- a/src/sim/system.cc +++ b/src/sim/system.cc @@ -275,10 +275,10 @@ System::replaceThreadContext(ThreadContext *tc, int context_id) #if !FULL_SYSTEM Addr -System::new_page() +System::allocPhysPages(int npages) { Addr return_addr = pagePtr << LogVMPageSize; - ++pagePtr; + pagePtr += npages; if (return_addr >= physmem->size()) fatal("Out of memory, please increase size of physical memory."); return return_addr; diff --git a/src/sim/system.hh b/src/sim/system.hh index a6bc47fc0..ed5193dfd 100644 --- a/src/sim/system.hh +++ b/src/sim/system.hh @@ -287,7 +287,9 @@ class System : public SimObject #else - Addr new_page(); + /// Allocate npages contiguous unused physical pages + /// @return Starting address of first page + Addr allocPhysPages(int npages); #endif // FULL_SYSTEM |