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-rw-r--r--src/cpu/inorder/cpu.cc13
-rw-r--r--src/cpu/inorder/cpu.hh1
-rw-r--r--src/cpu/inorder/pipeline_stage.cc20
-rw-r--r--src/cpu/inorder/pipeline_stage.hh15
-rw-r--r--src/cpu/inorder/reg_dep_map.cc8
-rw-r--r--src/cpu/inorder/reg_dep_map.hh2
-rw-r--r--src/cpu/inorder/resource.cc7
7 files changed, 43 insertions, 23 deletions
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 196682621..4130b9e14 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -356,6 +356,17 @@ InOrderCPU::InOrderCPU(Params *params)
InOrderCPU::~InOrderCPU()
{
delete resPool;
+
+ std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_it =
+ skedCache.begin();
+ std::map<SkedID, ThePipeline::RSkedPtr>::iterator sked_end =
+ skedCache.end();
+
+ while (sked_it != sked_end) {
+ delete (*sked_it).second;
+ sked_it++;
+ }
+ skedCache.clear();
}
std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
@@ -460,7 +471,7 @@ InOrderCPU::createBackEndSked(DynInstPtr inst)
W.needs(Grad, GraduationUnit::GraduateInst);
- // Insert Front Schedule into our cache of
+ // Insert Back Schedule into our cache of
// resource schedules
addToSkedCache(inst, res_sked);
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 073a0a982..2fa6bdc59 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -315,6 +315,7 @@ class InOrderCPU : public BaseCPU
void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
{
SkedID sked_id = genSkedID(inst);
+ assert(skedCache.find(sked_id) == skedCache.end());
skedCache[sked_id] = inst_sked;
}
diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index 15f143251..b267ac00e 100644
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -44,12 +44,17 @@ PipelineStage::PipelineStage(Params *params, unsigned stage_num)
stageBufferMax(params->stageWidth),
prevStageValid(false), nextStageValid(false), idle(false)
{
- switchedOutBuffer.resize(ThePipeline::MaxThreads);
- switchedOutValid.resize(ThePipeline::MaxThreads);
-
init(params);
}
+PipelineStage::~PipelineStage()
+{
+ for(ThreadID tid = 0; tid < numThreads; tid++) {
+ skidBuffer[tid].clear();
+ stalls[tid].resources.clear();
+ }
+}
+
void
PipelineStage::init(Params *params)
{
@@ -66,6 +71,12 @@ PipelineStage::init(Params *params)
else
lastStallingStage[tid] = NumStages - 1;
}
+
+ if ((InOrderCPU::ThreadModel) params->threadModel ==
+ InOrderCPU::SwitchOnCacheMiss) {
+ switchedOutBuffer.resize(ThePipeline::MaxThreads);
+ switchedOutValid.resize(ThePipeline::MaxThreads);
+ }
}
@@ -190,9 +201,6 @@ PipelineStage::takeOverFrom()
stalls[tid].resources.clear();
- while (!insts[tid].empty())
- insts[tid].pop();
-
skidBuffer[tid].clear();
}
wroteToTimeBuffer = false;
diff --git a/src/cpu/inorder/pipeline_stage.hh b/src/cpu/inorder/pipeline_stage.hh
index dfa88de87..ec70fefc5 100644
--- a/src/cpu/inorder/pipeline_stage.hh
+++ b/src/cpu/inorder/pipeline_stage.hh
@@ -91,10 +91,7 @@ class PipelineStage
public:
PipelineStage(Params *params, unsigned stage_num);
- /** MUST use init() function if this constructor is used. */
- PipelineStage() { }
-
- virtual ~PipelineStage() { }
+ virtual ~PipelineStage();
/** PipelineStage initialization. */
void init(Params *params);
@@ -268,16 +265,6 @@ class PipelineStage
*/
unsigned instsProcessed;
- /** Queue of all instructions coming from previous stage on this cycle. */
- std::queue<DynInstPtr> insts[ThePipeline::MaxThreads];
-
- /** Queue of instructions that are finished processing and ready to go
- * next stage. This is used to prevent from processing an instrution more
- * than once on any stage. NOTE: It is up to the PROGRAMMER must manage
- * this as a queue
- */
- std::list<DynInstPtr> instsToNextStage;
-
/** Skid buffer between previous stage and this one. */
std::list<DynInstPtr> skidBuffer[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/reg_dep_map.cc b/src/cpu/inorder/reg_dep_map.cc
index 98a0727a9..48820b50e 100644
--- a/src/cpu/inorder/reg_dep_map.cc
+++ b/src/cpu/inorder/reg_dep_map.cc
@@ -45,6 +45,14 @@ RegDepMap::RegDepMap(int size)
regMap.resize(size);
}
+RegDepMap::~RegDepMap()
+{
+ for (int i = 0; i < regMap.size(); i++) {
+ regMap[i].clear();
+ }
+ regMap.clear();
+}
+
string
RegDepMap::name()
{
diff --git a/src/cpu/inorder/reg_dep_map.hh b/src/cpu/inorder/reg_dep_map.hh
index fa4fe45f3..047e4d129 100644
--- a/src/cpu/inorder/reg_dep_map.hh
+++ b/src/cpu/inorder/reg_dep_map.hh
@@ -48,7 +48,7 @@ class RegDepMap
public:
RegDepMap(int size = TheISA::TotalNumRegs);
- ~RegDepMap() { }
+ ~RegDepMap();
std::string name();
diff --git a/src/cpu/inorder/resource.cc b/src/cpu/inorder/resource.cc
index c371f8244..6a2f5e62a 100644
--- a/src/cpu/inorder/resource.cc
+++ b/src/cpu/inorder/resource.cc
@@ -53,7 +53,11 @@ Resource::~Resource()
delete [] resourceEvent;
}
- delete deniedReq;
+ delete deniedReq;
+
+ for (int i = 0; i < width; i++) {
+ delete reqs[i];
+ }
}
@@ -386,6 +390,7 @@ ResourceRequest::~ResourceRequest()
DPRINTF(ResReqCount, "Res. Req %i deleted. resReqCount=%i.\n", reqID,
res->cpu->resReqCount);
#endif
+ inst = NULL;
}
void