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-rw-r--r--src/arch/arm/tlb.cc7
-rw-r--r--src/arch/arm/tlb.hh6
2 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 94343c1c2..7f296e7cf 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -197,6 +197,7 @@ TLB::insert(Addr addr, TlbEntry &entry)
table[0] = entry;
inserts++;
+ ppRefills->notify(1);
}
void
@@ -531,6 +532,12 @@ TLB::regStats()
accesses = readAccesses + writeAccesses + instAccesses;
}
+void
+TLB::regProbePoints()
+{
+ ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills"));
+}
+
Fault
TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
Translation *translation, bool &delay, bool timing)
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index b9025fa5f..06a51e5da 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -53,6 +53,7 @@
#include "mem/request.hh"
#include "params/ArmTLB.hh"
#include "sim/fault_fwd.hh"
+#include "sim/probe/pmu.hh"
#include "sim/tlb.hh"
class ThreadContext;
@@ -131,6 +132,9 @@ class TLB : public BaseTLB
Stats::Formula misses;
Stats::Formula accesses;
+ /** PMU probe for TLB refills */
+ ProbePoints::PMUUPtr ppRefills;
+
int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
bool bootUncacheability;
@@ -291,6 +295,8 @@ class TLB : public BaseTLB
void regStats();
+ void regProbePoints() M5_ATTR_OVERRIDE;
+
/**
* Get the table walker master port. This is used for migrating
* port connections during a CPU takeOverFrom() call. For