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-rw-r--r--src/cpu/simple/atomic.cc2
-rw-r--r--src/cpu/simple/base.cc6
-rw-r--r--src/cpu/simple/base.hh9
-rw-r--r--src/cpu/simple/timing.cc2
4 files changed, 13 insertions, 6 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 2254d44d5..23bd40b9b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -713,6 +713,8 @@ AtomicSimpleCPU::tick()
if (!curStaticInst || !curStaticInst->isDelayedCommit())
checkForInterrupts();
+ checkPcEventQueue();
+
Fault fault = setupFetchRequest(&ifetch_req);
if (fault == NoFault) {
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 367f38b89..4a91a9e12 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -494,12 +494,6 @@ BaseSimpleCPU::advancePC(Fault fault)
assert(thread->readNextPC() != thread->readNextNPC());
}
}
-
- Addr oldpc;
- do {
- oldpc = thread->readPC();
- system->pcEventQueue.service(tc);
- } while (oldpc != thread->readPC());
}
/*Fault
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 82f73e5dd..8c162a846 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -44,6 +44,7 @@
#include "mem/port.hh"
#include "mem/request.hh"
#include "sim/eventq.hh"
+#include "sim/system.hh"
// forward declarations
#if FULL_SYSTEM
@@ -86,6 +87,14 @@ class BaseSimpleCPU : public BaseCPU
protected:
Trace::InstRecord *traceData;
+ inline void checkPcEventQueue() {
+ Addr oldpc;
+ do {
+ oldpc = thread->readPC();
+ system->pcEventQueue.service(tc);
+ } while (oldpc != thread->readPC());
+ }
+
public:
void post_interrupt(int int_num, int index);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9fe3d2fff..a76824ff3 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -522,6 +522,8 @@ TimingSimpleCPU::fetch()
if (!curStaticInst || !curStaticInst->isDelayedCommit())
checkForInterrupts();
+ checkPcEventQueue();
+
Request *ifetch_req = new Request();
ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
Fault fault = setupFetchRequest(ifetch_req);