diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/riscv/isa/bitfields.isa | 8 | ||||
-rw-r--r-- | src/arch/riscv/isa/decoder.isa | 15 | ||||
-rw-r--r-- | src/arch/riscv/isa/formats/compressed.isa | 24 |
3 files changed, 34 insertions, 13 deletions
diff --git a/src/arch/riscv/isa/bitfields.isa b/src/arch/riscv/isa/bitfields.isa index 903fce385..20f1fc0de 100644 --- a/src/arch/riscv/isa/bitfields.isa +++ b/src/arch/riscv/isa/bitfields.isa @@ -104,6 +104,14 @@ def bitfield FC1 <11:7>; def bitfield FC2 <6:2>; def bitfield FP2 <4:2>; def bitfield CJUMPIMM <12:2>; +def bitfield CJUMPIMM3TO1 <5:3>; +def bitfield CJUMPIMM4TO4 <11:11>; +def bitfield CJUMPIMM5TO5 <2:2>; +def bitfield CJUMPIMM6TO6 <7:7>; +def bitfield CJUMPIMM7TO7 <6:6>; +def bitfield CJUMPIMM9TO8 <10:9>; +def bitfield CJUMPIMM10TO10 <8:8>; +def bitfield CJUMPIMMSIGN <12:12>; def bitfield CIMM8 <12:5>; def bitfield CIMM6 <12:7>; def bitfield CIMM5 <6:2>; diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 8de4829a6..8fcfba6ca 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -224,18 +224,9 @@ decode QUADRANT default Unknown::unknown() { } } } - 0x5: JOp::c_j({{ - int64_t offset = CJUMPIMM<3:1> << 1 | - CJUMPIMM<9:9> << 4 | - CJUMPIMM<0:0> << 5 | - CJUMPIMM<5:5> << 6 | - CJUMPIMM<4:4> << 7 | - CJUMPIMM<8:7> << 8 | - CJUMPIMM<6:6> << 10; - if (CJUMPIMM<10:10> > 0) - offset |= ~((int64_t)0x7FF); - NPC = PC + offset; - }}, IsIndirectControl, IsUncondControl, IsCall); + 0x5: CJOp::c_j({{ + NPC = PC + imm; + }}, IsDirectControl, IsUncondControl); format CBOp { 0x6: c_beqz({{ if (Rp1 == 0) diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa index 3ebc1c6ae..b520d53eb 100644 --- a/src/arch/riscv/isa/formats/compressed.isa +++ b/src/arch/riscv/isa/formats/compressed.isa @@ -47,6 +47,28 @@ def format CIOp(imm_code, code, imm_type='int64_t', *opt_flags) {{ exec_output = ImmExecute.subst(iop) }}; +def format CJOp(code, *opt_flags) {{ + regs = ['_destRegIdx[0]', '_srcRegIdx[0]'] + imm_code = """ + imm = CJUMPIMM3TO1 << 1 | + CJUMPIMM4TO4 << 4 | + CJUMPIMM5TO5 << 5 | + CJUMPIMM6TO6 << 6 | + CJUMPIMM7TO7 << 7 | + CJUMPIMM9TO8 << 8 | + CJUMPIMM10TO10 << 10; + if (CJUMPIMMSIGN) + imm |= ~((int64_t)0x7FF); + """ + iop = InstObjParams(name, Name, 'ImmOp<int64_t>', + {'code': code, 'imm_code': imm_code, + 'regs': ','.join(regs)}, opt_flags) + header_output = BranchDeclare.subst(iop) + decoder_output = ImmConstructor.subst(iop) + decode_block = BasicDecode.subst(iop) + exec_output = BranchExecute.subst(iop) +}}; + def format CBOp(code, *opt_flags) {{ imm_code = """ imm = CIMM5<2:1> << 1 | @@ -78,4 +100,4 @@ def format CompressedStore(sdisp_code, memacc_code, (header_output, decoder_output, decode_block, exec_output) = \ LoadStoreBase(name, Name, sdisp_code, ea_code, memacc_code, mem_flags, inst_flags, 'Store', exec_template_base='Store') -}};
\ No newline at end of file +}}; |