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-rw-r--r--src/arch/alpha/isa/decoder.isa2
-rw-r--r--src/arch/sparc/system.cc12
-rw-r--r--src/cpu/base.cc11
-rw-r--r--src/cpu/simple/atomic.cc4
-rw-r--r--src/mem/cache/cache_impl.hh4
-rw-r--r--src/sim/main.cc4
-rw-r--r--src/sim/pseudo_inst.cc10
-rw-r--r--src/sim/root.cc2
-rw-r--r--src/sim/sim_events.cc17
-rw-r--r--src/sim/sim_events.hh18
-rw-r--r--src/sim/sim_exit.hh8
11 files changed, 53 insertions, 39 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa
index 4fc9da3f3..5bd19b677 100644
--- a/src/arch/alpha/isa/decoder.isa
+++ b/src/arch/alpha/isa/decoder.isa
@@ -701,7 +701,7 @@ decode OPCODE default Unknown::unknown() {
0x00: decode PALFUNC {
format EmulatedCallPal {
0x00: halt ({{
- exitSimLoop(curTick, "halt instruction encountered");
+ exitSimLoop("halt instruction encountered");
}}, IsNonSpeculative);
0x83: callsys({{
xc->syscall(R0);
diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc
index 63cbbe057..ef6443d17 100644
--- a/src/arch/sparc/system.cc
+++ b/src/arch/sparc/system.cc
@@ -152,10 +152,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
Param<std::string> readfile;
Param<unsigned int> init_param;
- Param<bool> bin;
- VectorParam<std::string> binned_fns;
- Param<bool> bin_int;
-
END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
@@ -173,10 +169,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
- INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10),
- INIT_PARAM_DFLT(bin, "is this system to be binned", false),
- INIT_PARAM(binned_fns, "functions to be broken down and binned"),
- INIT_PARAM_DFLT(bin_int, "is interrupt code binned seperately?", true)
+ INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
END_INIT_SIM_OBJECT_PARAMS(SparcSystem)
@@ -196,9 +189,6 @@ CREATE_SIM_OBJECT(SparcSystem)
p->readfile = readfile;
p->system_type = system_type;
p->system_rev = system_rev;
- p->bin = bin;
- p->binned_fns = binned_fns;
- p->bin_int = bin_int;
return new SparcSystem(p);
}
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 513dd7c55..ea4b03bf2 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -41,6 +41,7 @@
#include "cpu/cpuevent.hh"
#include "cpu/thread_context.hh"
#include "cpu/profile.hh"
+#include "sim/sim_exit.hh"
#include "sim/param.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
@@ -125,8 +126,9 @@ BaseCPU::BaseCPU(Params *p)
//
if (p->max_insts_any_thread != 0)
for (int i = 0; i < number_of_threads; ++i)
- new SimLoopExitEvent(comInstEventQueue[i], p->max_insts_any_thread,
- "a thread reached the max instruction count");
+ schedExitSimLoop("a thread reached the max instruction count",
+ p->max_insts_any_thread, 0,
+ comInstEventQueue[i]);
if (p->max_insts_all_threads != 0) {
// allocate & initialize shared downcounter: each event will
@@ -150,8 +152,9 @@ BaseCPU::BaseCPU(Params *p)
//
if (p->max_loads_any_thread != 0)
for (int i = 0; i < number_of_threads; ++i)
- new SimLoopExitEvent(comLoadEventQueue[i], p->max_loads_any_thread,
- "a thread reached the max load count");
+ schedExitSimLoop("a thread reached the max load count",
+ p->max_loads_any_thread, 0,
+ comLoadEventQueue[i]);
if (p->max_loads_all_threads != 0) {
// allocate & initialize shared downcounter: each event will
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 7ba1b7df1..88698bfee 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -161,9 +161,9 @@ AtomicSimpleCPU::serialize(ostream &os)
{
SimObject::State so_state = SimObject::getState();
SERIALIZE_ENUM(so_state);
+ BaseSimpleCPU::serialize(os);
nameOut(os, csprintf("%s.tickEvent", name()));
tickEvent.serialize(os);
- BaseSimpleCPU::serialize(os);
}
void
@@ -171,8 +171,8 @@ AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
{
SimObject::State so_state;
UNSERIALIZE_ENUM(so_state);
- tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
BaseSimpleCPU::unserialize(cp, section);
+ tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
}
void
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 228cd2d73..00fecc2b7 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -51,7 +51,7 @@
#include "mem/cache/miss/mshr.hh"
#include "mem/cache/prefetch/prefetcher.hh"
-#include "sim/sim_events.hh" // for SimExitEvent
+#include "sim/sim_exit.hh" // for SimExitEvent
template<class TagStore, class Buffering, class Coherence>
bool
@@ -263,7 +263,7 @@ Cache<TagStore,Buffering,Coherence>::access(PacketPtr &pkt)
if (missCount) {
--missCount;
if (missCount == 0)
- new SimLoopExitEvent(curTick, "A cache reached the maximum miss count");
+ exitSimLoop("A cache reached the maximum miss count");
}
}
missQueue->handleMiss(pkt, size, curTick + hitLatency);
diff --git a/src/sim/main.cc b/src/sim/main.cc
index 728b7b810..874d0ac85 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -317,8 +317,8 @@ simulate(Tick num_cycles = -1)
else
num_cycles = curTick + num_cycles;
- Event *limit_event = new SimLoopExitEvent(num_cycles,
- "simulate() limit reached");
+ Event *limit_event = schedExitSimLoop("simulate() limit reached",
+ num_cycles);
while (1) {
// there should always be at least one event (the SimLoopExitEvent
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index b66c78b2c..addf897c6 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -138,14 +138,14 @@ namespace AlphaPseudo
void
m5exit_old(ThreadContext *tc)
{
- exitSimLoop(curTick, "m5_exit_old instruction encountered");
+ exitSimLoop("m5_exit_old instruction encountered");
}
void
m5exit(ThreadContext *tc, Tick delay)
{
Tick when = curTick + delay * Clock::Int::ns;
- exitSimLoop(when, "m5_exit instruction encountered");
+ schedExitSimLoop("m5_exit instruction encountered", when);
}
void
@@ -270,7 +270,11 @@ namespace AlphaPseudo
{
if (!doCheckpointInsts)
return;
- exitSimLoop("checkpoint");
+
+ Tick when = curTick + delay * Clock::Int::ns;
+ Tick repeat = period * Clock::Int::ns;
+
+ schedExitSimLoop("checkpoint", when, repeat);
}
uint64_t
diff --git a/src/sim/root.cc b/src/sim/root.cc
index ec5e2f7e2..565b57269 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -100,7 +100,7 @@ void
Root::startup()
{
if (max_tick != 0)
- exitSimLoop(curTick + max_tick, "reached maximum cycle count");
+ schedExitSimLoop("reached maximum cycle count", curTick + max_tick);
if (progress_interval != 0)
new ProgressEvent(&mainEventQueue, progress_interval);
diff --git a/src/sim/sim_events.cc b/src/sim/sim_events.cc
index d9e8bdeaa..2ccc9dad2 100644
--- a/src/sim/sim_events.cc
+++ b/src/sim/sim_events.cc
@@ -57,6 +57,11 @@ SimLoopExitEvent::process()
// otherwise do nothing... the IsExitEvent flag takes care of
// exiting the simulation loop and returning this object to Python
+
+ // but if you are doing this on intervals, don't forget to make another
+ if (repeat) {
+ schedule(curTick + repeat);
+ }
}
@@ -66,16 +71,20 @@ SimLoopExitEvent::description()
return "simulation loop exit";
}
-void
-exitSimLoop(Tick when, const std::string &message, int exit_code)
+SimLoopExitEvent *
+schedExitSimLoop(const std::string &message, Tick when, Tick repeat,
+ EventQueue *q, int exit_code)
{
- new SimLoopExitEvent(when, message, exit_code);
+ if (q == NULL)
+ q = &mainEventQueue;
+
+ return new SimLoopExitEvent(q, when, repeat, message, exit_code);
}
void
exitSimLoop(const std::string &message, int exit_code)
{
- exitSimLoop(curTick, message, exit_code);
+ schedExitSimLoop(message, curTick, 0, NULL, exit_code);
}
void
diff --git a/src/sim/sim_events.hh b/src/sim/sim_events.hh
index 3c4a9dd05..e1576b38c 100644
--- a/src/sim/sim_events.hh
+++ b/src/sim/sim_events.hh
@@ -42,6 +42,7 @@ class SimLoopExitEvent : public Event
// string explaining why we're terminating
std::string cause;
int code;
+ Tick repeat;
public:
// Default constructor. Only really used for derived classes.
@@ -49,16 +50,19 @@ class SimLoopExitEvent : public Event
: Event(&mainEventQueue, Sim_Exit_Pri)
{ }
- SimLoopExitEvent(Tick _when, const std::string &_cause, int c = 0)
- : Event(&mainEventQueue, Sim_Exit_Pri), cause(_cause),
- code(c)
- { setFlags(IsExitEvent); schedule(_when); }
-
SimLoopExitEvent(EventQueue *q,
- Tick _when, const std::string &_cause, int c = 0)
- : Event(q, Sim_Exit_Pri), cause(_cause), code(c)
+ Tick _when, Tick _repeat, const std::string &_cause,
+ int c = 0)
+ : Event(q, Sim_Exit_Pri), cause(_cause),
+ code(c), repeat(_repeat)
{ setFlags(IsExitEvent); schedule(_when); }
+// SimLoopExitEvent(EventQueue *q,
+// Tick _when, const std::string &_cause,
+// Tick _repeat = 0, int c = 0)
+// : Event(q, Sim_Exit_Pri), cause(_cause), code(c), repeat(_repeat)
+// { setFlags(IsExitEvent); schedule(_when); }
+
std::string getCause() { return cause; }
int getCode() { return code; }
diff --git a/src/sim/sim_exit.hh b/src/sim/sim_exit.hh
index 545bf4ae0..d4b31d1ea 100644
--- a/src/sim/sim_exit.hh
+++ b/src/sim/sim_exit.hh
@@ -38,6 +38,8 @@
// forward declaration
class Callback;
+class EventQueue;
+class SimLoopExitEvent;
/// Register a callback to be called when Python exits. Defined in
/// sim/main.cc.
@@ -47,12 +49,14 @@ void registerExitCallback(Callback *);
/// Python) at the indicated tick. The message and exit_code
/// parameters are saved in the SimLoopExitEvent to indicate why the
/// exit occurred.
-void exitSimLoop(Tick when, const std::string &message, int exit_code = 0);
+SimLoopExitEvent *schedExitSimLoop(const std::string &message, Tick when,
+ Tick repeat = 0, EventQueue *q = NULL,
+ int exit_code = 0);
/// Schedule an event to exit the simulation loop (returning to
/// Python) at the end of the current cycle (curTick). The message
/// and exit_code parameters are saved in the SimLoopExitEvent to
/// indicate why the exit occurred.
-void exitSimLoop(const std::string &cause, int exit_code = 0);
+void exitSimLoop(const std::string &message, int exit_code = 0);
#endif // __SIM_EXIT_HH__
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-12 16:32:58 +0000