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-rw-r--r--src/base/traceflags.py1
-rw-r--r--src/cpu/base.cc4
-rw-r--r--src/cpu/o3/alpha/cpu_builder.cc15
-rw-r--r--src/cpu/o3/commit.hh2
-rw-r--r--src/cpu/o3/commit_impl.hh3
-rw-r--r--src/cpu/o3/cpu.cc10
-rw-r--r--src/cpu/o3/fetch_impl.hh13
-rw-r--r--src/cpu/o3/inst_queue.hh1
-rw-r--r--src/cpu/o3/inst_queue_impl.hh5
-rw-r--r--src/cpu/o3/rob.hh1
-rw-r--r--src/cpu/o3/rob_impl.hh1
-rw-r--r--src/python/m5/config.py2
12 files changed, 43 insertions, 15 deletions
diff --git a/src/base/traceflags.py b/src/base/traceflags.py
index d51236c46..327ce6075 100644
--- a/src/base/traceflags.py
+++ b/src/base/traceflags.py
@@ -121,6 +121,7 @@ baseFlags = [
'FE',
'IBE',
'BE',
+ 'O3CPU',
'OzoneLSQ',
'PCEvent',
'PCIA',
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 9df61d2ce..40cec416b 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -68,12 +68,12 @@ BaseCPU::BaseCPU(Params *p)
number_of_threads(p->numberOfThreads), system(p->system)
#endif
{
- DPRINTF(BaseCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
+ DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this);
// add self to global list of CPUs
cpuList.push_back(this);
- DPRINTF(BaseCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
+ DPRINTF(FullCPU, "BaseCPU: CPU added to cpuList, mem address %#x.\n",
this);
if (number_of_threads > maxThreadsPerCPU)
diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc
index 8190256fb..12d083a43 100644
--- a/src/cpu/o3/alpha/cpu_builder.cc
+++ b/src/cpu/o3/alpha/cpu_builder.cc
@@ -274,12 +274,12 @@ CREATE_SIM_OBJECT(DerivO3CPU)
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
- numThreads.isValid() ? numThreads : workload.size();
+ (numThreads.isValid() && numThreads >= workload.size()) ?
+ numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
}
-
#endif
AlphaSimpleParams *params = new AlphaSimpleParams;
@@ -371,7 +371,16 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->numROBEntries = numROBEntries;
params->smtNumFetchingThreads = smtNumFetchingThreads;
- params->smtFetchPolicy = smtFetchPolicy;
+
+ // Default smtFetchPolicy to "RoundRobin", if necessary.
+ std::string round_robin_policy = "RoundRobin";
+ std::string single_thread = "SingleThread";
+
+ if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
+ params->smtFetchPolicy = single_thread;
+ else
+ params->smtFetchPolicy = smtFetchPolicy;
+
params->smtIQPolicy = smtIQPolicy;
params->smtLSQPolicy = smtLSQPolicy;
params->smtLSQThreshold = smtLSQThreshold;
diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh
index 860326283..60b555269 100644
--- a/src/cpu/o3/commit.hh
+++ b/src/cpu/o3/commit.hh
@@ -406,8 +406,10 @@ class DefaultCommit
/** The next PC of each thread. */
Addr nextPC[Impl::MaxThreads];
+#if THE_ISA != ALPHA_ISA
/** The next NPC of each thread. */
Addr nextNPC[Impl::MaxThreads];
+#endif
/** The sequence number of the youngest valid instruction in the ROB. */
InstSeqNum youngestSeqNum[Impl::MaxThreads];
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index cd7dd47d4..06b8e8a95 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1221,7 +1221,8 @@ DefaultCommit<Impl>::roundRobin()
unsigned tid = *pri_iter;
if (commitStatus[tid] == Running ||
- commitStatus[tid] == Idle) {
+ commitStatus[tid] == Idle ||
+ commitStatus[tid] == FetchTrapPending) {
if (rob->isHeadReady(tid)) {
priority_list.erase(pri_iter);
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 7ed17a91e..feca4cdf2 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -127,7 +127,7 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
regFile(params->numPhysIntRegs, params->numPhysFloatRegs),
- freeList(params->numberOfThreads,//number of activeThreads
+ freeList(params->numberOfThreads,
TheISA::NumIntRegs, params->numPhysIntRegs,
TheISA::NumFloatRegs, params->numPhysFloatRegs),
@@ -135,7 +135,7 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
params->smtROBPolicy, params->smtROBThreshold,
params->numberOfThreads),
- scoreboard(params->numberOfThreads,//number of activeThreads
+ scoreboard(params->numberOfThreads,
TheISA::NumIntRegs, params->numPhysIntRegs,
TheISA::NumFloatRegs, params->numPhysFloatRegs,
TheISA::NumMiscRegs * number_of_threads,
@@ -221,6 +221,12 @@ FullO3CPU<Impl>::FullO3CPU(Params *params)
#if !FULL_SYSTEM
int active_threads = params->workload.size();
+
+ if (active_threads > Impl::MaxThreads) {
+ panic("Workload Size too large. Increase the 'MaxThreads'"
+ "constant in your O3CPU impl. file (e.g. o3/alpha/impl.hh) or "
+ "edit your workload size.");
+ }
#else
int active_threads = 1;
#endif
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index e570dbb18..60eb76d17 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -114,8 +114,6 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
if (numThreads > Impl::MaxThreads)
fatal("numThreads is not a valid value\n");
- DPRINTF(Fetch, "Fetch constructor called\n");
-
// Set fetch stage's status to inactive.
_status = Inactive;
@@ -128,6 +126,8 @@ DefaultFetch<Impl>::DefaultFetch(Params *params)
// Figure out fetch policy
if (policy == "singlethread") {
fetchPolicy = SingleThread;
+ if (numThreads > 1)
+ panic("Invalid Fetch Policy for a SMT workload.");
} else if (policy == "roundrobin") {
fetchPolicy = RoundRobin;
DPRINTF(Fetch, "Fetch policy set to Round Robin\n");
@@ -559,7 +559,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
return false;
}
- DPRINTF(Fetch, "Doing cache access.\n");
+ DPRINTF(Fetch, "[tid:%i]: Doing cache access.\n", tid);
lastIcacheStall[tid] = curTick;
@@ -724,12 +724,15 @@ DefaultFetch<Impl>::tick()
// Reset the number of the instruction we're fetching.
numInst = 0;
+#if FULL_SYSTEM
if (fromCommit->commitInfo[0].interruptPending) {
interruptPending = true;
}
+
if (fromCommit->commitInfo[0].clearInterrupt) {
interruptPending = false;
}
+#endif
for (threadFetched = 0; threadFetched < numFetchingThreads;
threadFetched++) {
@@ -903,6 +906,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
return;
}
+ DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
+
// The current PC.
Addr &fetch_PC = PC[tid];
@@ -1279,6 +1284,6 @@ int
DefaultFetch<Impl>::branchCount()
{
list<unsigned>::iterator threads = (*activeThreads).begin();
- warn("Branch Count Fetch policy unimplemented\n");
+ panic("Branch Count Fetch policy unimplemented\n");
return *threads;
}
diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index d745faf7b..4c69ca384 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#ifndef __CPU_O3_INST_QUEUE_HH__
diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 1ef1b2cff..b99bd0900 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#include <limits>
@@ -125,7 +126,7 @@ InstructionQueue<Impl>::InstructionQueue(Params *params)
maxEntries[i] = part_amt;
}
- DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
+ DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
"%i entries per thread.\n",part_amt);
} else if (policy == "threshold") {
@@ -140,7 +141,7 @@ InstructionQueue<Impl>::InstructionQueue(Params *params)
maxEntries[i] = thresholdIQ;
}
- DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
+ DPRINTF(IQ, "IQ sharing policy set to Threshold:"
"%i entries per thread.\n",thresholdIQ);
} else {
assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh
index b98d7c4c2..6f8080ef4 100644
--- a/src/cpu/o3/rob.hh
+++ b/src/cpu/o3/rob.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#ifndef __CPU_O3_ROB_HH__
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index 6277dd68b..d9978b17f 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -26,6 +26,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Kevin Lim
+ * Korey Sewell
*/
#include "config/full_system.hh"
diff --git a/src/python/m5/config.py b/src/python/m5/config.py
index adabe0743..6f2873d40 100644
--- a/src/python/m5/config.py
+++ b/src/python/m5/config.py
@@ -274,7 +274,7 @@ class MetaSimObject(type):
cls._values[attr] = value
else:
raise AttributeError, \
- "Class %s has no parameter %s" % (cls.__name__, attr)
+ "Class %s has no parameter \'%s\'" % (cls.__name__, attr)
def __getattr__(cls, attr):
if cls._values.has_key(attr):
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 20:42:23 +0000