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-rw-r--r--src/arch/arm/isa.hh18
-rw-r--r--src/arch/arm/miscregs.hh19
2 files changed, 33 insertions, 4 deletions
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index a7bb1cc3e..8d547f9c6 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -110,7 +110,11 @@ namespace ArmISA
* Technically this should be 0, but we don't support those
* settings.
*/
- miscRegs[MISCREG_CPACR] = 0x0fffffff;
+ CPACR cpacr = 0;
+ // Enable CP 10, 11
+ cpacr.cp10 = 0x3;
+ cpacr.cp11 = 0x3;
+ miscRegs[MISCREG_CPACR] = cpacr;
/* One region, unified map. */
miscRegs[MISCREG_MPUIR] = 0x100;
@@ -249,9 +253,15 @@ namespace ArmISA
}
switch (misc_reg) {
case MISCREG_CPACR:
- newVal = bits(val, 27, 0);
- if (newVal != 0x0fffffff) {
- panic("Disabling coprocessors isn't implemented.\n");
+ {
+ CPACR newCpacr = 0;
+ CPACR valCpacr = val;
+ newCpacr.cp10 = valCpacr.cp10;
+ newCpacr.cp11 = valCpacr.cp11;
+ if (newCpacr.cp10 != 0x3 || newCpacr.cp11 != 3) {
+ panic("Disabling coprocessors isn't implemented.\n");
+ }
+ newVal = newCpacr;
}
break;
case MISCREG_CSSELR:
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 704450d1c..74be52c66 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -230,6 +230,25 @@ namespace ArmISA
Bitfield<1> a; // Alignment fault checking
Bitfield<0> m; // MMU enable bit
EndBitUnion(SCTLR)
+
+ BitUnion32(CPACR)
+ Bitfield<1, 0> cp0;
+ Bitfield<3, 2> cp1;
+ Bitfield<5, 4> cp2;
+ Bitfield<7, 6> cp3;
+ Bitfield<9, 8> cp4;
+ Bitfield<11, 10> cp5;
+ Bitfield<13, 12> cp6;
+ Bitfield<15, 14> cp7;
+ Bitfield<17, 16> cp8;
+ Bitfield<19, 18> cp9;
+ Bitfield<21, 20> cp10;
+ Bitfield<23, 22> cp11;
+ Bitfield<25, 24> cp12;
+ Bitfield<27, 26> cp13;
+ Bitfield<30> d32dis;
+ Bitfield<31> asedis;
+ EndBitUnion(CPACR)
};
#endif // __ARCH_ARM_MISCREGS_HH__