diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/sparc/isa/operands.isa | 3 | ||||
| -rw-r--r-- | src/arch/sparc/isa_traits.hh | 2 | ||||
| -rw-r--r-- | src/arch/sparc/sparc_traits.hh | 2 | ||||
| -rw-r--r-- | src/cpu/o3/free_list.hh | 2 | ||||
| -rw-r--r-- | src/cpu/o3/regfile.hh | 4 | ||||
| -rw-r--r-- | src/cpu/o3/rename_map.cc | 4 | ||||
| -rw-r--r-- | src/cpu/o3/scoreboard.cc | 15 |
7 files changed, 29 insertions, 3 deletions
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa index 110b37d15..a627a2e6f 100644 --- a/src/arch/sparc/isa/operands.isa +++ b/src/arch/sparc/isa/operands.isa @@ -149,7 +149,8 @@ def operands {{ 'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43), 'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44), 'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45), - 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', None, 46), +# 'Gsr': ('ControlReg', 'udw', 'MISCREG_GSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 46), + 'Gsr': ('IntReg', 'udw', 'NumIntArchRegs + 8', None, 46), 'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47), 'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48), 'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49), diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index d0b8827f3..8b3ec36a6 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -58,7 +58,7 @@ namespace SparcISA // These enumerate all the registers for dependence tracking. enum DependenceTags { - FP_Base_DepTag = 32*3+8, + FP_Base_DepTag = 32*3+9, Ctrl_Base_DepTag = FP_Base_DepTag + 64 }; diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh index d89ec1119..715c08c03 100644 --- a/src/arch/sparc/sparc_traits.hh +++ b/src/arch/sparc/sparc_traits.hh @@ -42,7 +42,7 @@ namespace SparcISA // Number of register windows, can legally be 3 to 32 const int NWindows = 8; //const int NumMicroIntRegs = 1; - const int NumMicroIntRegs = 8; + const int NumMicroIntRegs = 9; // const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16; // const int NumMicroIntRegs = 1; diff --git a/src/cpu/o3/free_list.hh b/src/cpu/o3/free_list.hh index c669b0b34..42fc0c533 100644 --- a/src/cpu/o3/free_list.hh +++ b/src/cpu/o3/free_list.hh @@ -168,7 +168,9 @@ SimpleFreeList::addReg(PhysRegIndex freed_reg) if (freed_reg != TheISA::ZeroReg) freeIntRegs.push(freed_reg); } else if (freed_reg < numPhysicalRegs) { +#if THE_ISA == ALPHA_ISA if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs)) +#endif freeFloatRegs.push(freed_reg); } } diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index b5b1cd021..75d3fa6eb 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -179,7 +179,9 @@ class PhysRegFile DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", int(reg_idx), (uint64_t)val); +#if THE_ISA == ALPHA_ISA if (reg_idx != TheISA::ZeroReg) +#endif floatRegFile[reg_idx].d = val; } @@ -194,7 +196,9 @@ class PhysRegFile DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", int(reg_idx), (uint64_t)val); +#if THE_ISA == ALPHA_ISA if (reg_idx != TheISA::ZeroReg) +#endif floatRegFile[reg_idx].d = val; } diff --git a/src/cpu/o3/rename_map.cc b/src/cpu/o3/rename_map.cc index b436ec1c3..e6649ce3e 100644 --- a/src/cpu/o3/rename_map.cc +++ b/src/cpu/o3/rename_map.cc @@ -165,17 +165,21 @@ SimpleRenameMap::rename(RegIndex arch_reg) // If it's not referencing the zero register, then rename the // register. +#if THE_ISA == ALPHA_ISA if (arch_reg != floatZeroReg) { +#endif renamed_reg = freeList->getFloatReg(); floatRenameMap[arch_reg].physical_reg = renamed_reg; assert(renamed_reg < numPhysicalRegs && renamed_reg >= numPhysicalIntRegs); +#if THE_ISA == ALPHA_ISA } else { // Otherwise return the zero register so nothing bad happens. renamed_reg = floatZeroReg; } +#endif } else { // Subtract off the base offset for miscellaneous registers. arch_reg = arch_reg - numLogicalRegs; diff --git a/src/cpu/o3/scoreboard.cc b/src/cpu/o3/scoreboard.cc index 1859b35a4..e7f8b7949 100644 --- a/src/cpu/o3/scoreboard.cc +++ b/src/cpu/o3/scoreboard.cc @@ -29,6 +29,7 @@ * Kevin Lim */ +#include "arch/isa_specific.hh" #include "cpu/o3/scoreboard.hh" Scoreboard::Scoreboard(unsigned activeThreads, @@ -79,11 +80,18 @@ Scoreboard::name() const bool Scoreboard::getReg(PhysRegIndex phys_reg) { +#if THE_ISA == ALPHA_ISA // Always ready if int or fp zero reg. if (phys_reg == zeroRegIdx || phys_reg == (zeroRegIdx + numPhysicalIntRegs)) { return 1; } +#else + // Always ready if int zero reg. + if (phys_reg == zeroRegIdx) { + return 1; + } +#endif return regScoreBoard[phys_reg]; } @@ -99,11 +107,18 @@ Scoreboard::setReg(PhysRegIndex phys_reg) void Scoreboard::unsetReg(PhysRegIndex ready_reg) { +#if THE_ISA == ALPHA_ISA if (ready_reg == zeroRegIdx || ready_reg == (zeroRegIdx + numPhysicalIntRegs)) { // Don't do anything if int or fp zero reg. return; } +#else + if (ready_reg == zeroRegIdx) { + // Don't do anything if int zero reg. + return; + } +#endif regScoreBoard[ready_reg] = 0; } |