diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/sparc/faults.cc | 110 |
1 files changed, 55 insertions, 55 deletions
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc index c5263cf58..6375fa5fe 100644 --- a/src/arch/sparc/faults.cc +++ b/src/arch/sparc/faults.cc @@ -52,226 +52,226 @@ namespace SparcISA template<> SparcFaultBase::FaultVals SparcFault<PowerOnReset>::vals -("power_on_reset", 0x001, 0, {H, H, H}); +("power_on_reset", 0x001, 0, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<WatchDogReset>::vals -("watch_dog_reset", 0x002, 120, {H, H, H}); +("watch_dog_reset", 0x002, 120, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<ExternallyInitiatedReset>::vals -("externally_initiated_reset", 0x003, 110, {H, H, H}); +("externally_initiated_reset", 0x003, 110, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<SoftwareInitiatedReset>::vals -("software_initiated_reset", 0x004, 130, {SH, SH, H}); +("software_initiated_reset", 0x004, 130, {{SH, SH, H}}); template<> SparcFaultBase::FaultVals SparcFault<REDStateException>::vals -("RED_state_exception", 0x005, 1, {H, H, H}); +("RED_state_exception", 0x005, 1, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<StoreError>::vals -("store_error", 0x007, 201, {H, H, H}); +("store_error", 0x007, 201, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<InstructionAccessException>::vals -("instruction_access_exception", 0x008, 300, {H, H, H}); +("instruction_access_exception", 0x008, 300, {{H, H, H}}); //XXX This trap is apparently dropped from ua2005 /*template<> SparcFaultBase::FaultVals SparcFault<InstructionAccessMMUMiss>::vals - {"inst_mmu", 0x009, 2, {H, H, H}};*/ + ("inst_mmu", 0x009, 2, {{H, H, H}});*/ template<> SparcFaultBase::FaultVals SparcFault<InstructionAccessError>::vals -("instruction_access_error", 0x00A, 400, {H, H, H}); +("instruction_access_error", 0x00A, 400, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<IllegalInstruction>::vals -("illegal_instruction", 0x010, 620, {H, H, H}); +("illegal_instruction", 0x010, 620, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<PrivilegedOpcode>::vals -("privileged_opcode", 0x011, 700, {P, SH, SH}); +("privileged_opcode", 0x011, 700, {{P, SH, SH}}); //XXX This trap is apparently dropped from ua2005 /*template<> SparcFaultBase::FaultVals SparcFault<UnimplementedLDD>::vals - {"unimp_ldd", 0x012, 6, {H, H, H}};*/ + ("unimp_ldd", 0x012, 6, {{H, H, H}});*/ //XXX This trap is apparently dropped from ua2005 /*template<> SparcFaultBase::FaultVals SparcFault<UnimplementedSTD>::vals - {"unimp_std", 0x013, 6, {H, H, H}};*/ + ("unimp_std", 0x013, 6, {{H, H, H}});*/ template<> SparcFaultBase::FaultVals SparcFault<FpDisabled>::vals -("fp_disabled", 0x020, 800, {P, P, H}); +("fp_disabled", 0x020, 800, {{P, P, H}}); /* SPARCv8 and SPARCv9 define just fp_disabled trap. SIMD is not contemplated * as a separate part. Therefore, we use the same code and TT */ template<> SparcFaultBase::FaultVals - SparcFault<VecDisabled>::vals = -{"fp_disabled", 0x020, 800, {P, P, H}}; + SparcFault<VecDisabled>::vals +("fp_disabled", 0x020, 800, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<FpExceptionIEEE754>::vals -("fp_exception_ieee_754", 0x021, 1110, {P, P, H}); +("fp_exception_ieee_754", 0x021, 1110, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<FpExceptionOther>::vals -("fp_exception_other", 0x022, 1110, {P, P, H}); +("fp_exception_other", 0x022, 1110, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<TagOverflow>::vals -("tag_overflow", 0x023, 1400, {P, P, H}); +("tag_overflow", 0x023, 1400, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<CleanWindow>::vals -("clean_window", 0x024, 1010, {P, P, H}); +("clean_window", 0x024, 1010, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<DivisionByZero>::vals -("division_by_zero", 0x028, 1500, {P, P, H}); +("division_by_zero", 0x028, 1500, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<InternalProcessorError>::vals -("internal_processor_error", 0x029, 4, {H, H, H}); +("internal_processor_error", 0x029, 4, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<InstructionInvalidTSBEntry>::vals -("instruction_invalid_tsb_entry", 0x02A, 210, {H, H, SH}); +("instruction_invalid_tsb_entry", 0x02A, 210, {{H, H, SH}}); template<> SparcFaultBase::FaultVals SparcFault<DataInvalidTSBEntry>::vals -("data_invalid_tsb_entry", 0x02B, 1203, {H, H, H}); +("data_invalid_tsb_entry", 0x02B, 1203, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<DataAccessException>::vals -("data_access_exception", 0x030, 1201, {H, H, H}); +("data_access_exception", 0x030, 1201, {{H, H, H}}); //XXX This trap is apparently dropped from ua2005 /*template<> SparcFaultBase::FaultVals SparcFault<DataAccessMMUMiss>::vals - {"data_mmu", 0x031, 12, {H, H, H}};*/ + ("data_mmu", 0x031, 12, {{H, H, H}});*/ template<> SparcFaultBase::FaultVals SparcFault<DataAccessError>::vals -("data_access_error", 0x032, 1210, {H, H, H}); +("data_access_error", 0x032, 1210, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<DataAccessProtection>::vals -("data_access_protection", 0x033, 1207, {H, H, H}); +("data_access_protection", 0x033, 1207, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<MemAddressNotAligned>::vals -("mem_address_not_aligned", 0x034, 1020, {H, H, H}); +("mem_address_not_aligned", 0x034, 1020, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<LDDFMemAddressNotAligned>::vals -("LDDF_mem_address_not_aligned", 0x035, 1010, {H, H, H}); +("LDDF_mem_address_not_aligned", 0x035, 1010, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<STDFMemAddressNotAligned>::vals -("STDF_mem_address_not_aligned", 0x036, 1010, {H, H, H}); +("STDF_mem_address_not_aligned", 0x036, 1010, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<PrivilegedAction>::vals -("privileged_action", 0x037, 1110, {H, H, SH}); +("privileged_action", 0x037, 1110, {{H, H, SH}}); template<> SparcFaultBase::FaultVals SparcFault<LDQFMemAddressNotAligned>::vals -("LDQF_mem_address_not_aligned", 0x038, 1010, {H, H, H}); +("LDQF_mem_address_not_aligned", 0x038, 1010, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<STQFMemAddressNotAligned>::vals -("STQF_mem_address_not_aligned", 0x039, 1010, {H, H, H}); +("STQF_mem_address_not_aligned", 0x039, 1010, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<InstructionRealTranslationMiss>::vals -("instruction_real_translation_miss", 0x03E, 208, {H, H, SH}); +("instruction_real_translation_miss", 0x03E, 208, {{H, H, SH}}); template<> SparcFaultBase::FaultVals SparcFault<DataRealTranslationMiss>::vals -("data_real_translation_miss", 0x03F, 1203, {H, H, H}); +("data_real_translation_miss", 0x03F, 1203, {{H, H, H}}); //XXX This trap is apparently dropped from ua2005 /*template<> SparcFaultBase::FaultVals SparcFault<AsyncDataError>::vals - {"async_data", 0x040, 2, {H, H, H}};*/ + ("async_data", 0x040, 2, {{H, H, H}});*/ template<> SparcFaultBase::FaultVals SparcFault<InterruptLevelN>::vals -("interrupt_level_n", 0x040, 0, {P, P, SH}); +("interrupt_level_n", 0x040, 0, {{P, P, SH}}); template<> SparcFaultBase::FaultVals SparcFault<HstickMatch>::vals -("hstick_match", 0x05E, 1601, {H, H, H}); +("hstick_match", 0x05E, 1601, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<TrapLevelZero>::vals -("trap_level_zero", 0x05F, 202, {H, H, SH}); +("trap_level_zero", 0x05F, 202, {{H, H, SH}}); template<> SparcFaultBase::FaultVals SparcFault<InterruptVector>::vals -("interrupt_vector", 0x060, 2630, {H, H, H}); +("interrupt_vector", 0x060, 2630, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<PAWatchpoint>::vals -("PA_watchpoint", 0x061, 1209, {H, H, H}); +("PA_watchpoint", 0x061, 1209, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<VAWatchpoint>::vals -("VA_watchpoint", 0x062, 1120, {P, P, SH}); +("VA_watchpoint", 0x062, 1120, {{P, P, SH}}); template<> SparcFaultBase::FaultVals SparcFault<FastInstructionAccessMMUMiss>::vals -("fast_instruction_access_MMU_miss", 0x064, 208, {H, H, SH}); +("fast_instruction_access_MMU_miss", 0x064, 208, {{H, H, SH}}); template<> SparcFaultBase::FaultVals SparcFault<FastDataAccessMMUMiss>::vals -("fast_data_access_MMU_miss", 0x068, 1203, {H, H, H}); +("fast_data_access_MMU_miss", 0x068, 1203, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<FastDataAccessProtection>::vals -("fast_data_access_protection", 0x06C, 1207, {H, H, H}); +("fast_data_access_protection", 0x06C, 1207, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<InstructionBreakpoint>::vals -("instruction_break", 0x076, 610, {H, H, H}); +("instruction_break", 0x076, 610, {{H, H, H}}); template<> SparcFaultBase::FaultVals SparcFault<CpuMondo>::vals -("cpu_mondo", 0x07C, 1608, {P, P, SH}); +("cpu_mondo", 0x07C, 1608, {{P, P, SH}}); template<> SparcFaultBase::FaultVals SparcFault<DevMondo>::vals -("dev_mondo", 0x07D, 1611, {P, P, SH}); +("dev_mondo", 0x07D, 1611, {{P, P, SH}}); template<> SparcFaultBase::FaultVals SparcFault<ResumableError>::vals -("resume_error", 0x07E, 3330, {P, P, SH}); +("resume_error", 0x07E, 3330, {{P, P, SH}}); template<> SparcFaultBase::FaultVals SparcFault<SpillNNormal>::vals -("spill_n_normal", 0x080, 900, {P, P, H}); +("spill_n_normal", 0x080, 900, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<SpillNOther>::vals -("spill_n_other", 0x0A0, 900, {P, P, H}); +("spill_n_other", 0x0A0, 900, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<FillNNormal>::vals -("fill_n_normal", 0x0C0, 900, {P, P, H}); +("fill_n_normal", 0x0C0, 900, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<FillNOther>::vals -("fill_n_other", 0x0E0, 900, {P, P, H}); +("fill_n_other", 0x0E0, 900, {{P, P, H}}); template<> SparcFaultBase::FaultVals SparcFault<TrapInstruction>::vals -("trap_instruction", 0x100, 1602, {P, P, H}); +("trap_instruction", 0x100, 1602, {{P, P, H}}); /** * This causes the thread context to enter RED state. This causes the side |