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-rw-r--r--src/arch/arm/ArmTLB.py3
-rw-r--r--src/arch/power/PowerTLB.py4
2 files changed, 5 insertions, 2 deletions
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index b3f711d83..4cac944f1 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -41,6 +41,7 @@ from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from MemObject import MemObject
+from BaseTLB import BaseTLB
# Basic stage 1 translation objects
class ArmTableWalker(MemObject):
@@ -59,7 +60,7 @@ class ArmTableWalker(MemObject):
sys = Param.System(Parent.any, "system object parameter")
-class ArmTLB(SimObject):
+class ArmTLB(BaseTLB):
type = 'ArmTLB'
cxx_class = 'ArmISA::TLB'
cxx_header = "arch/arm/tlb.hh"
diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py
index ae6503a1f..b12c5a8e3 100644
--- a/src/arch/power/PowerTLB.py
+++ b/src/arch/power/PowerTLB.py
@@ -31,7 +31,9 @@
from m5.SimObject import SimObject
from m5.params import *
-class PowerTLB(SimObject):
+from BaseTLB import BaseTLB
+
+class PowerTLB(BaseTLB):
type = 'PowerTLB'
cxx_class = 'PowerISA::TLB'
cxx_header = 'arch/power/tlb.hh'