summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/SConscript2
-rw-r--r--src/arch/SConscript11
-rw-r--r--src/cpu/SConscript7
-rw-r--r--src/cpu/checker/cpu.hh2
-rw-r--r--src/cpu/o3/commit_impl.hh12
-rw-r--r--src/cpu/o3/cpu.cc15
-rw-r--r--src/cpu/o3/iew.hh9
-rw-r--r--src/cpu/o3/lsq_unit.hh1
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh1
-rw-r--r--src/cpu/simple/atomic.cc14
-rw-r--r--src/cpu/simple/atomic.hh2
-rw-r--r--src/cpu/simple/base.cc8
-rw-r--r--src/cpu/simple/timing.cc53
-rw-r--r--src/cpu/simple/timing.hh48
-rw-r--r--src/cpu/simple_thread.cc1
-rw-r--r--src/python/m5/config.py3
-rw-r--r--src/python/m5/main.py2
-rw-r--r--src/python/m5/objects/DiskImage.py4
-rw-r--r--src/python/m5/objects/Ethernet.py45
-rw-r--r--src/python/m5/objects/Ide.py27
-rw-r--r--src/python/m5/objects/Root.py2
-rw-r--r--src/python/m5/objects/Tsunami.py77
-rw-r--r--src/sim/main.cc2
23 files changed, 295 insertions, 53 deletions
diff --git a/src/SConscript b/src/SConscript
index 5e61b285b..812089a00 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -299,7 +299,7 @@ alpha_eio_sources = Split('''
encumbered/eio/eio.cc
''')
-if env['TARGET_ISA'] == 'ALPHA_ISA':
+if env['TARGET_ISA'] == 'alpha':
syscall_emulation_sources += alpha_eio_sources
memtest_sources = Split('''
diff --git a/src/arch/SConscript b/src/arch/SConscript
index bc517341a..0a5962889 100644
--- a/src/arch/SConscript
+++ b/src/arch/SConscript
@@ -140,8 +140,15 @@ def isa_desc_emitter(target, source, env):
# Pieces are in place, so create the builder.
python = sys.executable # use same Python binary used to run scons
-isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
- emitter = isa_desc_emitter)
+
+# Also include the CheckerCPU as one of the models if it is being
+# enabled via command line.
+if env['USE_CHECKER']:
+ isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS CheckerCPU',
+ emitter = isa_desc_emitter)
+else:
+ isa_desc_builder = Builder(action=python + ' $SOURCES $TARGET.dir $CPU_MODELS',
+ emitter = isa_desc_emitter)
env.Append(BUILDERS = { 'ISADesc' : isa_desc_builder })
diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index bc4ec7923..7d45c7870 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -71,7 +71,8 @@ virtual Fault completeAcc(uint8_t *data, %s *xc, Trace::InstRecord *traceData) c
# Generate a temporary CPU list, including the CheckerCPU if
# it's enabled. This isn't used for anything else other than StaticInst
# headers.
-temp_cpu_list = env['CPU_MODELS']
+temp_cpu_list = env['CPU_MODELS'][:]
+
if env['USE_CHECKER']:
temp_cpu_list.append('CheckerCPU')
@@ -113,6 +114,9 @@ CheckerSupportedCPUList = ['O3CPU', 'OzoneCPU']
#
#################################################################
+# Keep a list of CPU models that support SMT
+env['SMT_CPU_MODELS'] = []
+
sources = []
need_simple_base = False
@@ -156,6 +160,7 @@ if 'O3CPU' in env['CPU_MODELS']:
''')
if env['USE_CHECKER']:
sources += Split('o3/checker_builder.cc')
+ env['SMT_CPU_MODELS'].append('O3CPU')
if 'OzoneCPU' in env['CPU_MODELS']:
need_bp_unit = True
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index a508c56ba..6d6ae1e0a 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -170,7 +170,7 @@ class CheckerCPU : public BaseCPU
virtual Counter totalInstructions() const
{
- return numInst - startNumInst;
+ return 0;
}
// number of simulated loads
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index 904af1071..c667d633a 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -996,6 +996,12 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// Check if the instruction caused a fault. If so, trap.
Fault inst_fault = head_inst->getFault();
+ // DTB will sometimes need the machine instruction for when
+ // faults happen. So we will set it here, prior to the DTB
+ // possibly needing it for its fault.
+ thread[tid]->setInst(
+ static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
+
if (inst_fault != NoFault) {
head_inst->setCompleted();
DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
@@ -1018,12 +1024,6 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
// execution doesn't generate extra squashes.
thread[tid]->inSyscall = true;
- // DTB will sometimes need the machine instruction for when
- // faults happen. So we will set it here, prior to the DTB
- // possibly needing it for its fault.
- thread[tid]->setInst(
- static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
-
// Execute the trap. Although it's slightly unrealistic in
// terms of timing (as it doesn't wait for the full timing of
// the trap event to complete before updating state), it's
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index b407f4fcc..c43cc2cf8 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -745,7 +745,8 @@ template <class Impl>
void
FullO3CPU<Impl>::serialize(std::ostream &os)
{
- SERIALIZE_ENUM(_status);
+ SimObject::State so_state = SimObject::getState();
+ SERIALIZE_ENUM(so_state);
BaseCPU::serialize(os);
nameOut(os, csprintf("%s.tickEvent", name()));
tickEvent.serialize(os);
@@ -766,7 +767,8 @@ template <class Impl>
void
FullO3CPU<Impl>::unserialize(Checkpoint *cp, const std::string &section)
{
- UNSERIALIZE_ENUM(_status);
+ SimObject::State so_state;
+ UNSERIALIZE_ENUM(so_state);
BaseCPU::unserialize(cp, section);
tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
@@ -1045,7 +1047,8 @@ template <class Impl>
void
FullO3CPU<Impl>::setArchFloatRegSingle(int reg_idx, float val, unsigned tid)
{
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
regFile.setFloatReg(phys_reg, val);
}
@@ -1054,7 +1057,8 @@ template <class Impl>
void
FullO3CPU<Impl>::setArchFloatRegDouble(int reg_idx, double val, unsigned tid)
{
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
regFile.setFloatReg(phys_reg, val, 64);
}
@@ -1063,7 +1067,8 @@ template <class Impl>
void
FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid)
{
- PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx);
+ int idx = reg_idx + TheISA::FP_Base_DepTag;
+ PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx);
regFile.setFloatRegBits(phys_reg, val);
}
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index fb9afde54..6c6be4787 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -31,11 +31,12 @@
#ifndef __CPU_O3_IEW_HH__
#define __CPU_O3_IEW_HH__
+#include "config/full_system.hh"
+
#include <queue>
#include "base/statistics.hh"
#include "base/timebuf.hh"
-#include "config/full_system.hh"
#include "cpu/o3/comm.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/lsq.hh"
@@ -215,7 +216,7 @@ class DefaultIEW
if (++wbOutstanding == wbMax)
ableToIssue = false;
DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
-#if DEBUG
+#ifdef DEBUG
wbList.insert(sn);
#endif
}
@@ -225,13 +226,13 @@ class DefaultIEW
if (wbOutstanding-- == wbMax)
ableToIssue = true;
DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding);
-#if DEBUG
+#ifdef DEBUG
assert(wbList.find(sn) != wbList.end());
wbList.erase(sn);
#endif
}
-#if DEBUG
+#ifdef DEBUG
std::set<InstSeqNum> wbList;
void dumpWb()
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index a76a73f0c..512b5a63c 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -601,6 +601,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
// Tell IQ/mem dep unit that this instruction will need to be
// rescheduled eventually
iewStage->rescheduleMemInst(load_inst);
+ iewStage->decrWb(load_inst->seqNum);
++lsqRescheduledLoads;
// Do not generate a writeback event as this instruction is not
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 85b150cd9..4f5dbbf1c 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -790,6 +790,7 @@ LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
// Squashed instructions do not need to complete their access.
if (inst->isSquashed()) {
+ iewStage->decrWb(inst->seqNum);
assert(!inst->isStore());
++lsqIgnoredResponses;
return;
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 1752b2b5b..c396f5033 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -159,18 +159,20 @@ AtomicSimpleCPU::~AtomicSimpleCPU()
void
AtomicSimpleCPU::serialize(ostream &os)
{
- SERIALIZE_ENUM(_status);
- BaseSimpleCPU::serialize(os);
+ SimObject::State so_state = SimObject::getState();
+ SERIALIZE_ENUM(so_state);
nameOut(os, csprintf("%s.tickEvent", name()));
tickEvent.serialize(os);
+ BaseSimpleCPU::serialize(os);
}
void
AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
{
- UNSERIALIZE_ENUM(_status);
- BaseSimpleCPU::unserialize(cp, section);
+ SimObject::State so_state;
+ UNSERIALIZE_ENUM(so_state);
tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
+ BaseSimpleCPU::unserialize(cp, section);
}
void
@@ -178,6 +180,10 @@ AtomicSimpleCPU::resume()
{
assert(system->getMemoryMode() == System::Atomic);
changeState(SimObject::Running);
+ if (thread->status() == ThreadContext::Active) {
+ if (!tickEvent.scheduled())
+ tickEvent.schedule(curTick);
+ }
}
void
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index d59ca01aa..b602af558 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -126,8 +126,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
-
virtual void resume();
+
void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index af10e64d7..240696c2b 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -178,8 +178,8 @@ void
BaseSimpleCPU::serialize(ostream &os)
{
BaseCPU::serialize(os);
- SERIALIZE_SCALAR(inst);
- nameOut(os, csprintf("%s.xc", name()));
+// SERIALIZE_SCALAR(inst);
+ nameOut(os, csprintf("%s.xc.0", name()));
thread->serialize(os);
}
@@ -187,8 +187,8 @@ void
BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
{
BaseCPU::unserialize(cp, section);
- UNSERIALIZE_SCALAR(inst);
- thread->unserialize(cp, csprintf("%s.xc", section));
+// UNSERIALIZE_SCALAR(inst);
+ thread->unserialize(cp, csprintf("%s.xc.0", section));
}
void
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index d2c2c7c47..5c1654f7e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -85,8 +85,16 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
}
+
+void
+TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
+{
+ pkt = _pkt;
+ Event::schedule(t);
+}
+
TimingSimpleCPU::TimingSimpleCPU(Params *p)
- : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
+ : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
{
_status = Idle;
ifetch_pkt = dcache_pkt = NULL;
@@ -103,14 +111,16 @@ TimingSimpleCPU::~TimingSimpleCPU()
void
TimingSimpleCPU::serialize(ostream &os)
{
- SERIALIZE_ENUM(_status);
+ SimObject::State so_state = SimObject::getState();
+ SERIALIZE_ENUM(so_state);
BaseSimpleCPU::serialize(os);
}
void
TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
{
- UNSERIALIZE_ENUM(_status);
+ SimObject::State so_state;
+ UNSERIALIZE_ENUM(so_state);
BaseSimpleCPU::unserialize(cp, section);
}
@@ -135,7 +145,9 @@ TimingSimpleCPU::resume()
if (_status != SwitchedOut && _status != Idle) {
// Delete the old event if it existed.
if (fetchEvent) {
- assert(!fetchEvent->scheduled());
+ if (fetchEvent->scheduled())
+ fetchEvent->deschedule();
+
delete fetchEvent;
}
@@ -458,11 +470,26 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
}
}
+void
+TimingSimpleCPU::IcachePort::ITickEvent::process()
+{
+ cpu->completeIfetch(pkt);
+}
bool
TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
{
- cpu->completeIfetch(pkt);
+ // These next few lines could be replaced with something faster
+ // who knows what though
+ Tick time = pkt->req->getTime();
+ while (time < curTick)
+ time += lat;
+
+ if (time == curTick)
+ cpu->completeIfetch(pkt);
+ else
+ tickEvent.schedule(pkt, time);
+
return true;
}
@@ -519,11 +546,25 @@ TimingSimpleCPU::completeDrain()
bool
TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
{
- cpu->completeDataAccess(pkt);
+ Tick time = pkt->req->getTime();
+ while (time < curTick)
+ time += lat;
+
+ if (time == curTick)
+ cpu->completeDataAccess(pkt);
+ else
+ tickEvent.schedule(pkt, time);
+
return true;
}
void
+TimingSimpleCPU::DcachePort::DTickEvent::process()
+{
+ cpu->completeDataAccess(pkt);
+}
+
+void
TimingSimpleCPU::DcachePort::recvRetry()
{
// we shouldn't get a retry unless we have a packet that we're
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index ac36e5c99..d03fa4bc0 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -74,11 +74,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
{
protected:
TimingSimpleCPU *cpu;
+ Tick lat;
public:
- CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
- : Port(_name), cpu(_cpu)
+ CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
+ : Port(_name), cpu(_cpu), lat(_lat)
{ }
protected:
@@ -92,14 +93,26 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); }
+
+ struct TickEvent : public Event
+ {
+ Packet *pkt;
+ TimingSimpleCPU *cpu;
+
+ TickEvent(TimingSimpleCPU *_cpu)
+ :Event(&mainEventQueue), cpu(_cpu) {}
+ const char *description() { return "Timing CPU clock event"; }
+ void schedule(Packet *_pkt, Tick t);
+ };
+
};
class IcachePort : public CpuPort
{
public:
- IcachePort(TimingSimpleCPU *_cpu)
- : CpuPort(_cpu->name() + "-iport", _cpu)
+ IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
+ : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
{ }
protected:
@@ -107,14 +120,26 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual bool recvTiming(Packet *pkt);
virtual void recvRetry();
+
+ struct ITickEvent : public TickEvent
+ {
+
+ ITickEvent(TimingSimpleCPU *_cpu)
+ : TickEvent(_cpu) {}
+ void process();
+ const char *description() { return "Timing CPU clock event"; }
+ };
+
+ ITickEvent tickEvent;
+
};
class DcachePort : public CpuPort
{
public:
- DcachePort(TimingSimpleCPU *_cpu)
- : CpuPort(_cpu->name() + "-dport", _cpu)
+ DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
+ : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
{ }
protected:
@@ -122,6 +147,17 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual bool recvTiming(Packet *pkt);
virtual void recvRetry();
+
+ struct DTickEvent : public TickEvent
+ {
+ DTickEvent(TimingSimpleCPU *_cpu)
+ : TickEvent(_cpu) {}
+ void process();
+ const char *description() { return "Timing CPU clock event"; }
+ };
+
+ DTickEvent tickEvent;
+
};
IcachePort icachePort;
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index af1db2ff2..5f86cf2b7 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -196,6 +196,7 @@ SimpleThread::copyState(ThreadContext *oldContext)
#if !FULL_SYSTEM
funcExeInst = oldContext->readFuncExeInst();
#endif
+ inst = oldContext->getInst();
}
void
diff --git a/src/python/m5/config.py b/src/python/m5/config.py
index 8eed28dcc..df4b74cbd 100644
--- a/src/python/m5/config.py
+++ b/src/python/m5/config.py
@@ -665,7 +665,8 @@ class BaseProxy(object):
result, done = self.find(obj)
if not done:
- raise AttributeError, "Can't resolve proxy '%s' from '%s'" % \
+ raise AttributeError, \
+ "Can't resolve proxy '%s' from '%s'" % \
(self.path(), base.path())
if isinstance(result, BaseProxy):
diff --git a/src/python/m5/main.py b/src/python/m5/main.py
index afe73d94c..a757aaf1a 100644
--- a/src/python/m5/main.py
+++ b/src/python/m5/main.py
@@ -249,6 +249,8 @@ def main():
# check to make sure we can find the listed script
if not arguments or not os.path.isfile(arguments[0]):
+ if arguments and not os.path.isfile(arguments[0]):
+ print "Script %s not found" % arguments[0]
usage(2)
# tell C++ about output directory
diff --git a/src/python/m5/objects/DiskImage.py b/src/python/m5/objects/DiskImage.py
index 70d8b2e45..a98b35a4f 100644
--- a/src/python/m5/objects/DiskImage.py
+++ b/src/python/m5/objects/DiskImage.py
@@ -10,6 +10,6 @@ class RawDiskImage(DiskImage):
class CowDiskImage(DiskImage):
type = 'CowDiskImage'
- child = Param.DiskImage("child image")
+ child = Param.DiskImage(RawDiskImage(read_only=True),
+ "child image")
table_size = Param.Int(65536, "initial table size")
- image_file = ''
diff --git a/src/python/m5/objects/Ethernet.py b/src/python/m5/objects/Ethernet.py
index 418670592..db7efe004 100644
--- a/src/python/m5/objects/Ethernet.py
+++ b/src/python/m5/objects/Ethernet.py
@@ -1,7 +1,7 @@
from m5 import build_env
from m5.config import *
from Device import DmaDevice
-from Pci import PciDevice
+from Pci import PciDevice, PciConfigData
class EtherInt(SimObject):
type = 'EtherInt'
@@ -84,6 +84,26 @@ class EtherDevBase(PciDevice):
tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
rss = Param.Bool(False, "Receive Side Scaling")
+class NSGigEPciData(PciConfigData):
+ VendorID = 0x100B
+ DeviceID = 0x0022
+ Status = 0x0290
+ SubClassCode = 0x00
+ ClassCode = 0x02
+ ProgIF = 0x00
+ BAR0 = 0x00000001
+ BAR1 = 0x00000000
+ BAR2 = 0x00000000
+ BAR3 = 0x00000000
+ BAR4 = 0x00000000
+ BAR5 = 0x00000000
+ MaximumLatency = 0x34
+ MinimumGrant = 0xb0
+ InterruptLine = 0x1e
+ InterruptPin = 0x01
+ BAR0Size = '256B'
+ BAR1Size = '4kB'
+
class NSGigE(EtherDevBase):
type = 'NSGigE'
@@ -91,11 +111,32 @@ class NSGigE(EtherDevBase):
dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
+ configdata = NSGigEPciData()
+
class NSGigEInt(EtherInt):
type = 'NSGigEInt'
device = Param.NSGigE("Ethernet device of this interface")
+class SinicPciData(PciConfigData):
+ VendorID = 0x1291
+ DeviceID = 0x1293
+ Status = 0x0290
+ SubClassCode = 0x00
+ ClassCode = 0x02
+ ProgIF = 0x00
+ BAR0 = 0x00000000
+ BAR1 = 0x00000000
+ BAR2 = 0x00000000
+ BAR3 = 0x00000000
+ BAR4 = 0x00000000
+ BAR5 = 0x00000000
+ MaximumLatency = 0x34
+ MinimumGrant = 0xb0
+ InterruptLine = 0x1e
+ InterruptPin = 0x01
+ BAR0Size = '64kB'
+
class Sinic(EtherDevBase):
type = 'Sinic'
@@ -111,6 +152,8 @@ class Sinic(EtherDevBase):
delay_copy = Param.Bool(False, "Delayed copy transmit")
virtual_addr = Param.Bool(False, "Virtual addressing")
+ configdata = SinicPciData()
+
class SinicInt(EtherInt):
type = 'SinicInt'
device = Param.Sinic("Ethernet device of this interface")
diff --git a/src/python/m5/objects/Ide.py b/src/python/m5/objects/Ide.py
index 9ee578177..a5fe1b595 100644
--- a/src/python/m5/objects/Ide.py
+++ b/src/python/m5/objects/Ide.py
@@ -1,8 +1,31 @@
from m5.config import *
-from Pci import PciDevice
+from Pci import PciDevice, PciConfigData
class IdeID(Enum): vals = ['master', 'slave']
+class IdeControllerPciData(PciConfigData):
+ VendorID = 0x8086
+ DeviceID = 0x7111
+ Command = 0x0
+ Status = 0x280
+ Revision = 0x0
+ ClassCode = 0x01
+ SubClassCode = 0x01
+ ProgIF = 0x85
+ BAR0 = 0x00000001
+ BAR1 = 0x00000001
+ BAR2 = 0x00000001
+ BAR3 = 0x00000001
+ BAR4 = 0x00000001
+ BAR5 = 0x00000001
+ InterruptLine = 0x1f
+ InterruptPin = 0x01
+ BAR0Size = '8B'
+ BAR1Size = '4B'
+ BAR2Size = '8B'
+ BAR3Size = '4B'
+ BAR4Size = '16B'
+
class IdeDisk(SimObject):
type = 'IdeDisk'
delay = Param.Latency('1us', "Fixed disk delay in microseconds")
@@ -12,3 +35,5 @@ class IdeDisk(SimObject):
class IdeController(PciDevice):
type = 'IdeController'
disks = VectorParam.IdeDisk("IDE disks attached to this controller")
+
+ configdata =IdeControllerPciData()
diff --git a/src/python/m5/objects/Root.py b/src/python/m5/objects/Root.py
index 373475a7a..33dd22620 100644
--- a/src/python/m5/objects/Root.py
+++ b/src/python/m5/objects/Root.py
@@ -7,7 +7,7 @@ from Debug import Debug
class Root(SimObject):
type = 'Root'
- clock = Param.RootClock('200MHz', "tick frequency")
+ clock = Param.RootClock('1THz', "tick frequency")
max_tick = Param.Tick('0', "maximum simulation ticks (0 = infinite)")
progress_interval = Param.Tick('0',
"print a progress message every n ticks (0 = never)")
diff --git a/src/python/m5/objects/Tsunami.py b/src/python/m5/objects/Tsunami.py
index 4613571d8..0b5ff9e7d 100644
--- a/src/python/m5/objects/Tsunami.py
+++ b/src/python/m5/objects/Tsunami.py
@@ -1,11 +1,10 @@
from m5.config import *
from Device import BasicPioDevice
from Platform import Platform
-
-class Tsunami(Platform):
- type = 'Tsunami'
-# pciconfig = Param.PciConfigAll("PCI configuration")
- system = Param.System(Parent.any, "system")
+from AlphaConsole import AlphaConsole
+from Uart import Uart8250
+from Pci import PciConfigAll
+from BadDevice import BadDevice
class TsunamiCChip(BasicPioDevice):
type = 'TsunamiCChip'
@@ -25,3 +24,71 @@ class TsunamiIO(BasicPioDevice):
class TsunamiPChip(BasicPioDevice):
type = 'TsunamiPChip'
tsunami = Param.Tsunami(Parent.any, "Tsunami")
+
+class Tsunami(Platform):
+ type = 'Tsunami'
+ system = Param.System(Parent.any, "system")
+
+ cchip = TsunamiCChip(pio_addr=0x801a0000000)
+ pchip = TsunamiPChip(pio_addr=0x80180000000)
+ pciconfig = PciConfigAll()
+ fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
+
+ fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
+ fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
+ fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
+ fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
+
+ fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
+
+ fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
+
+ fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
+ fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
+ fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
+ fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
+ fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
+ fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
+ fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
+ fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
+ fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
+ fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
+
+ fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
+ fake_ata1 = IsaFake(pio_addr=0x801fc000170)
+
+ fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
+ io = TsunamiIO(pio_addr=0x801fc000000)
+ uart = Uart8250(pio_addr=0x801fc0003f8)
+ console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
+
+ # Attach I/O devices to specified bus object. Can't do this
+ # earlier, since the bus object itself is typically defined at the
+ # System level.
+ def attachIO(self, bus):
+ self.cchip.pio = bus.port
+ self.pchip.pio = bus.port
+ self.pciconfig.pio = bus.default
+ self.fake_sm_chip.pio = bus.port
+ self.fake_uart1.pio = bus.port
+ self.fake_uart2.pio = bus.port
+ self.fake_uart3.pio = bus.port
+ self.fake_uart4.pio = bus.port
+ self.fake_ppc.pio = bus.port
+ self.fake_OROM.pio = bus.port
+ self.fake_pnp_addr.pio = bus.port
+ self.fake_pnp_write.pio = bus.port
+ self.fake_pnp_read0.pio = bus.port
+ self.fake_pnp_read1.pio = bus.port
+ self.fake_pnp_read2.pio = bus.port
+ self.fake_pnp_read3.pio = bus.port
+ self.fake_pnp_read4.pio = bus.port
+ self.fake_pnp_read5.pio = bus.port
+ self.fake_pnp_read6.pio = bus.port
+ self.fake_pnp_read7.pio = bus.port
+ self.fake_ata0.pio = bus.port
+ self.fake_ata1.pio = bus.port
+ self.fb.pio = bus.port
+ self.io.pio = bus.port
+ self.uart.pio = bus.port
+ self.console.pio = bus.port
diff --git a/src/sim/main.cc b/src/sim/main.cc
index d0725ab37..4ea8c4138 100644
--- a/src/sim/main.cc
+++ b/src/sim/main.cc
@@ -215,7 +215,7 @@ loadIniFile(PyObject *_resolveFunc)
configStream = simout.find("config.out");
// The configuration database is now complete; start processing it.
- inifile.load("config.ini");
+ inifile.load(simout.resolve("config.ini"));
// Initialize statistics database
Stats::InitSimStats();
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-13 14:30:14 +0000