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-rw-r--r--src/SConscript1
-rw-r--r--src/cpu/base.cc1
-rw-r--r--src/cpu/base.hh1
-rw-r--r--src/cpu/checker/cpu.hh3
-rw-r--r--src/cpu/checker/cpu_impl.hh2
-rw-r--r--src/cpu/o3/cpu.cc6
-rw-r--r--src/cpu/o3/cpu.hh5
-rw-r--r--src/cpu/o3/fetch.hh2
-rw-r--r--src/cpu/ozone/cpu.hh5
-rw-r--r--src/cpu/ozone/cpu_impl.hh6
-rw-r--r--src/cpu/simple/base.cc1
-rw-r--r--src/cpu/simple/base.hh6
-rw-r--r--src/sim/pseudo_inst.cc4
-rw-r--r--src/sim/sim_object.cc1
14 files changed, 8 insertions, 36 deletions
diff --git a/src/SConscript b/src/SConscript
index 0d0cb2486..9825cafe7 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -89,7 +89,6 @@ base_sources = Split('''
cpu/pc_event.cc
cpu/quiesce_event.cc
cpu/static_inst.cc
- cpu/sampler/sampler.cc
cpu/simple_thread.cc
cpu/thread_state.cc
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index 40cec416b..0b9c80591 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -41,7 +41,6 @@
#include "cpu/cpuevent.hh"
#include "cpu/thread_context.hh"
#include "cpu/profile.hh"
-#include "cpu/sampler/sampler.hh"
#include "sim/param.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 51f3bb905..5256a411f 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -36,7 +36,6 @@
#include "base/statistics.hh"
#include "config/full_system.hh"
-#include "cpu/sampler/sampler.hh"
#include "sim/eventq.hh"
#include "sim/sim_object.hh"
#include "arch/isa_traits.hh"
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index 785387e60..b520e1be0 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -66,7 +66,6 @@ class ThreadContext;
class MemInterface;
class Checkpoint;
class Request;
-class Sampler;
/**
* CheckerCPU class. Dynamically verifies instructions as they are
@@ -374,7 +373,7 @@ class Checker : public CheckerCPU
: CheckerCPU(p)
{ }
- void switchOut(Sampler *s);
+ void switchOut();
void takeOverFrom(BaseCPU *oldCPU);
void verify(DynInstPtr &inst);
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 7c1efb0b1..81f97726c 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -293,7 +293,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
template <class DynInstPtr>
void
-Checker<DynInstPtr>::switchOut(Sampler *s)
+Checker<DynInstPtr>::switchOut()
{
instList.clear();
}
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index feca4cdf2..fb7739db8 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -714,9 +714,8 @@ FullO3CPU<Impl>::haltContext(int tid)
template <class Impl>
void
-FullO3CPU<Impl>::switchOut(Sampler *_sampler)
+FullO3CPU<Impl>::switchOut()
{
- sampler = _sampler;
switchCount = 0;
fetch.switchOut();
decode.switchOut();
@@ -745,12 +744,11 @@ FullO3CPU<Impl>::signalSwitched()
#if USE_CHECKER
if (checker)
- checker->switchOut(sampler);
+ checker->switchOut();
#endif
if (tickEvent.scheduled())
tickEvent.squash();
- sampler->signalSwitched();
_status = SwitchedOut;
}
assert(switchCount <= 5);
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 1cff6142d..bd0451601 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -271,7 +271,7 @@ class FullO3CPU : public BaseO3CPU
virtual void syscall(int tid) { panic("Unimplemented!"); }
/** Switches out this CPU. */
- void switchOut(Sampler *sampler);
+ void switchOut();
/** Signals to this CPU that a stage has completed switching out. */
void signalSwitched();
@@ -550,9 +550,6 @@ class FullO3CPU : public BaseO3CPU
/** Pointer to memory. */
MemObject *mem;
- /** Pointer to the sampler */
- Sampler *sampler;
-
/** Counter of how many stages have completed switching out. */
int switchCount;
diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 7fcd21b7d..848ebf39e 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -40,8 +40,6 @@
#include "mem/port.hh"
#include "sim/eventq.hh"
-class Sampler;
-
/**
* DefaultFetch class handles both single threaded and SMT fetch. Its
* width is specified by the parameters; each cycle it tries to fetch
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index f726ac99b..8993781ea 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -55,7 +55,6 @@ class AlphaDTB;
class PhysicalMemory;
class MemoryController;
-class Sampler;
class RemoteGDB;
class GDBListener;
@@ -356,12 +355,10 @@ class OzoneCPU : public BaseCPU
int cpuId;
- void switchOut(Sampler *sampler);
+ void switchOut();
void signalSwitched();
void takeOverFrom(BaseCPU *oldCPU);
- Sampler *sampler;
-
int switchCount;
#if FULL_SYSTEM
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 2cdc8a3da..ccb1c8418 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -244,9 +244,8 @@ OzoneCPU<Impl>::~OzoneCPU()
template <class Impl>
void
-OzoneCPU<Impl>::switchOut(Sampler *_sampler)
+OzoneCPU<Impl>::switchOut()
{
- sampler = _sampler;
switchCount = 0;
// Front end needs state from back end, so switch out the back end first.
backEnd->switchOut();
@@ -262,13 +261,12 @@ OzoneCPU<Impl>::signalSwitched()
frontEnd->doSwitchOut();
#if USE_CHECKER
if (checker)
- checker->switchOut(sampler);
+ checker->switchOut();
#endif
_status = SwitchedOut;
if (tickEvent.scheduled())
tickEvent.squash();
- sampler->signalSwitched();
}
assert(switchCount <= 2);
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index db5dd2acf..a50541189 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -41,7 +41,6 @@
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/profile.hh"
-#include "cpu/sampler/sampler.hh"
#include "cpu/simple/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/smt.hh"
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 39bc86050..57cfa3c2c 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -38,7 +38,6 @@
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/pc_event.hh"
-#include "cpu/sampler/sampler.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "mem/port.hh"
@@ -128,11 +127,6 @@ class BaseSimpleCPU : public BaseCPU
// Static data storage
TheISA::IntReg dataReg;
- // Pointer to the sampler that is telling us to switchover.
- // Used to signal the completion of the pipe drain and schedule
- // the next switchover
- Sampler *sampler;
-
StaticInstPtr curStaticInst;
void checkForInterrupts();
diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc
index b2854e491..dc08e6c06 100644
--- a/src/sim/pseudo_inst.cc
+++ b/src/sim/pseudo_inst.cc
@@ -52,8 +52,6 @@
using namespace std;
-extern Sampler *SampCPU;
-
using namespace Stats;
using namespace TheISA;
@@ -280,7 +278,5 @@ namespace AlphaPseudo
void switchcpu(ThreadContext *tc)
{
- if (SampCPU)
- SampCPU->switchCPUs();
}
}
diff --git a/src/sim/sim_object.cc b/src/sim/sim_object.cc
index 4205b5762..655bdcf4e 100644
--- a/src/sim/sim_object.cc
+++ b/src/sim/sim_object.cc
@@ -37,7 +37,6 @@
#include "base/misc.hh"
#include "base/trace.hh"
#include "base/stats/events.hh"
-#include "base/serializer.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
#include "sim/stats.hh"
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 11:19:44 +0000