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-rw-r--r--src/arch/arm/vtophys.hh1
-rw-r--r--src/arch/mips/vtophys.hh1
-rw-r--r--src/arch/power/vtophys.hh1
-rw-r--r--src/arch/sparc/vtophys.hh4
-rw-r--r--src/cpu/inorder/thread_context.hh2
-rwxr-xr-xsrc/cpu/o3/thread_context.hh2
-rw-r--r--src/cpu/simple_thread.hh2
-rw-r--r--src/kern/solaris/solaris.hh2
-rw-r--r--src/mem/ruby/system/RubyPort.cc3
-rw-r--r--src/mem/ruby/system/RubyPort.hh2
10 files changed, 2 insertions, 18 deletions
diff --git a/src/arch/arm/vtophys.hh b/src/arch/arm/vtophys.hh
index a85209a4a..12a6c6ec6 100644
--- a/src/arch/arm/vtophys.hh
+++ b/src/arch/arm/vtophys.hh
@@ -38,7 +38,6 @@
#include "arch/arm/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace ArmISA {
inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index 37a7378a8..a3fbdd457 100644
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -38,7 +38,6 @@
#include "arch/mips/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace MipsISA {
Addr vtophys(Addr vaddr);
diff --git a/src/arch/power/vtophys.hh b/src/arch/power/vtophys.hh
index a2582b296..51696d9b2 100644
--- a/src/arch/power/vtophys.hh
+++ b/src/arch/power/vtophys.hh
@@ -40,7 +40,6 @@
#include "arch/power/utility.hh"
class ThreadContext;
-class FunctionalPort;
namespace PowerISA {
diff --git a/src/arch/sparc/vtophys.hh b/src/arch/sparc/vtophys.hh
index f55967b53..7c1d23e80 100644
--- a/src/arch/sparc/vtophys.hh
+++ b/src/arch/sparc/vtophys.hh
@@ -36,13 +36,9 @@
#include "arch/sparc/pagetable.hh"
class ThreadContext;
-class FunctionalPort;
namespace SparcISA {
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
-
Addr vtophys(Addr vaddr);
Addr vtophys(ThreadContext *tc, Addr vaddr);
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 7fe0fb5ef..5a9cfce32 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -44,8 +44,6 @@ namespace Kernel {
class Statistics;
};
-class TranslatingPort;
-
/**
* Derived ThreadContext class for use with the InOrderCPU. It
* provides the interface for any external objects to access a
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index ff6ca0093..ffe828c94 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -40,8 +40,6 @@ namespace Kernel {
class Statistics;
};
-class TranslatingPort;
-
/**
* Derived ThreadContext class for use with the O3CPU. It
* provides the interface for any external objects to access a
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index f2132dc36..97964c0e8 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -57,8 +57,6 @@ class BaseCPU;
class FunctionProfile;
class ProfileNode;
-class PhysicalPort;
-class TranslatingPort;
namespace TheISA {
namespace Kernel {
diff --git a/src/kern/solaris/solaris.hh b/src/kern/solaris/solaris.hh
index da6ce84f7..9cd5af16f 100644
--- a/src/kern/solaris/solaris.hh
+++ b/src/kern/solaris/solaris.hh
@@ -34,8 +34,6 @@
#include "base/types.hh"
#include "kern/operatingsystem.hh"
-class TranslatingPort;
-
///
/// This class encapsulates the types, structures, constants,
/// functions, and syscall-number mappings specific to the Solaris
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc
index b60ca2a07..af414f17a 100644
--- a/src/mem/ruby/system/RubyPort.cc
+++ b/src/mem/ruby/system/RubyPort.cc
@@ -88,8 +88,7 @@ RubyPort::getPort(const std::string &if_name, int idx)
// RubyPort should only have one port to physical memory
assert (physMemPort == NULL);
- physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
- ruby_system, access_phys_mem);
+ physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this);
return physMemPort;
}
diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh
index 2ffdef3d9..6df713a13 100644
--- a/src/mem/ruby/system/RubyPort.hh
+++ b/src/mem/ruby/system/RubyPort.hh
@@ -155,7 +155,7 @@ class RubyPort : public MemObject
uint16_t m_port_id;
uint64_t m_request_cnt;
- M5Port* physMemPort;
+ PioPort* physMemPort;
/*! Vector of CPU Port attached to this Ruby port. */
typedef std::vector<M5Port*>::iterator CpuPortIter;