diff options
Diffstat (limited to 'src')
-rw-r--r-- | src/arch/alpha/isa/decoder.isa | 34 | ||||
-rw-r--r-- | src/sim/pseudo_inst.cc | 21 | ||||
-rw-r--r-- | src/sim/pseudo_inst.hh | 3 |
3 files changed, 23 insertions, 35 deletions
diff --git a/src/arch/alpha/isa/decoder.isa b/src/arch/alpha/isa/decoder.isa index 2177e8c4f..dc30039b2 100644 --- a/src/arch/alpha/isa/decoder.isa +++ b/src/arch/alpha/isa/decoder.isa @@ -806,14 +806,15 @@ decode OPCODE default Unknown::unknown() { 0x04: quiesceTime({{ R0 = PseudoInst::quiesceTime(xc->tcBase()); }}, IsNonSpeculative, IsUnverifiable); - 0x10: ivlb({{ - warn_once("Obsolete M5 instruction ivlb encountered.\n"); + 0x10: deprecated_ivlb({{ + warn_once("Obsolete M5 ivlb instruction encountered.\n"); }}); - 0x11: ivle({{ - warn_once("Obsolete M5 instruction ivlb encountered.\n"); + 0x11: deprecated_ivle({{ + warn_once("Obsolete M5 ivlb instruction encountered.\n"); }}); - 0x20: m5exit_old({{ - PseudoInst::m5exit_old(xc->tcBase()); + 0x20: deprecated_exit ({{ + warn_once("deprecated M5 exit instruction encountered.\n"); + PseudoInst::m5exit(xc->tcBase(), 0); }}, No_OpClass, IsNonSpeculative); 0x21: m5exit({{ PseudoInst::m5exit(xc->tcBase(), R16); @@ -821,7 +822,9 @@ decode OPCODE default Unknown::unknown() { 0x31: loadsymbol({{ PseudoInst::loadsymbol(xc->tcBase()); }}, No_OpClass, IsNonSpeculative); - 0x30: initparam({{ Ra = xc->tcBase()->getCpuPtr()->system->init_param; }}); + 0x30: initparam({{ + Ra = xc->tcBase()->getCpuPtr()->system->init_param; + }}); 0x40: resetstats({{ PseudoInst::resetstats(xc->tcBase(), R16, R17); }}, IsNonSpeculative); @@ -849,11 +852,20 @@ decode OPCODE default Unknown::unknown() { 0x54: m5panic({{ panic("M5 panic instruction called at pc=%#x.", xc->readPC()); }}, IsNonSpeculative); - 0x55: m5anBegin({{ - PseudoInst::anBegin(xc->tcBase(), R16); + 0x55: m5reserved1({{ + warn("M5 reserved opcode ignored"); + }}, IsNonSpeculative); + 0x56: m5reserved2({{ + warn("M5 reserved opcode ignored"); + }}, IsNonSpeculative); + 0x57: m5reserved3({{ + warn("M5 reserved opcode ignored"); + }}, IsNonSpeculative); + 0x58: m5reserved4({{ + warn("M5 reserved opcode ignored"); }}, IsNonSpeculative); - 0x56: m5anWait({{ - PseudoInst::anWait(xc->tcBase(), R16, R17); + 0x59: m5reserved5({{ + warn("M5 reserved opcode ignored"); }}, IsNonSpeculative); } } diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index ec384a4c5..60a74b224 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -124,12 +124,6 @@ quiesceTime(ThreadContext *tc) } void -m5exit_old(ThreadContext *tc) -{ - exitSimLoop("m5_exit_old instruction encountered"); -} - -void m5exit(ThreadContext *tc, Tick delay) { Tick when = curTick + delay * Clock::Int::ns; @@ -223,21 +217,6 @@ addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr) } void -anBegin(ThreadContext *tc, uint64_t cur) -{ - Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur & - 0xFFFFFFFF, 0,0); -} - -void -anWait(ThreadContext *tc, uint64_t cur, uint64_t wait) -{ - Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur & - 0xFFFFFFFF, wait >> 32, wait & 0xFFFFFFFF); -} - - -void dumpresetstats(ThreadContext *tc, Tick delay, Tick period) { if (!tc->getCpuPtr()->params->do_statistics_insts) diff --git a/src/sim/pseudo_inst.hh b/src/sim/pseudo_inst.hh index d94b358e5..40702fced 100644 --- a/src/sim/pseudo_inst.hh +++ b/src/sim/pseudo_inst.hh @@ -48,7 +48,6 @@ void quiesceNs(ThreadContext *tc, uint64_t ns); void quiesceCycles(ThreadContext *tc, uint64_t cycles); uint64_t quiesceTime(ThreadContext *tc); void m5exit(ThreadContext *tc, Tick delay); -void m5exit_old(ThreadContext *tc); void loadsymbol(ThreadContext *xc); void resetstats(ThreadContext *tc, Tick delay, Tick period); void dumpstats(ThreadContext *tc, Tick delay, Tick period); @@ -59,7 +58,5 @@ uint64_t readfile(ThreadContext *tc, Addr vaddr, uint64_t len, void debugbreak(ThreadContext *tc); void switchcpu(ThreadContext *tc); void addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr); -void anBegin(ThreadContext *tc, uint64_t cur); -void anWait(ThreadContext *tc, uint64_t cur, uint64_t wait); /* namespace PsuedoInst */ } |