diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/mem/bus.cc | 5 | ||||
| -rw-r--r-- | src/mem/cache/cache_impl.hh | 2 | ||||
| -rw-r--r-- | src/mem/cache/miss/mshr.cc | 2 | ||||
| -rw-r--r-- | src/mem/tport.cc | 1 |
4 files changed, 4 insertions, 6 deletions
diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 42c4431bb..620e2ac60 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -148,10 +148,7 @@ void Bus::occupyBus(PacketPtr pkt) // The first word will be delivered after the current tick, the delivery // of the address if any, and one bus cycle to deliver the data - pkt->firstWordTime = - tickNextIdle + - pkt->isRequest() ? clock : 0 + - clock; + pkt->firstWordTime = tickNextIdle + (pkt->isRequest() ? clock : 0) + clock; //Advance it numCycles bus cycles. //XXX Should this use the repeated addition trick as well? diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh index 402e34db2..02e951df4 100644 --- a/src/mem/cache/cache_impl.hh +++ b/src/mem/cache/cache_impl.hh @@ -736,7 +736,7 @@ Cache<TagStore>::handleResponse(PacketPtr pkt) // If critical word (no offset) return first word time completion_time = tags->getHitLatency() + - transfer_offset ? pkt->finishTime : pkt->firstWordTime; + (transfer_offset ? pkt->finishTime : pkt->firstWordTime); assert(!target->pkt->req->isUncacheable()); missLatency[target->pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc index 7796773a3..4e9b98481 100644 --- a/src/mem/cache/miss/mshr.cc +++ b/src/mem/cache/miss/mshr.cc @@ -263,7 +263,7 @@ MSHR::handleSnoop(PacketPtr pkt, Counter _order) if (targets->needsExclusive || pkt->needsExclusive()) { // actual target device (typ. PhysicalMemory) will delete the // packet on reception, so we need to save a copy here - PacketPtr cp_pkt = new Packet(pkt); + PacketPtr cp_pkt = new Packet(pkt, true); targets->add(cp_pkt, curTick, _order, false); ++ntargets; diff --git a/src/mem/tport.cc b/src/mem/tport.cc index b1a6a4813..9fa27046b 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -95,6 +95,7 @@ void SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when) { assert(when > curTick); + assert(when < curTick + Clock::Int::ms); // Nothing is on the list: add it and schedule an event if (transmitList.empty() || when < transmitList.front().tick) { |