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-rw-r--r--src/cpu/static_inst.hh27
-rw-r--r--src/mem/bus.hh42
2 files changed, 33 insertions, 36 deletions
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index c4a29da59..2e1ebd766 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -597,19 +597,20 @@ StaticInst::decode(StaticInst::ExtMachInst mach_inst, Addr addr)
Addr page_addr = addr & ~(TheISA::PageBytes - 1);
// checks recently decoded addresses
- if (recentDecodes[0].decodePage) {
- if (page_addr == recentDecodes[0].page_addr) {
- if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
- return recentDecodes[0].decodePage->getInst(addr);
-
- return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
- } else if (recentDecodes[1].decodePage &&
- page_addr == recentDecodes[1].page_addr) {
- if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
- return recentDecodes[1].decodePage->getInst(addr);
-
- return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
- }
+ if (recentDecodes[0].decodePage &&
+ page_addr == recentDecodes[0].page_addr) {
+ if (recentDecodes[0].decodePage->decoded(mach_inst, addr))
+ return recentDecodes[0].decodePage->getInst(addr);
+
+ return searchCache(mach_inst, addr, recentDecodes[0].decodePage);
+ }
+
+ if (recentDecodes[1].decodePage &&
+ page_addr == recentDecodes[1].page_addr) {
+ if (recentDecodes[1].decodePage->decoded(mach_inst, addr))
+ return recentDecodes[1].decodePage->getInst(addr);
+
+ return searchCache(mach_inst, addr, recentDecodes[1].decodePage);
}
// searches the page containing the address to decode
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 32a039335..83a4f6a55 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -193,17 +193,17 @@ class Bus : public MemObject
// Checks the cache and returns the id of the port that has the requested
// address within its range
inline int checkPortCache(Addr addr) {
- if (portCache[0].valid) {
- if (addr >= portCache[0].start && addr < portCache[0].end) {
- return portCache[0].id;
- } else if (portCache[1].valid) {
- if (addr >= portCache[1].start && addr < portCache[1].end) {
- return portCache[1].id;
- } else if (portCache[2].valid && addr >= portCache[2].start &&
- addr < portCache[2].end) {
- return portCache[2].id;
- }
- }
+ if (portCache[0].valid && addr >= portCache[0].start &&
+ addr < portCache[0].end) {
+ return portCache[0].id;
+ }
+ if (portCache[1].valid && addr >= portCache[1].start &&
+ addr < portCache[1].end) {
+ return portCache[1].id;
+ }
+ if (portCache[2].valid && addr >= portCache[2].start &&
+ addr < portCache[2].end) {
+ return portCache[2].id;
}
return -1;
@@ -312,17 +312,14 @@ class Bus : public MemObject
// Checks the peer port interfaces cache for the port id and returns
// a pointer to the matching port
inline BusPort* checkBusCache(short id) {
- if (busCache[0].valid) {
- if (id == busCache[0].id) {
- return busCache[0].port;
- if (busCache[1].valid) {
- if (id == busCache[1].id) {
- return busCache[1].port;
- if (busCache[2].valid && id == busCache[2].id)
- return busCache[2].port;
- }
- }
- }
+ if (busCache[0].valid && id == busCache[0].id) {
+ return busCache[0].port;
+ }
+ if (busCache[1].valid && id == busCache[1].id) {
+ return busCache[1].port;
+ }
+ if (busCache[2].valid && id == busCache[2].id) {
+ return busCache[2].port;
}
return NULL;
@@ -345,7 +342,6 @@ class Bus : public MemObject
// Invalidates the cache. Needs to be called in constructor.
inline void clearBusCache() {
- // memset(busCache, 0, 3 * sizeof(BusCache));
busCache[2].valid = false;
busCache[1].valid = false;
busCache[0].valid = false;