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-rw-r--r--src/arch/x86/isa.cc59
-rw-r--r--src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py3
-rw-r--r--src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py3
3 files changed, 49 insertions, 16 deletions
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index f2d3ce42a..f9b99db0f 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -129,11 +129,13 @@ ISA::readMiscRegNoEffect(int miscReg) const
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
// attempt to read them directly.
- assert( miscReg != MISCREG_CR1 &&
- !(miscReg > MISCREG_CR4 &&
- miscReg < MISCREG_CR8) &&
- !(miscReg > MISCREG_CR8 &&
- miscReg <= MISCREG_CR15));
+ assert(miscReg >= MISCREG_CR0 &&
+ miscReg < NUM_MISCREGS &&
+ miscReg != MISCREG_CR1 &&
+ !(miscReg > MISCREG_CR4 &&
+ miscReg < MISCREG_CR8) &&
+ !(miscReg > MISCREG_CR8 &&
+ miscReg <= MISCREG_CR15));
return regVal[miscReg];
}
@@ -160,11 +162,48 @@ ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
// Make sure we're not dealing with an illegal control register.
// Instructions should filter out these indexes, and nothing else should
// attempt to write to them directly.
- assert( miscReg != MISCREG_CR1 &&
- !(miscReg > MISCREG_CR4 &&
- miscReg < MISCREG_CR8) &&
- !(miscReg > MISCREG_CR8 &&
- miscReg <= MISCREG_CR15));
+ assert(miscReg >= MISCREG_CR0 &&
+ miscReg < NUM_MISCREGS &&
+ miscReg != MISCREG_CR1 &&
+ !(miscReg > MISCREG_CR4 &&
+ miscReg < MISCREG_CR8) &&
+ !(miscReg > MISCREG_CR8 &&
+ miscReg <= MISCREG_CR15));
+
+ HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG);
+ switch (miscReg) {
+ case MISCREG_FSW:
+ val &= (1ULL << 16) - 1;
+ regVal[miscReg] = val;
+ miscReg = MISCREG_X87_TOP;
+ val <<= 11;
+ case MISCREG_X87_TOP:
+ val &= (1ULL << 3) - 1;
+ break;
+ case MISCREG_FTW:
+ val &= (1ULL << 8) - 1;
+ break;
+ case MISCREG_FCW:
+ case MISCREG_FOP:
+ val &= (1ULL << 16) - 1;
+ break;
+ case MISCREG_MXCSR:
+ val &= (1ULL << 32) - 1;
+ break;
+ case MISCREG_FISEG:
+ case MISCREG_FOSEG:
+ if (m5Reg.submode != SixtyFourBitMode)
+ val &= (1ULL << 16) - 1;
+ break;
+ case MISCREG_FIOFF:
+ case MISCREG_FOOFF:
+ if (m5Reg.submode != SixtyFourBitMode)
+ val &= (1ULL << 32) - 1;
+ break;
+ default:
+ break;
+ }
+
regVal[miscReg] = val;
}
diff --git a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
index 1017d519f..2b9ad756e 100644
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
@@ -122,9 +122,6 @@ fxrstorCommonTemplate = """
# FSW includes TOP when read
ld t1, seg, %(mode)s, "DISPLACEMENT + 2", dataSize=2
wrval fsw, t1
- srli t1, t1, 11, dataSize=2
- andi t1, t1, 0x7, dataSize=2
- wrval "InstRegIndex(MISCREG_X87_TOP)", t1
# FTW
ld t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=1
diff --git a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
index 44c44062b..20ecff43a 100644
--- a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
+++ b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
@@ -36,9 +36,6 @@ fldenvTemplate = """
ld t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=2
wrval fsw, t1
- srli t1, t1, 11, dataSize=2
- andi t1, t1, 0x7, dataSize=2
- wrval "InstRegIndex(MISCREG_X87_TOP)", t1
ld t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=2
wrval ftw, t1