diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/arch/mips/isa/decoder.isa | 6 | ||||
| -rw-r--r-- | src/arch/mips/isa_traits.hh | 2 | ||||
| -rw-r--r-- | src/arch/mips/regfile/int_regfile.cc | 35 | ||||
| -rw-r--r-- | src/arch/mips/regfile/int_regfile.hh | 3 | ||||
| -rwxr-xr-x | src/arch/mips/regfile/misc_regfile.cc | 2 |
5 files changed, 27 insertions, 21 deletions
diff --git a/src/arch/mips/isa/decoder.isa b/src/arch/mips/isa/decoder.isa index 0a12c4f6e..8af504e55 100644 --- a/src/arch/mips/isa/decoder.isa +++ b/src/arch/mips/isa/decoder.isa @@ -603,7 +603,8 @@ decode OPCODE_HI default Unknown::unknown() { 0xA: rdpgpr({{ if(Config_AR >= 1) { // Rev 2 of the architecture - Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS); + panic("Shadow Sets Not Fully Implemented.\n"); + //Rd = xc->tcBase()->readIntReg(RT + NumIntRegs * SRSCtl_PSS); } else { @@ -613,7 +614,8 @@ decode OPCODE_HI default Unknown::unknown() { 0xE: wrpgpr({{ if(Config_AR >= 1) { // Rev 2 of the architecture - xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt); + panic("Shadow Sets Not Fully Implemented.\n"); + //xc->tcBase()->setIntReg(RD + NumIntRegs * SRSCtl_PSS,Rt); // warn("Writing %d to %d, PSS: %d, SRS: %x\n",Rt,RD + NumIntRegs * SRSCtl_PSS, SRSCtl_PSS,SRSCtl); } else diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh index d4d1de479..3450c273e 100644 --- a/src/arch/mips/isa_traits.hh +++ b/src/arch/mips/isa_traits.hh @@ -181,6 +181,8 @@ namespace MipsISA const int NumIntRegs = NumIntArchRegs*NumShadowRegSets + NumIntSpecialRegs; //HI & LO Regs const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// + const int TotalArchRegs = NumIntArchRegs * NumShadowRegSets; + // Static instruction parameters const int MaxInstSrcRegs = 10; const int MaxInstDestRegs = 8; diff --git a/src/arch/mips/regfile/int_regfile.cc b/src/arch/mips/regfile/int_regfile.cc index 4ffbcdfb8..88de4be94 100644 --- a/src/arch/mips/regfile/int_regfile.cc +++ b/src/arch/mips/regfile/int_regfile.cc @@ -44,6 +44,12 @@ IntRegFile::clear() currShadowSet=0; } +int +IntRegFile::readShadowSet() +{ + return currShadowSet; +} + void IntRegFile::setShadowSet(int css) { @@ -54,21 +60,17 @@ IntRegFile::setShadowSet(int css) IntReg IntRegFile::readReg(int intReg) { - if (intReg < NumIntRegs) { + if (intReg < NumIntArchRegs) { // Regular GPR Read DPRINTF(MipsPRA, "Reading Reg: %d, CurrShadowSet: %d\n", intReg, - currShadowSet); + currShadowSet); - if (intReg >= NumIntArchRegs * NumShadowRegSets) { - return regs[intReg + NumIntRegs * currShadowSet]; - } else { - int index = intReg + NumIntArchRegs * currShadowSet; - index = index % NumIntArchRegs; - return regs[index]; - } + return regs[intReg + NumIntArchRegs * currShadowSet]; } else { - // Read from shadow GPR .. probably called by RDPGPR - return regs[intReg]; + unsigned special_reg_num = intReg - NumIntArchRegs; + + // Read A Special Reg + return regs[TotalArchRegs + special_reg_num]; } } @@ -76,13 +78,12 @@ Fault IntRegFile::setReg(int intReg, const IntReg &val) { if (intReg != ZeroReg) { - if (intReg < NumIntRegs) { - if (intReg >= NumIntArchRegs * NumShadowRegSets) - regs[intReg] = val; - else - regs[intReg + NumIntRegs * currShadowSet] = val; + if (intReg < NumIntArchRegs) { + regs[intReg + NumIntArchRegs * currShadowSet] = val; } else { - regs[intReg] = val; + unsigned special_reg_num = intReg - NumIntArchRegs; + + regs[TotalArchRegs + special_reg_num] = val; } } diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh index 8ddd276e6..0f453a382 100644 --- a/src/arch/mips/regfile/int_regfile.hh +++ b/src/arch/mips/regfile/int_regfile.hh @@ -48,7 +48,7 @@ namespace MipsISA } enum MiscIntRegNums { - LO = NumIntArchRegs*NumShadowRegSets, + LO = NumIntArchRegs, HI, DSPACX0, DSPLo1, @@ -72,6 +72,7 @@ namespace MipsISA int currShadowSet; public: void clear(); + int readShadowSet(); void setShadowSet(int css); IntReg readReg(int intReg); Fault setReg(int intReg, const IntReg &val); diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc index e81f940f5..06523a8c9 100755 --- a/src/arch/mips/regfile/misc_regfile.cc +++ b/src/arch/mips/regfile/misc_regfile.cc @@ -40,7 +40,7 @@ #include "cpu/base.hh" #include "cpu/exetrace.hh" -#include "params/DerivO3CPU.hh" +//#include "params/DerivO3CPU.hh" using namespace std; |