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-rw-r--r--src/cpu/simple/timing.cc4
-rw-r--r--src/mem/packet.cc8
-rw-r--r--src/mem/packet.hh1
3 files changed, 6 insertions, 7 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index b86d4b2d7..4451dfe81 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -730,7 +730,9 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
traceData = NULL;
}
- if (pkt->isRead() && pkt->isLocked()) {
+ // the locked flag may be cleared on the response packet, so check
+ // pkt->req and not pkt to see if it was a load-locked
+ if (pkt->isRead() && pkt->req->isLocked()) {
TheISA::handleLockedRead(thread, pkt->req);
}
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index f3bd06f36..35fd44e5b 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -101,12 +101,10 @@ MemCmd::commandInfo[] =
/* ReadExResp */
{ SET4(IsRead, NeedsExclusive, IsResponse, HasData),
InvalidCmd, "ReadExResp" },
- /* LoadLockedReq */
+ /* LoadLockedReq: note that we use plain ReadResp as response, so that
+ * we can also use ReadRespWithInvalidate when needed */
{ SET4(IsRead, IsLocked, IsRequest, NeedsResponse),
- LoadLockedResp, "LoadLockedReq" },
- /* LoadLockedResp */
- { SET4(IsRead, IsLocked, IsResponse, HasData),
- InvalidCmd, "LoadLockedResp" },
+ ReadResp, "LoadLockedReq" },
/* StoreCondReq */
{ SET6(IsWrite, NeedsExclusive, IsLocked,
IsRequest, NeedsResponse, HasData),
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index a278a3945..36aff5b42 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -81,7 +81,6 @@ class MemCmd
ReadExReq,
ReadExResp,
LoadLockedReq,
- LoadLockedResp,
StoreCondReq,
StoreCondResp,
SwapReq,