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-rw-r--r--src/dev/Ethernet.py11
-rw-r--r--src/dev/i8254xGBe.cc10
2 files changed, 8 insertions, 13 deletions
diff --git a/src/dev/Ethernet.py b/src/dev/Ethernet.py
index 670f48eac..d73d56d03 100644
--- a/src/dev/Ethernet.py
+++ b/src/dev/Ethernet.py
@@ -69,7 +69,6 @@ class EtherDevice(PciDevice):
class IGbE(EtherDevice):
# Base class for two IGbE adapters listed above
type = 'IGbE'
- #abstract = True
hardware_address = Param.EthernetAddr(NextEthernetAddr,
"Ethernet Hardware Address")
use_flow_control = Param.Bool(False,
@@ -105,20 +104,22 @@ class IGbE(EtherDevice):
wb_comp_delay = Param.Latency('10ns', "delay after desc wb occurs")
tx_read_delay = Param.Latency('0ns', "delay after tx dma read")
rx_write_delay = Param.Latency('0ns', "delay after rx dma read")
- is8257 = Param.Bool("Select between and 8254x and 8257x device")
-
+ phy_pid = Param.UInt16("Phy PID that corresponds to device ID")
+ phy_epid = Param.UInt16("Phy EPID that corresponds to device ID")
class IGbE_e1000(IGbE):
# Older Intel 8254x based gigabit ethernet adapter
# Uses Intel e1000 driver
DeviceID = 0x1075
- is8257 = False
+ phy_pid = 0x02A8
+ phy_epid = 0x0380
class IGbE_igb(IGbE):
# Newer Intel 8257x based gigabit ethernet adapter
# Uses Intel igb driver and in theory supports packet splitting and LRO
DeviceID = 0x10C9
- is8257 = True
+ phy_pid = 0x0141
+ phy_epid = 0x0CC0
class EtherDevBase(EtherDevice):
type = 'EtherDevBase'
diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc
index 2a7ba0b31..1e4fd130c 100644
--- a/src/dev/i8254xGBe.cc
+++ b/src/dev/i8254xGBe.cc
@@ -446,16 +446,10 @@ IGbE::write(PacketPtr pkt)
regs.mdic.data(0x796D); // link up
break;
case PHY_PID:
- if (params()->is8257)
- regs.mdic.data(0x0141);
- else
- regs.mdic.data(0x02A8);
+ regs.mdic.data(params()->phy_pid);
break;
case PHY_EPID:
- if (params()->is8257)
- regs.mdic.data(0x0CC0);
- else
- regs.mdic.data(0x0380);
+ regs.mdic.data(params()->phy_epid);
break;
case PHY_GSTATUS:
regs.mdic.data(0x7C00);