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-rw-r--r--src/arch/alpha/utility.hh7
-rw-r--r--src/arch/mips/utility.hh7
-rw-r--r--src/arch/sparc/SConscript1
-rw-r--r--src/arch/sparc/asi.cc279
-rw-r--r--src/arch/sparc/asi.hh55
-rw-r--r--src/cpu/checker/cpu_impl.hh2
-rw-r--r--src/cpu/o3/fetch_impl.hh2
-rw-r--r--src/cpu/ozone/cpu.hh4
-rw-r--r--src/cpu/ozone/cpu_impl.hh2
-rw-r--r--src/cpu/ozone/dyn_inst_impl.hh4
-rw-r--r--src/cpu/ozone/front_end_impl.hh2
-rw-r--r--src/cpu/simple/base.cc2
-rw-r--r--src/kern/linux/linux.hh4
-rw-r--r--src/kern/solaris/solaris.hh4
-rw-r--r--src/kern/tru64/tru64.hh56
15 files changed, 340 insertions, 91 deletions
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index d3ccc0444..0304d1c3a 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -37,16 +37,17 @@
#include "arch/alpha/isa_traits.hh"
#include "arch/alpha/regfile.hh"
#include "base/misc.hh"
+#include "cpu/thread_context.hh"
namespace AlphaISA
{
static inline ExtMachInst
- makeExtMI(MachInst inst, const uint64_t &pc) {
+ makeExtMI(MachInst inst, ThreadContext * xc) {
#if FULL_SYSTEM
ExtMachInst ext_inst = inst;
- if (pc && 0x1)
- return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
+ if (xc->readPC() && 0x1)
+ return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32);
else
return ext_inst;
#else
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index ae2fe1aea..56689ba4d 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -35,6 +35,7 @@
#include "arch/mips/types.hh"
#include "base/misc.hh"
#include "config/full_system.hh"
+#include "cpu/thread_context.hh"
//XXX This is needed for size_t. We should use something other than size_t
//#include "kern/linux/linux.hh"
#include "sim/host.hh"
@@ -86,11 +87,11 @@ namespace MipsISA {
}
static inline ExtMachInst
- makeExtMI(MachInst inst, const uint64_t &pc) {
+ makeExtMI(MachInst inst, ThreadContext * xc) {
#if FULL_SYSTEM
ExtMachInst ext_inst = inst;
- if (pc && 0x1)
- return ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32);
+ if (xc->readPC() && 0x1)
+ return ext_inst|=(static_cast<ExtMachInst>(xc->readPC() & 0x1) << 32);
else
return ext_inst;
#else
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 66f2b57e0..e317502e0 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -44,6 +44,7 @@ Import('env')
# Base sources used by all configurations.
base_sources = Split('''
+ asi.cc
faults.cc
floatregfile.cc
intregfile.cc
diff --git a/src/arch/sparc/asi.cc b/src/arch/sparc/asi.cc
new file mode 100644
index 000000000..00c9e041e
--- /dev/null
+++ b/src/arch/sparc/asi.cc
@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/sparc/asi.hh"
+
+namespace SparcISA
+{
+ bool AsiIsBlock(ASI asi)
+ {
+ return
+ (asi == ASI_BLK_AIUP) ||
+ (asi == ASI_BLK_AIUS) ||
+ (asi == ASI_BLK_AIUPL) ||
+ (asi == ASI_BLK_AIUSL) ||
+ (asi == ASI_BLK_P) ||
+ (asi == ASI_BLK_S) ||
+ (asi == ASI_BLK_PL) ||
+ (asi == ASI_BLK_SL);
+ }
+
+ bool AsiIsPrimary(ASI asi)
+ {
+ return
+ (asi == ASI_AIUP) ||
+ (asi == ASI_BLK_AIUP) ||
+ (asi == ASI_AIUPL) ||
+ (asi == ASI_BLK_AIUPL) ||
+ (asi == ASI_LDTX_AIUP) ||
+ (asi == ASI_LDTX_AIUPL) ||
+ (asi == ASI_P) ||
+ (asi == ASI_PNF) ||
+ (asi == ASI_PL) ||
+ (asi == ASI_PNFL) ||
+ (asi == ASI_PST8_P) ||
+ (asi == ASI_PST16_P) ||
+ (asi == ASI_PST32_P) ||
+ (asi == ASI_PST8_PL) ||
+ (asi == ASI_PST16_PL) ||
+ (asi == ASI_PST32_PL) ||
+ (asi == ASI_FL8_P) ||
+ (asi == ASI_FL16_P) ||
+ (asi == ASI_FL8_PL) ||
+ (asi == ASI_FL16_PL) ||
+ (asi == ASI_LDTX_P) ||
+ (asi == ASI_LDTX_PL) ||
+ (asi == ASI_BLK_P) ||
+ (asi == ASI_BLK_PL);
+ }
+
+ bool AsiIsSecondary(ASI asi)
+ {
+ return
+ (asi == ASI_AIUS) ||
+ (asi == ASI_BLK_AIUS) ||
+ (asi == ASI_AIUSL) ||
+ (asi == ASI_BLK_AIUSL) ||
+ (asi == ASI_LDTX_AIUS) ||
+ (asi == ASI_LDTX_AIUSL) ||
+ (asi == ASI_S) ||
+ (asi == ASI_SNF) ||
+ (asi == ASI_SL) ||
+ (asi == ASI_SNFL) ||
+ (asi == ASI_PST8_S) ||
+ (asi == ASI_PST16_S) ||
+ (asi == ASI_PST32_S) ||
+ (asi == ASI_PST8_SL) ||
+ (asi == ASI_PST16_SL) ||
+ (asi == ASI_PST32_SL) ||
+ (asi == ASI_FL8_S) ||
+ (asi == ASI_FL16_S) ||
+ (asi == ASI_FL8_SL) ||
+ (asi == ASI_FL16_SL) ||
+ (asi == ASI_LDTX_S) ||
+ (asi == ASI_LDTX_SL) ||
+ (asi == ASI_BLK_S) ||
+ (asi == ASI_BLK_SL);
+ }
+
+ bool AsiNucleus(ASI asi)
+ {
+ return
+ (asi == ASI_N) ||
+ (asi == ASI_NL) ||
+ (asi == ASI_LDTX_N) ||
+ (asi == ASI_LDTX_NL);
+ }
+
+ bool AsiIsAsIfUser(ASI asi)
+ {
+ return
+ (asi == ASI_AIUP) ||
+ (asi == ASI_AIUS) ||
+ (asi == ASI_BLK_AIUP) ||
+ (asi == ASI_BLK_AIUS) ||
+ (asi == ASI_AIUPL) ||
+ (asi == ASI_AIUSL) ||
+ (asi == ASI_BLK_AIUPL) ||
+ (asi == ASI_BLK_AIUSL) ||
+ (asi == ASI_LDTX_AIUP) ||
+ (asi == ASI_LDTX_AIUS) ||
+ (asi == ASI_LDTX_AIUPL) ||
+ (asi == ASI_LDTX_AIUSL);
+ }
+
+ bool AsiIsIO(ASI asi)
+ {
+ return
+ (asi == ASI_REAL_IO) ||
+ (asi == ASI_REAL_IO_L);
+ }
+
+ bool AsiIsReal(ASI asi)
+ {
+ return
+ (asi == ASI_REAL) ||
+ (asi == ASI_REAL_IO) ||
+ (asi == ASI_REAL_L) ||
+ (asi == ASI_REAL_IO_L) ||
+ (asi == ASI_LDTX_REAL) ||
+ (asi == ASI_LDTX_REAL_L) ||
+ (asi == ASI_MMU_REAL);
+ }
+
+ bool AsiIsLittle(ASI asi)
+ {
+ return
+ (asi == ASI_NL) ||
+ (asi == ASI_AIUPL) ||
+ (asi == ASI_AIUSL) ||
+ (asi == ASI_REAL_L) ||
+ (asi == ASI_REAL_IO_L) ||
+ (asi == ASI_BLK_AIUPL) ||
+ (asi == ASI_BLK_AIUSL) ||
+ (asi == ASI_LDTX_AIUPL) ||
+ (asi == ASI_LDTX_AIUSL) ||
+ (asi == ASI_LDTX_REAL_L) ||
+ (asi == ASI_LDTX_NL) ||
+ (asi == ASI_PL) ||
+ (asi == ASI_SL) ||
+ (asi == ASI_PNFL) ||
+ (asi == ASI_SNFL) ||
+ (asi == ASI_PST8_PL) ||
+ (asi == ASI_PST8_SL) ||
+ (asi == ASI_PST16_PL) ||
+ (asi == ASI_PST16_SL) ||
+ (asi == ASI_PST32_PL) ||
+ (asi == ASI_PST32_SL) ||
+ (asi == ASI_FL8_PL) ||
+ (asi == ASI_FL8_SL) ||
+ (asi == ASI_FL16_PL) ||
+ (asi == ASI_FL16_SL) ||
+ (asi == ASI_LDTX_PL) ||
+ (asi == ASI_LDTX_SL) ||
+ (asi == ASI_BLK_PL) ||
+ (asi == ASI_BLK_SL);
+ }
+
+ bool AsiIsTwin(ASI asi)
+ {
+ return
+ (asi == ASI_LDTX_AIUP) ||
+ (asi == ASI_LDTX_AIUS) ||
+ (asi == ASI_LDTX_REAL) ||
+ (asi == ASI_LDTX_N) ||
+ (asi == ASI_LDTX_AIUPL) ||
+ (asi == ASI_LDTX_AIUSL) ||
+ (asi == ASI_LDTX_REAL_L) ||
+ (asi == ASI_LDTX_NL) ||
+ (asi == ASI_LDTX_P) ||
+ (asi == ASI_LDTX_S) ||
+ (asi == ASI_LDTX_PL) ||
+ (asi == ASI_LDTX_SL);
+ }
+
+ bool AsiIsPartialStore(ASI asi)
+ {
+ return
+ (asi == ASI_PST8_P) ||
+ (asi == ASI_PST8_S) ||
+ (asi == ASI_PST16_P) ||
+ (asi == ASI_PST16_S) ||
+ (asi == ASI_PST32_P) ||
+ (asi == ASI_PST32_S) ||
+ (asi == ASI_PST8_PL) ||
+ (asi == ASI_PST8_SL) ||
+ (asi == ASI_PST16_PL) ||
+ (asi == ASI_PST16_SL) ||
+ (asi == ASI_PST32_PL) ||
+ (asi == ASI_PST32_SL);
+ }
+
+ bool AsiIsFloatingLoad(ASI asi)
+ {
+ return
+ (asi == ASI_FL8_P) ||
+ (asi == ASI_FL8_S) ||
+ (asi == ASI_FL16_P) ||
+ (asi == ASI_FL16_S) ||
+ (asi == ASI_FL8_PL) ||
+ (asi == ASI_FL8_SL) ||
+ (asi == ASI_FL16_PL) ||
+ (asi == ASI_FL16_SL);
+ }
+
+ bool AsiIsNoFault(ASI asi)
+ {
+ return
+ (asi == ASI_PNF) ||
+ (asi == ASI_SNF) ||
+ (asi == ASI_PNFL) ||
+ (asi == ASI_SNFL);
+ }
+
+ bool AsiIsScratchPad(ASI asi)
+ {
+ return
+ (asi == ASI_SCRATCHPAD) ||
+ (asi == ASI_HYP_SCRATCHPAD);
+ }
+
+ bool AsiIsCmt(ASI asi)
+ {
+ return
+ (asi == ASI_CMT_PER_STRAND) ||
+ (asi == ASI_CMT_SHARED);
+ }
+
+ bool AsiIsQueue(ASI asi)
+ {
+ return asi == ASI_QUEUE;
+ }
+
+ bool AsiIsDtlb(ASI asi)
+ {
+ return
+ (asi == ASI_DTLB_DATA_IN_REG) ||
+ (asi == ASI_DTLB_DATA_ACCESS_REG) ||
+ (asi == ASI_DTLB_TAG_READ_REG);
+ }
+
+ bool AsiIsMmu(ASI asi)
+ {
+ return
+ (asi == ASI_MMU_CONTEXTID) ||
+ (asi == ASI_IMMU) ||
+ (asi == ASI_MMU_REAL) ||
+ (asi == ASI_MMU) ||
+ (asi == ASI_DMMU) ||
+ (asi == ASI_UMMU) ||
+ (asi == ASI_DMMU_DEMAP);
+ }
+}
diff --git a/src/arch/sparc/asi.hh b/src/arch/sparc/asi.hh
index 482e077e0..876567225 100644
--- a/src/arch/sparc/asi.hh
+++ b/src/arch/sparc/asi.hh
@@ -156,23 +156,23 @@ namespace SparcISA
ASI_PST32_SL = 0xCD,
ASI_PST32_SECONDARY_LITTLE = ASI_PST32_SL,
//0xCE-0xCF implementation dependent
- ASI_PL8_P = 0xD0,
- ASI_PL8_PRIMARY = ASI_PL8_P,
- ASI_PL8_S = 0xD1,
- ASI_PL8_SECONDARY = ASI_PL8_S,
- ASI_PL16_P = 0xD2,
- ASI_PL16_PRIMARY = ASI_PL16_P,
- ASI_PL16_S = 0xD3,
- ASI_PL16_SECONDARY = ASI_PL16_S,
+ ASI_FL8_P = 0xD0,
+ ASI_FL8_PRIMARY = ASI_FL8_P,
+ ASI_FL8_S = 0xD1,
+ ASI_FL8_SECONDARY = ASI_FL8_S,
+ ASI_FL16_P = 0xD2,
+ ASI_FL16_PRIMARY = ASI_FL16_P,
+ ASI_FL16_S = 0xD3,
+ ASI_FL16_SECONDARY = ASI_FL16_S,
//0xD4-0xD7 implementation dependent
- ASI_PL8_PL = 0xD8,
- ASI_PL8_PRIMARY_LITTLE = ASI_PL8_PL,
- ASI_PL8_SL = 0xD9,
- ASI_PL8_SECONDARY_LITTLE = ASI_PL8_SL,
- ASI_PL16_PL = 0xDA,
- ASI_PL16_PRIMARY_LITTLE = ASI_PL16_PL,
- ASI_PL16_SL = 0xDB,
- ASI_PL16_SECONDARY_LITTLE = ASI_PL16_SL,
+ ASI_FL8_PL = 0xD8,
+ ASI_FL8_PRIMARY_LITTLE = ASI_FL8_PL,
+ ASI_FL8_SL = 0xD9,
+ ASI_FL8_SECONDARY_LITTLE = ASI_FL8_SL,
+ ASI_FL16_PL = 0xDA,
+ ASI_FL16_PRIMARY_LITTLE = ASI_FL16_PL,
+ ASI_FL16_SL = 0xDB,
+ ASI_FL16_SECONDARY_LITTLE = ASI_FL16_SL,
//0xDC-0xDF implementation dependent
//0xE0-0xE1 reserved
ASI_LDTX_P = 0xE2,
@@ -193,9 +193,30 @@ namespace SparcISA
ASI_BLK_PL = 0xF8,
ASI_BLOCK_PRIMARY_LITTLE = ASI_BLK_PL,
ASI_BLK_SL = 0xF9,
- ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL
+ ASI_BLOCK_SECONDARY_LITTLE = ASI_BLK_SL,
//0xFA-0xFF implementation dependent
+ MAX_ASI = 0xFF
};
+
+ //Functions that classify an asi
+ bool AsiIsBlock(ASI);
+ bool AsiIsPrimary(ASI);
+ bool AsiIsSecondary(ASI);
+ bool AsiIsNucleus(ASI);
+ bool AsiIsAsIfUser(ASI);
+ bool AsiIsIO(ASI);
+ bool AsiIsReal(ASI);
+ bool AsiIsLittle(ASI);
+ bool AsiIsTwin(ASI);
+ bool AsiIsPartialStore(ASI);
+ bool AsiIsFloatingLoad(ASI);
+ bool AsiIsNoFault(ASI);
+ bool AsiIsScratchPad(ASI);
+ bool AsiIsCmt(ASI);
+ bool AsiIsQueue(ASI);
+ bool AsiIsDtlb(ASI);
+ bool AsiIsMmu(ASI);
+
};
#endif // __ARCH_SPARC_TLB_HH__
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 81f97726c..48458bb1a 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -200,7 +200,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
validateInst(inst);
curStaticInst = StaticInst::decode(makeExtMI(machInst,
- thread->readPC()));
+ thread->getTC()));
#if FULL_SYSTEM
thread->setInst(machInst);
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 1e080181c..80e429ae9 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1109,7 +1109,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
inst = TheISA::gtoh(*reinterpret_cast<TheISA::MachInst *>
(&cacheData[tid][offset]));
- ext_inst = TheISA::makeExtMI(inst, fetch_PC);
+ ext_inst = TheISA::makeExtMI(inst, cpu->tcBase(tid));
// Create a new DynInst from the instruction fetched.
DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh
index e411c12bd..dd63d2e00 100644
--- a/src/cpu/ozone/cpu.hh
+++ b/src/cpu/ozone/cpu.hh
@@ -257,8 +257,8 @@ class OzoneCPU : public BaseCPU
void setFuncExeInst(Counter new_val)
{ thread->funcExeInst = new_val; }
#endif
- void changeRegFileContext(TheISA::RegFile::ContextParam param,
- TheISA::RegFile::ContextVal val)
+ void changeRegFileContext(TheISA::RegContextParam param,
+ TheISA::RegContextVal val)
{ panic("Not supported on Alpha!"); }
};
diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh
index 80f18434c..45e14b9de 100644
--- a/src/cpu/ozone/cpu_impl.hh
+++ b/src/cpu/ozone/cpu_impl.hh
@@ -35,6 +35,7 @@
#include "arch/isa_traits.hh" // For MachInst
#include "base/trace.hh"
#include "cpu/base.hh"
+#include "cpu/checker/cpu.hh"
#include "cpu/thread_context.hh"
#include "cpu/exetrace.hh"
#include "cpu/ozone/cpu.hh"
@@ -53,6 +54,7 @@
//#include "base/remote_gdb.hh"
#include "cpu/profile.hh"
#include "kern/kernel_stats.hh"
+#include "mem/physical.hh"
#include "sim/faults.hh"
#include "sim/sim_events.hh"
#include "sim/sim_exit.hh"
diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh
index ba0d70417..db1460eba 100644
--- a/src/cpu/ozone/dyn_inst_impl.hh
+++ b/src/cpu/ozone/dyn_inst_impl.hh
@@ -215,14 +215,14 @@ OzoneDynInst<Impl>::clearMemDependents()
}
template <class Impl>
-MiscReg
+TheISA::MiscReg
OzoneDynInst<Impl>::readMiscReg(int misc_reg)
{
return this->thread->readMiscReg(misc_reg);
}
template <class Impl>
-MiscReg
+TheISA::MiscReg
OzoneDynInst<Impl>::readMiscRegWithEffect(int misc_reg, Fault &fault)
{
return this->thread->readMiscRegWithEffect(misc_reg, fault);
diff --git a/src/cpu/ozone/front_end_impl.hh b/src/cpu/ozone/front_end_impl.hh
index 1b120460a..8a15378a7 100644
--- a/src/cpu/ozone/front_end_impl.hh
+++ b/src/cpu/ozone/front_end_impl.hh
@@ -842,7 +842,7 @@ FrontEnd<Impl>::getInstFromCacheline()
// Get the instruction from the array of the cache line.
inst = htog(*reinterpret_cast<MachInst *>(&cacheData[offset]));
- ExtMachInst decode_inst = TheISA::makeExtMI(inst, PC);
+ ExtMachInst decode_inst = TheISA::makeExtMI(inst, tc);
// Create a new DynInst from the instruction fetched.
DynInstPtr instruction = new DynInst(decode_inst, PC, PC+sizeof(MachInst),
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index f801b93fa..025314fcb 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -396,7 +396,7 @@ BaseSimpleCPU::preExecute()
// decode the instruction
inst = gtoh(inst);
- curStaticInst = StaticInst::decode(makeExtMI(inst, thread->readPC()));
+ curStaticInst = StaticInst::decode(makeExtMI(inst, thread->getTC()));
traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
thread->readPC());
diff --git a/src/kern/linux/linux.hh b/src/kern/linux/linux.hh
index 3a2677642..6e0b37d91 100644
--- a/src/kern/linux/linux.hh
+++ b/src/kern/linux/linux.hh
@@ -54,11 +54,11 @@ class Linux : public OperatingSystem
//@{
/// Basic Linux types.
-/* typedef uint64_t size_t;
+ typedef uint64_t size_t;
typedef uint64_t off_t;
typedef int64_t time_t;
typedef uint32_t uid_t;
- typedef uint32_t gid_t;*/
+ typedef uint32_t gid_t;
//@}
/// Stat buffer. Note that we can't call it 'stat' since that
diff --git a/src/kern/solaris/solaris.hh b/src/kern/solaris/solaris.hh
index a5ca41cdd..ed574fdbf 100644
--- a/src/kern/solaris/solaris.hh
+++ b/src/kern/solaris/solaris.hh
@@ -56,7 +56,7 @@ class Solaris : public OperatingSystem
//@{
/// Basic Solaris types.
-/* typedef uint64_t size_t;
+ typedef uint64_t size_t;
typedef uint64_t off_t;
typedef int64_t time_t;
typedef int32_t uid_t;
@@ -65,7 +65,7 @@ class Solaris : public OperatingSystem
typedef uint64_t ino_t;
typedef uint64_t dev_t;
typedef uint32_t mode_t;
- typedef uint32_t nlink_t;*/
+ typedef uint32_t nlink_t;
//@}
struct tgt_timespec {
diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh
index 87ac88007..97a5e2a7c 100644
--- a/src/kern/tru64/tru64.hh
+++ b/src/kern/tru64/tru64.hh
@@ -393,34 +393,6 @@ class Tru64 : public OperatingSystem
uint64_t pad2[2]; //!< pad2
};
- /*/// Helper function to convert a host stat buffer to a target stat
- /// buffer. Also copies the target buffer out to the simulated
- /// memory space. Used by stat(), fstat(), and lstat().
- template <class T>
- static void
- copyOutStatBuf(TranslatingPort *mem, Addr addr, global_stat *host)
- {
- using namespace TheISA;
-
- TypedBufferArg<T> tgt(addr);
-
- tgt->st_dev = htog(host->st_dev);
- tgt->st_ino = htog(host->st_ino);
- tgt->st_mode = htog(host->st_mode);
- tgt->st_nlink = htog(host->st_nlink);
- tgt->st_uid = htog(host->st_uid);
- tgt->st_gid = htog(host->st_gid);
- tgt->st_rdev = htog(host->st_rdev);
- tgt->st_size = htog(host->st_size);
- tgt->st_atimeX = htog(host->st_atime);
- tgt->st_mtimeX = htog(host->st_mtime);
- tgt->st_ctimeX = htog(host->st_ctime);
- tgt->st_blksize = htog(host->st_blksize);
- tgt->st_blocks = htog(host->st_blocks);
-
- tgt.copyOut(mem);
- }*/
-
/// Helper function to convert a host statfs buffer to a target statfs
/// buffer. Also copies the target buffer out to the simulated
/// memory space. Used by statfs() and fstatfs().
@@ -450,34 +422,6 @@ class Tru64 : public OperatingSystem
tgt.copyOut(mem);
}
-/* /// Helper function to convert a host stat buffer to an old pre-F64
- /// (4.x) target stat buffer. Also copies the target buffer out to
- /// the simulated memory space. Used by pre_F64_stat(),
- /// pre_F64_fstat(), and pre_F64_lstat().
- static void
- copyOutPreF64StatBuf(TranslatingPort *mem, Addr addr, struct stat *host)
- {
- using namespace TheISA;
-
- TypedBufferArg<Tru64::pre_F64_stat> tgt(addr);
-
- tgt->st_dev = htog(host->st_dev);
- tgt->st_ino = htog(host->st_ino);
- tgt->st_mode = htog(host->st_mode);
- tgt->st_nlink = htog(host->st_nlink);
- tgt->st_uid = htog(host->st_uid);
- tgt->st_gid = htog(host->st_gid);
- tgt->st_rdev = htog(host->st_rdev);
- tgt->st_size = htog(host->st_size);
- tgt->st_atimeX = htog(host->st_atime);
- tgt->st_mtimeX = htog(host->st_mtime);
- tgt->st_ctimeX = htog(host->st_ctime);
- tgt->st_blksize = htog(host->st_blksize);
- tgt->st_blocks = htog(host->st_blocks);
-
- tgt.copyOut(mem);
- }*/
-
/// The target system's hostname.
static const char *hostname;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 16:35:10 +0000